TWI704395B - Display apparatus - Google Patents

Abstract

A display apparatus includes pixels and a gate driver. The pixels include N pixels arranged in order, and N is a positive integer greater than or equal to 2. The N pixels include a pth pixel and a qth pixel, wherein p is an odd number less than or equal to N, p is a positive integer, q is an even number less than or equal to N , and q is a positive integer. The gate driver is electrically connected to a scan line of the pth pixel, wherein the gate driver receives a first start signal to generate a first gate pulse signal in a first sub-frame interval of a frame interval. The gate driver is electrically connected to a scan line of the qth pixel, wherein the gate driver receives a second start signal to generate a second gate pulse signal in a second sub-frame interval of the frame interval following the first sub-frame interval.

Description

Display device

The present invention relates to an electronic device, and more particularly to a display device.

With the advancement of display technology, display devices have been widely used in daily life, such as home audio-visual entertainment, information display billboards in public places, monitors for e-sports, and portable electronic products.

Generally speaking, the display device includes a pixel array substrate, a counter substrate, and a display medium disposed between the pixel array substrate and the counter substrate. The pixel array substrate has a plurality of pixels. To increase the resolution of the display device, more pixels must be set in the unit area. In other words, the distance between the pixel electrode of the pixel and the data line will be shorter. When the distance between the pixel electrode and the data line is short, the coupling capacitance of the pixel electrode and the data line is large, which in turn causes the phenomenon of vertical cross-talk.

The invention provides a display device with good performance.

A display device according to an embodiment of the present invention includes a substrate, a plurality of pixels arranged on the substrate, and a gate driving circuit. Each pixel includes a scan line, a data line, a first switch element and a first pixel electrode. The first switch element has a first end, a second end and a control end. The first terminal of the first switch element is electrically connected to the data line. The control terminal of the first switch element is electrically connected to the scan line. The first pixel electrode is electrically connected to the second end of the first switch element. Multiple pixels include N pixels arranged in sequence, N is a positive integer greater than or equal to 2, N pixels include p-th pixel and q-th pixel, p is an odd number less than or equal to N and Is a positive integer, q is an even number less than or equal to N and is a positive integer. The gate driving circuit is electrically connected to a scan line of the p-th pixel. In the first sub-frame interval of a frame interval, the gate driving circuit receives the first start signal to generate the first gate Pulse signal. The gate driving circuit is electrically connected to a scan line of the q-th pixel, wherein the gate driving circuit receives the second start signal in the second sub-frame interval of the same frame interval after the first sub-frame interval , To generate the second gate pulse signal. The first gate pulse signal has a first enabling time width, the second gate pulse signal has a second enabling time width, and the first enabling time width is different from the second enabling time width.

A display device according to an embodiment of the present invention includes a substrate, a plurality of pixels arranged on the substrate, and a gate driving circuit. Each pixel includes a scan line, a data line, a first switch element, a first pixel electrode, a second switch element, a second pixel electrode, a third switch element, a control line, and a charge refresh capacitor. The first switch element has a first terminal, a second terminal and a control terminal. The first terminal of the first switch element is electrically connected to the data line, and the control terminal of the first switch element is electrically connected to the scan line. The first pixel electrode is electrically connected to the second end of the first switch element. The second switch element has a first end, a second end and a control end. The first end of the second switch element is electrically connected to the data line. The control terminal of the second switch element is electrically connected to the scan line. The second end of the second switch element is electrically connected to the second pixel electrode. The third switch element has a first end, a second end and a control end. The first end of the third switch element is electrically connected to the second end of the second switch element. The control terminal of the third switch element is electrically connected to the control line. The second terminal of the third switching element is electrically connected to the charging refresh capacitor. Multiple pixels include N pixels arranged in sequence, N is a positive integer greater than or equal to 2, N pixels include p-th pixel and q-th pixel, p is an odd number less than or equal to N and Is a positive integer, q is an even number less than or equal to N and is a positive integer. The gate driving circuit is electrically connected to a scan line of the p-th pixel. In the first sub-frame interval of a frame interval, the gate driving circuit receives the first start signal to generate the first gate Pulse signal. The gate driving circuit is electrically connected to a scan line of the q-th pixel, wherein the gate driving circuit receives the second start signal in the second sub-frame interval of the same frame interval after the first sub-frame interval , To generate the second gate pulse signal.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.

It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected" can refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that there are other elements between two elements.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account the measurement in question and the The specific amount of measurement-related error (ie, the limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the "about", "approximately" or "substantially" used herein can select a more acceptable range of deviation or standard deviation based on optical properties, etching properties, or other properties, instead of using one standard deviation for all properties .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.

FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention.

FIG. 2 shows the first gate pulse signals Vg1, Vg3, Vg5, Vg7, the second gate pulse signals Vg2, Vg4, Vg6, the polarity signal Vpol, the first start signal Vst1, the second start signal according to an embodiment of the present invention. The start signal Vst2, the first data signal Vdl1, the second data signal Vdl2, and the pixel electrode signal Vpx.

FIG. 3 is a schematic diagram of the layout of the pixel PX according to an embodiment of the present invention. 1 omits the illustration of the substrate 110 in FIG. 3.

4 is a schematic cross-sectional view of a display device according to an embodiment of the invention. The cross-section of the pixel array substrate 1 in FIG. 4 corresponds to the cross-sectional lines A-A' and B-B' in FIG. 3.

1, 3 and 4, the display device 10 includes a pixel array substrate 1, a counter substrate 2 opposite to the pixel array substrate 1, and a display disposed between the pixel array substrate 1 and the counter substrate 2 Medium 3.

In this embodiment, the opposite substrate 2 may optionally include a substrate 210, a light blocking pattern 230, and a color filter layer 220. The light blocking pattern 230 is commonly referred to as a black matrix (Black Matrix). The light blocking pattern 230 is disposed on the substrate 210 and has a plurality of openings 232. The color filter layer 220 is disposed on the substrate 210 and overlaps the plurality of openings 232 of the light blocking pattern 230. However, the present invention is not limited to this. According to other embodiments, the color filter layer 220 and/or the light blocking pattern 230 may also be disposed on the substrate 110 of the pixel array substrate 1 to form a color filter on the array (color filter on array; COA) and/or Black matrix on Array (BOA) structure.

In this embodiment, the display medium 3 may be a non-self-luminous material, such as but not limited to: liquid crystal. However, the present invention is not limited to this. According to other embodiments, the display medium 3 may also be a self-luminous material, such as but not limited to: organic electroluminescent material, micro light emitting diode (µLED), etc.

The pixel array substrate 1 includes a substrate 110 and a plurality of pixels PX disposed on the substrate 110. Each pixel PX includes a scan line SL, a data line DL, a switching element T, and a pixel electrode 130. The data line DL extends in a first direction d1, and the scan line SL extends in a second direction d2, where the first direction d1 and the second direction d2 are staggered. The switching element T includes a control terminal Tc, a gate insulating layer GI, a semiconductor pattern Td, a first terminal Ta, and a second terminal Tb. The gate insulating layer GI is disposed between the control terminal Tc and the semiconductor pattern Td. The first terminal Ta and the second terminal Tb are electrically connected to two different regions of the semiconductor pattern Td, respectively. The first terminal Ta of the switching element T is electrically connected to the data line DL. The control terminal Tc of the switching element T is electrically connected to the scan line SL. The pixel electrode 130 is electrically connected to the second terminal Tb of the switching element T.

Please refer to FIG. 3, in this embodiment, at least one pixel PX includes a light-shielding conductive pattern 120. The light-shielding conductive pattern 120 is disposed between the data line DL of the pixel PX and the pixel electrode 130 of the pixel PX. In other words, at least a part of the vertical projection of the light-shielding conductive pattern 120 on the substrate 110 is located between the vertical projection of the data line DL on the substrate 110 and the vertical projection of the pixel electrode 130 on the substrate 110.

For example, in this embodiment, the light-shielding conductive pattern 120 may include a first light-shielding conductive portion 120a and a second light-shielding conductive portion 120b. The first light-shielding conductive portion 120a is disposed on the data line DL and the pixel electrode of the same pixel PX1 Between 130, the second light-shielding conductive portion 120b is disposed between the pixel electrode 130 of one pixel PX1 and the data line DL of the other pixel PX2. In this embodiment, the first light-shielding conductive portion 120a and the second light-shielding conductive portion 120b extend in the first direction d1. That is, in this embodiment, the first light-shielding conductive portion 120a, the second light-shielding conductive portion 120b and the data line DL can be arranged substantially in parallel, but the invention is not limited.

In this embodiment, the first light-shielding conductive portion 120a and the pixel electrode 130 may partially overlap, and the second light-shielding conductive portion 120b and the pixel electrode 130 may partially overlap. However, the present invention is not limited to this. According to other embodiments, the first light-shielding conductive portion 120a and/or the second light-shielding conductive portion 120b and the pixel electrode 130 may not overlap.

3 and 4, in this embodiment, the light-shielding conductive pattern 120 and the scan line SL can be made together. In other words, the light-shielding conductive pattern 120 and the scan line SL may be formed on the same conductive layer, and the material of the light-shielding conductive pattern 120 and the scan line SL may be the same.

Based on the consideration of conductivity, the scan line SL generally uses a metal material. However, the present invention is not limited to this. According to other embodiments, the scan line SL may also use other conductive materials, such as alloys, nitrides of metallic materials, oxides of metallic materials, oxynitrides of metallic materials, or metallic materials and Stacked layers of other conductive materials.

In this embodiment, the light-shielding conductive pattern 120 has a predetermined potential, including a fixed potential (for example, 0V, ground or floating potential) or an adjustable non-zero potential.

In this embodiment, the pixel PX further includes a common electrode 240 (shown in FIG. 4). The potential difference between the common electrode 240 and the pixel electrode 130 is used to drive the display medium 3.

For example, in this embodiment, the display device 10 may be a multi-domain vertical alignment (MVA) type liquid crystal display, and the pixel electrode 130 includes a first main portion 130a (shown in FIG. 3), The second trunk portion 130b (drawn in FIG. 3) interlaced with the first trunk portion 130a and the plurality of branch portions 130c (drawn in FIG. 3) connected to the first trunk portion 130a and the second trunk portion 130b, and the pixel electrode 130 and the common electrode 240 may be respectively disposed on two opposite substrates 110 and 210. However, the present invention is not limited to this. According to other embodiments, the pixel electrode 130 may have other shapes, and/or the pixel electrode 130 and the common electrode 240 may also be disposed on the same substrate.

In this embodiment, the pixel PX may optionally include a light shielding electrode 140 (shown in FIG. 3). The light-shielding electrode 140 overlaps the first trunk portion 130 a and the second trunk portion 130 b of the pixel electrode 130. In this embodiment, the light-shielding electrode 140 and the light-shielding conductive pattern 120 can be formed on the same conductive layer, and the light-shielding electrode 140 can be connected between the first light-shielding conductive portion 120a and the second light-shielding conductive portion 120b, but the present invention does not use this Is limited.

Please refer to FIG. 1, the display device 10 further includes a driving system for driving a plurality of pixels PX. The driving system may include a timing control circuit 4, a gate driving circuit 5 and a data driving circuit 6. The timing control circuit 4 is electrically connected to the gate drive circuit 5 and the data drive circuit 6. The gate driving circuit 5 is electrically connected to the scanning lines SL of the plurality of pixels PX. The data driving circuit 6 is electrically connected to the data lines DL of a plurality of pixels PX.

Multiple pixels PX are arranged in a pixel array. In the embodiment of FIG. 1, the gate driving circuit 5 can be selectively arranged on a single side of the pixel array. However, the present invention is not limited to this. According to other embodiments, the gate driving circuit 5 may also be arranged on opposite sides of the pixel array.

The plurality of pixels PX includes N pixels PX arranged in sequence along the first direction d1. N is a positive integer greater than or equal to 2. The N pixels PX include the p-th pixel PX and the q-th pixel PX, p is an odd number less than or equal to N and a positive integer, and q is an even number less than or equal to N and a positive integer. In short, the N pixels PX arranged in sequence along the first direction d1 include odd-numbered pixels PX and even-numbered pixels PX.

For example, the plurality of pixels PX arranged in sequence along the first direction d1 include pixels PX 1, 3, 5, 7... and pixels PX 2, 4, 6... , 5, 7... pixels PX respectively include scan lines SL1, SL3, SL5, SL7..., and the second, fourth, and sixth pixels PX respectively include scan lines SL2, SL4, SL6....

1 and 2, in the first sub-frame interval t1 of a frame interval t, the gate driving circuit 5 receives the first start signal Vst1 from the timing control circuit 4 to generate a plurality of first Gate pulse signals Vg1, Vg3, Vg5, Vg7... In the first sub-frame interval t1, the plurality of first gate pulse signals Vg1, Vg3, Vg5, Vg7... are transmitted to the plurality of scan lines SL1, SL3, SL5, SL7... of the odd pixel PX in time sequence.

In the second sub-frame interval t2 of the same frame interval t after the first sub-frame interval t1, the gate driving circuit 5 receives the second start signal Vst2 to generate a plurality of second gate pulse signals Vg2, Vg4 , Vg6..., wherein a plurality of second gate pulse signals Vg2, Vg4, Vg6... are transmitted to a plurality of scan lines SL2, SL4, SL6... of even-numbered pixels PX in a time sequence.

In the first sub-frame interval t1 and the second sub-frame interval t2, the timing control circuit 4 outputs a polarity signal Vpol to the data driving circuit 6. After receiving the first gate pulse signal Vg1, Vg3, Vg5, Vg7... after the multiple scan lines SL1, SL3, SL5, SL7 of odd pixels PX and the multiple scan lines SL2, SL4, SL6... of even pixels PX Before receiving the second gate pulse signals Vg2, Vg4, Vg6..., the polarity signal Vpol is switched from the first voltage level to the second voltage level.

The data driving circuit 6 receives the polarity signal Vpol to output the first data signal Vdl1 and the second data signal Vdl2 to the same data line DL in the first sub-frame interval t1 and the second sub-frame interval t2, respectively. The polarity of the signal Vdl1 is opposite to the polarity of the second data signal Vdl2. For example, in this embodiment, the pixel array includes a plurality of pixel rows R1, R2 arranged in a second direction d2, and the plurality of pixels PX of each pixel row R1, R2 are in the first direction d1 Arranged in order; the plurality of pixel rows R1 and R2 include a plurality of odd pixel rows R1 and a plurality of even pixel rows R2 alternately arranged in the second direction d2; in the first subframe interval t1, the odd pixel rows R1 The pixel PX has a first polarity (for example: positive polarity), and the odd pixel PX in the even-numbered pixel row R2 has a second polarity (for example: negative polarity); in the second subframe interval t2, the even-numbered picture in the odd-numbered pixel row R1 The pixel PX has the second polarity (for example: negative polarity), and the even pixel PX of the even pixel row R2 has the first polarity (for example: positive polarity); but the present invention is not limited to this.

及電壓差

可互相補償，進而改善垂直串音（vertical cross-talk）現象。 Thereby, the pixel electrode 130 is respectively coupled to the data line DL of opposite polarity in the first sub-frame interval t1 and the second sub-frame interval t2. The voltage difference between the signal Vpx of the pixel electrode 130 in the first sub-frame interval t1 and the second sub-frame interval t2 due to the capacitive coupling between the data line DL and the pixel electrode 130

And voltage difference

It can compensate each other to improve the vertical cross-talk phenomenon.

It is worth noting that the first gate pulse signals Vg1, Vg3, Vg5, Vg7... have a first enable time width W1, and the first enable time width W1 refers to the first gate pulse signals Vg1, Vg3, Vg5, Vg7 ...Has the time length of the gate opening potential, the second gate pulse signal Vg2, Vg4, Vg6...has the second enable time width W2, the second enable time width W2 refers to the second gate pulse signal Vg2, Vg4, Vg6...has the time length of the gate on potential, and the first enabling time width W1 is different from the second enabling time width W2.

In other words, the pixel electrode 130, the common electrode 240 and the display medium 3 of each pixel PX can form a display capacitance, and the display capacitance of the odd-numbered pixels PX and the display capacitance of the even-numbered pixels PX are in the first sub-frame interval. t1 and the second sub-frame interval t2 following the first sub-frame interval t1 are charged, and the time that the display capacitor of the odd-numbered pixels PX is charged is different from the time that the display capacitor of the even-numbered pixels PX is charged. In this way, display failure caused by the leakage of the switching element T can be avoided.

。具體而言，第一致能時間寬度W1及/或第二致能時間寬度W2可介於12微秒（µs）～14微秒，但本發明不以此為限。 For example, in this embodiment,

. Specifically, the first enabling time width W1 and/or the second enabling time width W2 may be between 12 microseconds (µs) to 14 microseconds, but the invention is not limited thereto.

FIG. 5 is a schematic diagram of the layout of a pixel PXA according to another embodiment of the present invention. The pixel PXA in FIG. 5 is similar to the pixel PX in FIG. 3. The difference between the two is that the pixel PXA in FIG. 5 does not include the light-shielding conductive pattern 120 of the pixel PX in FIG. 3. That is, in the embodiment of FIG. 5, there is no light-shielding conductive pattern extending in the first direction d1 between the data line DL and the pixel electrode 130.

The pixel PXA in FIG. 5 can be used to replace the pixel PX in FIG. 1 to form another display device 10A. The display device 10A including a plurality of pixels PXA can also be driven by the aforementioned driving system. In particular, the pixel PXA does not include the light-shielding conductive pattern 120 and the display device 10A has a high aperture ratio. With the aforementioned driving system, the display device 10A can improve the vertical cross-talk phenomenon under the premise of having a high aperture ratio. .

6A is a schematic circuit diagram of a pixel PXB according to another embodiment of the invention. FIG. 6B is a schematic diagram of the layout of the pixel PXB according to another embodiment of the present invention. The pixel PXB in FIGS. 6A and 6B is similar to the pixel PX in FIG. 3, and the differences between the two are explained as follows.

6A and 6B, in this embodiment, each pixel PXB includes a scan line SL, a data line DL, a control line CL, a switching element T, and a pixel electrode 130. The switching element T includes a first switching element T1, a second switching element T2 and a third switching element T3, and the pixel electrode 130 includes a first pixel electrode 131 and a second pixel electrode 132.

The first switching element T1 includes a control terminal Tc, a first terminal Ta, and a second terminal Tb. The first terminal Ta of the first switching element T1 is electrically connected to the data line DL. The control terminal Tc of the first switching element T1 is electrically connected to the scan line SL. The first pixel electrode 131 is electrically connected to the second terminal Tb of the first switching element T1.

The second switching element T2 has a first terminal Ta, a second terminal Tb, and a control terminal Tc. The first terminal Ta of the second switching element T2 is electrically connected to the data line DL. The control terminal Tc of the second switch element T2 is electrically connected to the scan line SL. The second terminal Tb of the second switching element T2 is electrically connected to the second pixel electrode 132.

The third switching element T3 has a first terminal Ta, a second terminal Tb, and a control terminal Tc. The first terminal Ta of the third switching element T3 is electrically connected to the second terminal Tb of the second switching element T2. The control terminal Tc of the third switch element T3 is electrically connected to the control line CL. In this embodiment, the control line CL can extend in the second direction d2, and the control line CL and the scan line SL can be arranged substantially in parallel, but the invention is not limited to this.

In this embodiment, the pixel PXB further includes a light shielding electrode 140. The light shielding electrode 140 includes a first light shielding electrode 141 and a second light shielding electrode 142. The first light-shielding electrode 141 overlaps with the first trunk portion 130 a and the second trunk portion 130 b of the first pixel electrode 131. The second light-shielding electrode 142 overlaps with the first trunk portion 130a and the second trunk portion 130b of the second pixel electrode 132.

The second light-shielding electrode 142 overlaps the second pixel electrode 132 to form a charge refresh capacitor Cx. The second terminal Tb of the third switching element T3 is electrically connected to an electrode (ie, the second light-shielding electrode 142) of the charge refresh capacitor Cx.

For example, in this embodiment, the pixel PXB further includes a connection pattern 150, wherein the connection pattern 150 and the pixel electrode 130 can be formed on the same film layer, and the second terminal Tb of the third switching element T3 can be connected through The pattern 150 is electrically connected to the second light shielding electrode 142, but the invention is not limited to this.

In this embodiment, the pixel PXB includes a light-shielding conductive pattern 120. The light-shielding conductive pattern 120 is disposed between the data line DL of the pixel PX and the first pixel electrode 131 of the pixel PX. In other words, at least a part of the vertical projection of the light-shielding conductive pattern 120 on the substrate 110 is located between the vertical projection of the data line DL on the substrate 110 and the vertical projection of the first pixel electrode 131 on the substrate 110.

The plurality of pixels PXB includes pixels PX1 and PX2 that are arranged in the second direction d2 and are adjacent to each other. For example, in this embodiment, the light-shielding conductive pattern 120 may include a first light-shielding conductive portion 120a and a second light-shielding conductive portion 120b. The first light-shielding conductive portion 120a is disposed on the data line DL of the same pixel PX1 and the first picture. Between the pixel electrodes 131, the second light-shielding conductive portion 120b is disposed between the first pixel electrode 131 of one pixel PX1 and the data line DL of the other pixel PX2.

The pixel PXB can be used to replace the pixel PX in FIG. 1 to form another display device 10B. The display device 10B including a plurality of pixels PXB can also be driven by the aforementioned driving system. With the aforementioned driving system, the display device 10B including multiple pixels PXB can also improve the vertical crosstalk phenomenon.

FIG. 7 is a schematic diagram of the layout of pixel PXC according to another embodiment of the present invention. The pixel PXC in FIG. 7 is similar to the pixel PXB in FIGS. 6A and 6B. The difference between the two is that the pixel PXC in FIG. 7 does not include the light-shielding conductive pattern 120 of the pixel PXB in FIGS. 6A and 6B. That is, in the embodiment of FIG. 7, no light-shielding conductive pattern extending in the first direction d1 is provided between the data line DL and the first pixel electrode 131.

The pixel PXC of FIG. 7 can be used to replace the pixel PX of FIG. 1 to form another display device 10C. The display device 10C including a plurality of pixels PXC can also be driven by the aforementioned driving system. In particular, the pixel PXC does not include the light-shielding conductive pattern 120 and the display device 10C has a high aperture ratio. The display device 10C with the aforementioned driving system can improve the vertical crosstalk under the premise of having a high aperture ratio.

FIG. 8 is a schematic circuit diagram of a pixel PXD according to an embodiment of the invention. The pixel PXD in FIG. 8 is similar to the pixel PX in FIG. 3, and the differences between the two are explained as follows.

Referring to FIG. 8, in this embodiment, each pixel PXD includes a scan line SL, a data line DL, a common line TL, a switching element T, and a pixel electrode 130. The switching element T includes a first switching element T1, a second switching element T2 and a third switching element T3, and the pixel electrode 130 includes a first pixel electrode 131 and a second pixel electrode 132.

The first switching element T1 includes a control terminal Tc, a first terminal Ta, and a second terminal Tb. The first terminal Ta of the first switching element T1 is electrically connected to the data line DL. The control terminal Tc of the first switching element T1 is electrically connected to the scan line SL. The first pixel electrode 131 is electrically connected to the second terminal Tb of the first switching element T1.

The second switching element T2 has a first terminal Ta, a second terminal Tb, and a control terminal Tc. The first terminal Ta of the second switching element T2 is electrically connected to the data line DL. The control terminal Tc of the second switch element T2 is electrically connected to the scan line SL. The second terminal Tb of the second switching element T2 is electrically connected to the second pixel electrode 132.

The third switching element T3 has a first terminal Ta, a second terminal Tb, and a control terminal Tc. The first terminal Ta of the third switching element T3 is electrically connected to the second terminal Tb of the second switching element T2. The control terminal Tc of the third switch element T3 is electrically connected to the scan line SL. The second terminal Tb of the third switching element T3 is electrically connected to the common line TL.

In this embodiment, on the actual layout, the pixel PXD includes a light-shielding conductive pattern (not shown). The light-shielding conductive pattern is disposed between the data line DL of the pixel PXD and the first pixel electrode 131 of the pixel PXD. That is, at least a part of the vertical projection of the light-shielding conductive pattern on the substrate (not shown) is located between the vertical projection of the data line DL on the substrate and the vertical projection of the first pixel electrode 131 on the substrate.

The plurality of pixels PXD includes pixels PX1 and PX2 that are arranged in the second direction d2 and are adjacent to each other. For example, in this embodiment, in the actual layout, the light-shielding conductive pattern (not shown) may include a first light-shielding conductive portion (not shown) and a second light-shielding conductive portion (not shown), the first The light-shielding conductive part is arranged between the data line DL of the same pixel PX1 and the first pixel electrode 131, and the second light-shielding conductive part is arranged between the first pixel electrode 131 of one pixel PX1 and the data line of another pixel PX2 Between DL.

The pixel PXD of FIG. 8 can be used to replace the pixel PX of FIG. 1 to form another display device 10D. The display device 10D including a plurality of pixels PXD can also be driven by the aforementioned driving system. With the aforementioned driving system, the display device 10D including a plurality of PXD pixels can also improve the vertical crosstalk phenomenon.

FIG. 9 is a circuit diagram of a pixel PXE according to another embodiment of the invention. The pixel PXE in FIG. 9 is similar to the pixel PXD in FIG. 8. The difference between the two is that the pixel PXE in FIG. 9 does not include the light-shielding conductive pattern of the pixel PXD in FIG. 8. That is, in the embodiment of FIG. 9, there is no light-shielding conductive pattern extending in the first direction d1 between the data line DL and the first pixel electrode 131.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

、

：電壓差 W1、W2：致能時間寬度 1: Pixel array substrate 2: Counter substrate 3: Display medium 4: Timing control circuit 5: Gate drive circuit 6: Data drive circuit 10, 10A, 10B, 10C, 10D, 10E: Display device 110, 210: Substrate 120: Light-shielding conductive patterns 120a, 120b: Light-shielding conductive parts 130, 131, 132: Pixel electrodes 130a, 130b: Main part 130c: Branch parts 140, 141, 142: Light-shielding electrode 150: Connection pattern 220: Color filter layer 230 : Light blocking pattern 232: Opening 240: Common electrode A-A', B-B': Section line CL: Control line Cx: Charge update capacitor DL: Data line d1: First direction d2: Second direction GI: Gate insulation Layers PX, PXA, PXB, PXC, PXD, PXE: pixels R1, R2: pixel rows SL, SL1 to SL7: scanning lines TL: common lines T, T1, T2, T3: switching element Ta: first end Tb: Second terminal Tc: control terminal Td: semiconductor pattern t: frame interval t1, t2: sub-frame interval Vdl1: first data signal Vdl2: second data signal Vg1, Vg3, Vg5, Vg7: first gate pulse signal Vg2, Vg4, Vg6: second gate pulse signal Vpol: polarity signal Vpx: pixel electrode signal Vst1: first start signal Vst2: second start signal

,

：Voltage difference W1, W2: Enable time width

FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention. FIG. 2 shows the first gate pulse signals Vg1, Vg3, Vg5, Vg7, the second gate pulse signals Vg2, Vg4, Vg6, the polarity signal Vpol, the first start signal Vst1, the second start signal according to an embodiment of the present invention. The start signal Vst2, the first data signal Vdl1, the second data signal Vdl2, and the pixel electrode signal Vpx. FIG. 3 is a schematic diagram of the layout of the pixel PX according to an embodiment of the present invention. 4 is a schematic cross-sectional view of a display device according to an embodiment of the invention. FIG. 5 is a schematic diagram of the layout of pixel PXA according to another embodiment of the present invention. 6A is a schematic circuit diagram of a pixel PXB according to another embodiment of the invention. FIG. 6B is a schematic diagram of the layout of the pixel PXB according to another embodiment of the present invention. FIG. 7 is a schematic diagram of the layout of pixel PXC according to still another embodiment of the present invention. FIG. 8 is a schematic circuit diagram of a pixel PXD according to an embodiment of the invention. FIG. 9 is a circuit diagram of a pixel PXE according to another embodiment of the invention.

4: Timing control circuit 5: Gate drive circuit 6: Data drive circuit 10, 10A, 10B, 10C, 10D, 10E: display device DL: Data line d1: the first direction d2: second direction PX, PXA, PXB, PXC, PXD, PXE: pixels R1, R2: pixel row SL, SL1～SL7: scan line

Claims (17)

A display device includes: A substrate; A plurality of pixels are arranged on the substrate, and each of the pixels includes: A scan line A data line; A first switch element has a first end, a second end and a control end, wherein the first end of the first switch element is electrically connected to the data line, and the control end of the first switch element Electrically connected to the scan line; and A first pixel electrode electrically connected to the second end of the first switch element; and A gate driving circuit, wherein the pixels include N pixels arranged in sequence, and N is a positive integer greater than or equal to 2, and the N pixels include a p-th pixel and a q-th pixel , P is an odd number less than or equal to N and a positive integer, q is an even number less than or equal to N and a positive integer; The gate driving circuit is electrically connected to a scan line of the p-th pixel. In a first sub-frame interval of a frame interval, the gate driving circuit receives a first start signal to Generate a first gate pulse signal; The gate driving circuit is electrically connected to a scan line of the qth pixel, wherein after the first sub-frame interval is a second sub-frame interval of the frame interval, the gate driving circuit receives A second start signal to generate a second gate pulse signal; The first gate pulse signal has a first enabling time width, the second gate pulse signal has a second enabling time width, and the first enabling time width is different from the second enabling time width. The display device described in item 1 of the scope of patent application further includes: A data driving circuit is electrically connected to a data line of the p-th pixel and a data line of the q-th pixel, wherein the data driving circuit is in the first subframe interval and the second subframe respectively The frame interval outputs a first data signal and a second data signal, and the polarity of the first data signal is opposite to the polarity of the second data signal. As for the display device described in claim 1, wherein the first enabling time width is W1, the second enabling time width is W2, and

. The display device according to claim 1, wherein there is a light-shielding conductive pattern between the data line of at least one of the pixels and the first pixel electrode of the at least one of the pixels . The display device according to claim 1, wherein there is no shading between the data line of at least one of the pixels and the first pixel electrode of the at least one of the pixels Conductive pattern. For the display device described in item 1 of the scope of patent application, each of the pixels further includes: A second switch element having a first terminal, a second terminal and a control terminal; A second pixel electrode, wherein the first end of the second switch element is electrically connected to the data line, the control end of the second switch element is electrically connected to the scan line, and the second switch element The second end is electrically connected to the second pixel electrode; A third switch element having a first end, a second end and a control end, wherein the first end of the third switch element is electrically connected to the second end of the second switch element; A control line, wherein the control terminal of the third switch element is electrically connected to the control line; and A charging refresh capacitor, wherein the second end of the third switch element is electrically connected to the charging refresh capacitor. The display device according to claim 6, wherein there is a light-shielding conductive pattern between the data line of at least one of the pixels and the first pixel electrode of the at least one of the pixels . The display device according to claim 6, wherein there is no shading between the data line of at least one of the pixels and the first pixel electrode of the at least one of the pixels Conductive pattern. For the display device described in item 1 of the scope of patent application, each of the pixels further includes: A second switch element having a first terminal, a second terminal and a control terminal; A second pixel electrode, wherein the first end of the second switch element is electrically connected to the data line, the control end of the second switch element is electrically connected to the scan line, and the second switch element The second end is electrically connected to the second pixel electrode; A third switch element has a first end, a second end and a control end, wherein the first end of the third switch element is electrically connected to the second end of the second switch element, and the first end The control terminal of the three switch elements is electrically connected to the scan line; and A common line, wherein the second end of the third switch element is electrically connected to the common line. The display device according to claim 9, wherein there is a light-shielding conductive pattern between the data line of at least one of the pixels and the first pixel electrode of the at least one of the pixels . The display device according to claim 9, wherein there is no shading between the data line of at least one of the pixels and the first pixel electrode of the at least one of the pixels Conductive pattern. A display device includes: Multiple pixels, each of the pixels includes: A scan line A data line; A first switch element has a first end, a second end and a control end, wherein the first end of the first switch element is electrically connected to the data line, and the control end of the first switch element Electrically connected to the scan line; A first pixel electrode electrically connected to the second end of the first switch element; A second switch element having a first terminal, a second terminal and a control terminal; A second pixel electrode, wherein the first end of the second switch element is electrically connected to the data line, the control end of the second switch element is electrically connected to the scan line, and the second switch element The second end is electrically connected to the second pixel electrode; A third switch element having a first end, a second end and a control end, wherein the first end of the third switch element is electrically connected to the second end of the second switch element; A control line, wherein the control terminal of the third switch element is electrically connected to the control line; and A charging refresh capacitor, wherein the second terminal of the third switch element is electrically connected to the charging refresh capacitor; and A gate driving circuit, wherein the pixels include N pixels arranged in sequence, and N is a positive integer greater than or equal to 2, and the N pixels include a p-th pixel and a q-th pixel , P is an odd number less than or equal to N and a positive integer, q is an even number less than or equal to N and a positive integer; The gate driving circuit is electrically connected to a scan line of the p-th pixel. In a first sub-frame interval of a frame interval, the gate driving circuit receives a first start signal to Generate a first gate pulse signal; The gate driving circuit is electrically connected to a scan line of the qth pixel, wherein after the first sub-frame interval is a second sub-frame interval of the frame interval, the gate driving circuit receives A second start signal to generate a second gate pulse signal. The display device described in item 12 of the scope of patent application further includes: A data driving circuit is electrically connected to a data line of the p-th pixel and a data line of the q-th pixel, wherein the data driving circuit is in the first subframe interval and the second subframe respectively The frame interval outputs a first data signal and a second data signal, and the polarity of the first data signal is opposite to the polarity of the second data signal. As for the display device described in claim 12, the second gate pulse signal has a second enabling time width, and the first enabling time width is different from the second enabling time width. For the display device according to claim 12, wherein the first enabling time width is W1, the second enabling time width is W2, and

. The display device according to claim 12, wherein a light-shielding conductive pattern exists between the data line of at least one of the pixels and the first pixel electrode of the at least one of the pixels. The display device according to claim 12, wherein there is no shading between the data line of at least one of the pixels and the first pixel electrode of the at least one of the pixels Conductive pattern.

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