TWI703441B - Pin multiplexer and method for controlling pin multiplexer - Google Patents

Abstract

The present invention provides a pin multiplexer including a multiplexing circuit, a control circuit and a detecting circuit. The multiplexing circuit includes a first port, a second port and a third port, wherein the first port, the second port and the third port are coupled to a first device, a second device and a third device, respectively. The control circuit is configured to control the multiplexing circuit to operate in a first mode or a second mode, wherein when the multiplexing circuit operates in the first mode, the first port is coupled the second port; and when the multiplexing circuit operates in the second mode, the first port is coupled to the third port. When the multiplexing circuit operates in the second mode, the detecting circuit detects signals corresponding to the first port to generate a detection result, and the detection result is used to dynamically switch the data transmission direction during the data communication between the third device and the first device.

Description

Pin multiplexing device and method for controlling pin multiplexing device

The invention relates to a pin multiplexing device.

In chip design, in order to allow the limited pins to have the most functions as possible, a pin multiplexing device is usually used to switch the functions of the pins. However, the current pin multiplexing device sets the function switch of the pin before the signal transmission starts. However, because the pin function cannot be switched during the signal transmission process, it is not suitable for bidirectional data. Complicated transmission behavior such as transmission. In addition, if it is suitable for more complex transmission behaviors such as two-way data transmission, it may be necessary to set up some dedicated pins, which increases the manufacturing cost.

Therefore, one of the objectives of the present invention is to provide a pin multiplexing device, which can dynamically switch pin functions to change the data transmission direction during data transmission between two electronic devices, so as to solve the problems in the prior art.

In an embodiment of the present invention, a pin multiplexing device is disclosed, which includes a multiplexing circuit, a control circuit, and a detection circuit. The multiplex circuit includes a first port, a second Two ports and a third port, wherein the first port, the second port, and the third port all include a plurality of pins, and the plurality of the first port, the second port and the third port The pins are used to connect to a first device, a second device, and a third device through a plurality of contacts; the control circuit is used to control the multiplex circuit to operate in a first mode or a second mode , Wherein when the multiplex circuit is operated in the first mode, the first port is connected to the second port; and when the multiplex circuit is operated in the second mode, the first port is connected to the second port Three ports; and when the multiplex circuit is operating in the second mode, the detection circuit detects signals on a part of the pins of the first port or the connected contacts to connect the third device with During the data transmission process of the first device, the data transmission direction of the third device and the first device is dynamically switched.

In another embodiment of the present invention, a method of controlling a pin multiplexing device is disclosed, wherein the pin multiplexing device includes a multiplexing circuit, and the multiplexing circuit includes a first port and a second port. Two ports and a third port, wherein the first port, the second port, and the third port all include a plurality of pins, and the plurality of the first port, the second port and the third port The pins are used to respectively connect to a first device, a second device, and a third device through a plurality of contacts; and the method includes: controlling the multiplex circuit to operate in a first mode or a second Mode, wherein when the multiplex circuit is operated in the first mode, the first port is connected to the second port; and when the multiplex circuit is operated in the second mode, the first port is connected to the The third port; and when the multiplex circuit is operating in the second mode, by detecting a part of the pin of the first port or the signal on the connected contact, the third device and the first During the data transmission process of the device, the data transmission direction of the third device and the first device is dynamically switched.

100: Pin multiplexing device

110: Multiplex circuit

111: First Port

112: second port

113: Third Port

114: Port 4

115_1~115_N, 116_1~116_N: pin

120: control circuit

130: detection circuit

140: register

155_1~155_N, 156_1~156_N: interface circuit

171: First Device

172: Second Device

173: Third Device

174: Fourth Device

210, 220: Buffer

230: contact

400~414: Step

SPI_CSB: Chip selection signal

SPI_CLK: clock signal

SPI_D0, SPI_D1, SPI_D2, SPI_D3: data signal

V1, V2: signal

Vc, Vc’: control signal

V_en: Enabling signal

V_mode: Mode control signal

Figure 1 is a schematic diagram of a pin multiplexing device according to an embodiment of the invention.

Figure 2 shows a schematic diagram of an interface circuit according to an embodiment of the invention.

Figure 3 is a timing diagram of the clock signal, chip selection signal, and four data signals.

Fig. 4 is a flowchart of a method of controlling a pin multiplexing device according to an embodiment of the present invention.

FIG. 1 is a schematic diagram of a pin multiplexing device 100 according to an embodiment of the invention. As shown in Figure 1, the pin multiplexing device 100 includes a multiplexing circuit 110, a control circuit 120, a detection circuit 130, and a register 140. The multiplexing circuit 110 includes a first port 111 , A second port 112, a third port 113, and a fourth port 114, and the first port 111, the second port 112, the third port 113, and the fourth port 114 all include multiple pins, For example, the illustrated first port 111 includes pins 115_1 to 115_N, and the third port 113 includes pins 116_1 to 116_N.

The first port 111, the second port 112, the third port 113, and the fourth port 114 in the pin multiplexing device 100 are used to connect to a first device 171, a second device 172, and a third device 173, respectively. And a fourth device 174, for example, the pins 115_1~115_N of the first port 111 can be connected to the first device 171 through the interface circuit 155_1~155_N, and the pins 116_1~116_N of the third port 113 can be connected to the interface circuit 156_1~156_N It is connected to the third device 173 for data transmission between the above-mentioned devices. The interface circuits 155_1 to 155_N may include transceiver circuits and pads. In one embodiment, the multiplex circuit 110 can operate in a first mode and a second mode. When the multiplex circuit 110 operates in the first mode, the first port 111 is connected to the second port 112 for The first device 171 communicates with the second device 172, and the third port 113 is connected to the fourth port 114 for the third device 173 to communicate with the fourth device 174; on the other hand, when the multiplex circuit 110 operates in the In the second mode, the first port 111 is connected to the third port 113 for the first device 171 to communicate with the third device 173, and at this time the second port 112 and the fourth port 114 No operation is required, that is, the second device 172 and the fourth device 174 will not communicate through the pin multiplexing device 100 at this time.

Specifically, the pin multiplexing device 100 can be controlled by the user or other control methods, so that the control circuit 120 generates a mode control signal V_mode to the multiplex circuit 110, so that the multiplex circuit 110 operates in the first mode Or the second mode. When the multiplex circuit 110 operates in the first mode, since the first port 111 is connected to the second port 112, and the third port 113 is connected to the fourth port 114, the first device 171 can be replicated through pins The device 100 is used for data transmission with the second device 172, and the third device 173 can transmit data with the fourth device 174 through the pin multiplexing device 100; in addition, in this second mode, since the first port 111 It is connected to the third port 113, so the first device 171 can transmit data with the third device 173 through the pin multiplexing device 100; in addition, in the second mode, the multiplexing circuit 110 will generate the unanimous signal V_en To the detection circuit 130 so that the detection circuit 130 loads the configuration data from the register 140 and performs configuration, and starts to detect at least a part of the pins of the first port 111 or the signal on the corresponding interface circuit (Figure 1 only shows the signal of the detection pin 115_N, but this is not a limitation of the present invention), so as to dynamically switch the third device 173 during data transmission between the first device 171 and the third device 173 Data transmission direction with the first device 171. For example, if the third device 173 transmits data to the first device 171 through the pin multiplexing device 100 at the beginning of the second mode, then the detection circuit 130 can continue to detect the first port 111 at this time. Whether the signal on at least part of the pin conforms to a specific pattern, and when it is determined that the detected signal conforms to the specific pattern, a control signal Vc is generated to the multiplex circuit 110 to control/change at least part of the The signal transmission direction of the interface circuits 155_1 to 155_N enables the first device 171 to directly transmit data to the third device 173 through the interface circuits 155_1 to 155_N and the pin multiplexing device 100.

Figure 2 shows a schematic diagram of an interface circuit 200 according to an embodiment of the present invention, where The interface circuit 200 can be applied to at least a part of the interface circuits 155_1 to 155_N and the interface circuits 156_1 to 156_N. As shown in Figure 2, the interface circuit 200 includes two buffers 210 and 220 as a transceiver circuit and a contact 230. Taking the interface circuit 155_N as an example, the contact 230 can be connected to the first device 171, and the two The two buffers 210 and 220 can be generated by the multiplex circuit 110 according to the control signal Vc output by the detection circuit 130. In detail, at the beginning of the second mode, the multiplexing circuit 110 can generate a control signal Vc' to turn on the buffer 210 and turn off the buffer 220, so that the third device 173 can pass through the pin multiplexing device 100 and the interface The buffer 210 and the contact 230 in the circuit 155_N transmit a signal V1 to the first device 171, and the detection circuit 130 determines that the detected signal conforms to the specific pattern and generates a control signal Vc to the multiplexing circuit 110 At this time, the multiplexing circuit 110 can generate a control signal Vc' to turn off the buffer 210 and turn on the buffer 220, so that the third device 173 passes through the pin multiplexing device 100 and the buffer 220 and the contact 230 in the interface circuit 155_N. A signal V2 is received from the first device 171.

According to the above embodiments, the pin multiplexing device 100 can dynamically switch the signal transmission direction during the signal transmission process, and since the switching timing is determined by a dedicated hardware circuit (that is, the detection circuit 130) For the two electronic devices that perform signal transmission, it can be recognized that the pins are exclusively owned by each other. Therefore, it can support signal transmission methods with more complicated transmission protocols, and it is also helpful to reduce the number of dedicated pins. Minimize the number of chip pins and reduce costs.

In one embodiment, the first device 171 may be a flash memory conforming to a serial peripheral interface (Serial Peripheral Interface, SPI), and the second device 172 may be a flash memory used to control the first device 171 For the controller, the third device 173 is a pluggable device, the third device 173 can be a memory card or a programmer, and the fourth device 174 can be used to control a memory card controller of the memory card. In this embodiment, the first port 111 includes six pins 115_1~115_6 corresponding to the six interface circuits 155_1~155_6, and the third port 113 includes six pins corresponding to the six interface circuits 156_1~156_6. One pin 116_1~116_6.

In this embodiment, when the third device 173 is a memory card, the control circuit 120 generates the mode control signal V_mode (for example, V_mode=0) to make the pin multiplexing device 100 operate in the first mode, and then flash The memory controller (ie, the second device 172) can access the flash memory (ie, the first device 171) through the second port 112 and the first port 111 of the pin multiplexing device 100, and the memory The card controller (ie, the fourth device 174) can access the memory card (ie, the third device 173) through the fourth port 114 and the third port 113 of the pin multiplexing device 100; in this embodiment When the third device 173 is a memory card and the pin multiplexing device 100 operates in the first mode, the functions of the six pins 116_1~116_6 of the third port 113 can correspond to a clock signal SD_CLK and a command signal respectively SD_CMD and the four data signals SD_D0, SD_D1, SD_D2, SD_D3, and since those with ordinary knowledge in the field should be able to easily understand the functions of these signals in the relevant specifications of the memory card, the details are not repeated here. In addition, when the third device 173 is a programmer, the control circuit 120 generates the mode control signal V_mode (for example, V_mode=1) to make the pin multiplexing device 100 operate in the second mode. At this time, the programmer (ie, The third device 173) can access the flash memory (that is, the first device 171) through the third port 113 of the pin multiplexing device 100; in this embodiment, when the third device 173 is a programmer and When the pin multiplexing device 100 operates in the second mode, the functions of the six pins 116_1 to 116_6 of the third port 113 can correspond to a clock signal SPI_CLK, a chip selection signal SPI_CSB and four data in the SPI protocol. Signals SPI_D0, SPI_D1, SPI_D2, SPI_D3, and since those with ordinary knowledge in the field should be able to easily understand the functions of these signals when accessing SPI flash memory, the details are not repeated here.

In this embodiment, when the third device 173 is a programmer, it can quickly erase, program, verify, etc., the flash memory (ie, the first device 171).

In this embodiment, when the third device 173 is a programmer and the pin multiplexing device 100 is operating in the second mode, the detection circuit 130 can detect the data signal SPI_D according to the clock signal SPI_CLK and the chip selection signal SPI_CSB. To decide whether to switch the transfer direction of the programmer and flash memory. Specifically, refer to the timing diagram of the clock signal SPI_CLK, the chip selection signal SPI_CSB, and the four data signals SPI_D0, SPI_D1, SPI_D2, and SPI_D3 shown in Figure 3. Referring to Figures 1 and 3 at the same time, the pin multiplexing device 100 initially controls the interface circuits 155_1~155_6 and the interface circuits 156_1~156_6 so that the programmer transmits data to the flash memory, and when the detection circuit 130 detects It is measured that when the fast read command shown in Figure 3 is received during the 0~7 cycle of the clock signal SPI_CLK (that is, it conforms to a specific pattern), it can be determined that the clock signal SPI_CLK is on the 8th ~13 cycles and 14~19 cycles receive address information and redundant information, and the flash memory will start to send data to the programmer after the 19th cycle of the clock signal SPI_CLK. Therefore, the detection circuit 130 can transmit the control signal Vc to the multiplexing circuit 110 in the 19th cycle of the clock signal SPI_CLK, so that the multiplexing circuit 110 generates the control signal Vc' to change the interface circuits 155_3~155_6 and the interface circuits 156_3~ 156_6 transfer direction, so that the flash memory can transmit the data signals SPI_D0, SPI_D1, SPI_D2, SPI_D3 to the programmer through the interface circuit 155_3~155_6 and the pins 115_3~115_6 of the first port 111. In addition, after the reading is completed, the programmer can switch the level of the chip selection signal SPI_CSB (for example, switch from "0" to "1"), and the detection circuit 130 can transmit the control signal when it detects this action Vc is applied to the multiplex circuit 110 to restore the original transmission direction.

In one embodiment, the detection circuit 130 can turn off the detection of the data signal SPI_D0 when the fast read command as shown in Figure 3 is detected, and wait until the programmer switches the chip selection signal after the read is completed After the level of SPI_CSB is set, the detection of the data signal SPI_D0 is started to prevent the signal change on SPI_D0 from causing the detection circuit 130 to malfunction.

Fig. 4 is a flowchart of a method of controlling a pin multiplexing device according to an embodiment of the present invention. With reference to the contents disclosed in Figures 1 to 4 and above, the process is as follows.

Step 400: The process starts.

Step 402: Determine whether the mode control signal V_mode is “0”, if it is, then the process goes to step 404; otherwise, it goes to step 406.

Step 404: The pin multiplexing device operates in the first mode.

Step 406: The pin multiplexing device operates in the second mode.

Step 408: Set the pin multiplexing device.

Step 410: Configure the detection circuit.

Step 412: The third device accesses the first device through the pin multiplexing device.

Step 414: End.

To briefly summarize the present invention, in the pin multiplexing device of the present invention, a dedicated hardware circuit is used to detect whether the signal on the pin or the interface circuit conforms to a specific pattern, and the pin is dynamically switched accordingly As well as the signal transmission direction of the interface circuit, it can support signal transmission methods with more complicated transmission protocols, and it is also beneficial to reduce the number of dedicated pins, so as to minimize the number of chip pins and reduce costs.

The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Pin multiplexing device

110: Multiplex circuit

111: First Port

112: second port

113: Third Port

114: Port 4

115_1~115_N, 116_1~116_N: pin

120: control circuit

130: detection circuit

140: register

155_1~155_N, 156_1~156_N: interface circuit

171: First Device

172: Second Device

173: Third Device

174: Fourth Device

Vc: control signal

V_en: Enabling signal

V_mode: Mode control signal

Claims (10)

A pin multiplexing device includes: a multiplexing circuit including a first port, a second port and a third port, wherein the first port, the second port and the third port all include A plurality of pins, and the pins of the first port, the second port and the third port are used to connect to a first device, a second device, and a third device through a plurality of interface circuits, respectively Device; a control circuit for controlling the multiplex circuit to operate in a first mode or a second mode, wherein when the multiplex circuit is operated in the first mode, the first port is connected to the second Port; and when the multiplex circuit is operated in the second mode, the first port is connected to the third port; and a detection circuit, wherein when the multiplex circuit is operated in the second mode, the detection circuit The test circuit detects a part of the pin of the first port or the signal on the connected interface circuit to dynamically switch between the third device and the first device during the process of data transmission between the third device and the first device. The data transmission direction of the first device. For the pin multiplexing device described in claim 1, wherein when the multiplexing circuit is operating in the first mode, the detection circuit does not detect the part of the pins or all the pins of the first port The signal on the connected interface circuit. The pin multiplexing device described in the first item of the scope of patent application, wherein when the multiplex circuit is operated in the second mode, the third device transmits through the part of the pins of the first port of the multiplex circuit Data to the first device; and when the detection circuit detects that the part of the pins of the first port or the signal on the connected interface circuit conforms to a specific pattern, the detection circuit generates a control signal So that the first device transmits data through the part of the pins of the first port of the multiplexer circuit To the third device. For the pin multiplexing device described in item 3 of the scope of patent application, the interface circuit corresponding to the part of the pins of the first port includes a transceiver circuit, and when the detection circuit detects the first port When the signal on the part of the pins or the connected interface circuit conforms to the specific pattern, the detection circuit generates the control signal to control the transceiver circuit through the multiplexer circuit, so that the first device can pass through the multiplexer The part of the pins of the first port of the IC transmits data to the third device. For the pin multiplexing device described in item 1 of the scope of patent application, the multiplexing circuit further includes a fourth port, and the pins of the fourth port are used to connect to each other through a plurality of contacts. A fourth device; and when the multiplex circuit is operated in the first mode, the third port is connected to the fourth port. For the pin multiplexing device described in item 5 of the scope of patent application, wherein the first device is a flash memory, the second device is a flash memory controller, the third device is a memory card or It is a programmer, and the fourth device is a memory card controller. The pin multiplexing device described in item 6 of the scope of patent application, wherein when the third device is the memory card, the control circuit controls the multiplexing circuit to operate in the first mode, so that the flash memory The body controller is connected to the flash memory through the multiplexing circuit, and the memory card controller is connected to the memory card through the multiplexing circuit; and when the third device is the programmer, the control circuit controls The multiplexing circuit operates in the second mode, so that the programmer is connected to the flash memory through the multiplexing circuit. A method of controlling a pin multiplexing device, wherein the pin multiplexing device includes a multiplex circuit, the multiplex circuit includes a first port, a second port and a third port, wherein the first port The port, the second port, and the third port all include multiple pins, and the multiple pins of the first port, the second port, and the third port are used to connect through multiple interface circuits, respectively To a first device, a second device, and a third device; and the method includes: controlling the multiplex circuit to operate in a first mode or a second mode, wherein when the multiplex circuit operates in the first mode In one mode, the first port is connected to the second port; and when the multiplex circuit is operating in the second mode, the first port is connected to the third port; and when the multiplex circuit is operating in In the second mode, by detecting a part of the pin of the first port or the signal on the connected interface circuit, the third device is dynamically switched to the first device during data transmission. The data transmission direction of the three devices and the first device. Such as the method described in item 8 of the scope of patent application, wherein when the multiplex circuit is operated in the second mode, by detecting the signal on the part of the pins of the first port or the connected interface circuit, During the process of data transmission between the third device and the first device, the step of dynamically switching the data transmission direction of the third device and the first device includes: when the multiplexing circuit is operating in the second mode, The third device transmits data to the first device through the part of the pins of the first port of the multiplex circuit; and when the part of the pins of the first port or the connected interface circuit is detected When the signal conforms to a specific pattern, a control signal is generated so that the first device transmits data to the third device through the part of the pins of the first port of the multiplex circuit. For the method described in claim 9, wherein the interface circuit corresponding to the part of the pins of the first port includes a transceiver circuit, and when it is detected that the part of the pins of the first port is When the signal on the connected interface circuit conforms to the specific pattern, the step of generating the control signal so that the first device transmits data to the third device through the part of the pins of the first port of the multiplexer circuit includes Yes: When it is detected that the signal on the part of the pins of the first port or the connected interface circuit conforms to the specific pattern, the control signal is generated to control the transceiver circuit through the multiplex circuit, so that the The first device transmits data to the third device through the part of the pins of the first port of the multiplex circuit.

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