TWI701815B - Memory device - Google Patents

Abstract

A memory device is provided. The memory device comprises a stack structure and a channel structure. The stack structure is on a substrate and comprises gate electrodes and insulating films stacked alternately. The channel structure is electrically coupled to the gate electrodes, and is on sidewall surfaces of the gate electrodes. The channel structure comprises a first channel structure and a second channel structure. The second channel structure is on an upper surface of the first channel structure. The first channel structure and/or the second channel structure has a ring shape.

Description

Memory device

The present invention relates to a memory device.

As the critical size of components in integrated circuits gradually shrinks to the perceptible limit of the process technology, designers have begun to look for technologies that can achieve greater memory density, thereby achieving lower costs per bit. Technologies that are currently being watched include NAND memory and its manufacturing method.

The invention relates to a memory device.

According to one aspect of the present invention, a memory device is provided, which includes a memory device including a stacked structure and a channel structure. The stacked structure is located on the substrate. The stacked structure includes gate electrodes and insulating films stacked alternately. The channel structure is electrically coupled to the gate electrode and is located on the side surface of the gate electrode. The channel structure includes a first channel structure and a second channel structure. The second channel structure is located on the upper surface of the first channel structure. The first channel structure and/or the second channel structure have a ring shape.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

102: Base

104, 204: insulating film

106, 206: etching stop layer

109: bottom conductive layer

109S1: side surface

109S2: upper surface

110: The first groove

111: conductive layer

111S: side surface

112: charge storage layer

112A: upper surface

112B: side surface

112S: upper surface

114: insulating layer

114S: upper surface

116: Notch

210: second groove

216: Notch

217: Top conductive layer

217S: side surface

218: Gate Dielectric Layer

220: insulating material

300, 304: conductive pillar

302: conductive layer

320 opening

322: Insulated Wall

BL: bit line

CL1: The first channel structure

CL1B: The first bottom channel layer

CL1R: The first ring channel layer

CL1S1: Upper surface

CL1S2: upper surface

CL1S3: Upper surface

CL2, CL4: connection layer

CL2S: upper surface

CL3: Second channel structure

CL31: The first channel layer

CL32: Second channel layer

CL32B: second bottom channel layer

CL32R: The second ring channel layer

CSL: Common Source Line

D1: First direction

D2: second direction

D3: Third party

GSL: Ground selection line

IG: bottom inversion gate electrode

K: Stacked structure

K1: The first stacked layer

K1S: upper surface

K2: second stacked layer

K2S: upper surface

N1: first distance

N2: second distance

P1, P2, P3, P4, P5, P6, P7: profile

WL: Character line

SSL: Serial selection line

FIG. 1 to FIG. 20 illustrate a method of manufacturing a memory device according to an embodiment.

Some examples are described below. It should be noted that this disclosure does not show all possible embodiments, and other implementation aspects not mentioned in this disclosure may also be applicable. Furthermore, the size ratios in the drawings are not drawn in proportion to the actual products. Therefore, the contents of the description and illustrations are only used to describe the embodiments, rather than to limit the protection scope of this disclosure. In addition, the descriptions in the embodiments, such as detailed structure, process steps, material applications, etc., are for illustrative purposes only, and are not intended to limit the scope of the disclosure. The details of the steps and structures of the embodiments can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present disclosure. In the following description, the same/similar symbols represent the same/similar elements.

FIG. 1 to FIG. 20 illustrate a method of manufacturing a memory device according to an embodiment.

Referring to FIG. 1, conductive layers and insulating films can be alternately stacked on the substrate 102 to form a first stacked layer K1. In an embodiment, the substrate 102 may include a silicon substrate, and the first stacked layer K1 may be formed on an insulating layer on the silicon substrate. The insulating layer may include materials such as silicon oxide. The conductive layer includes the bottom conductive layer 109 and other conductive layers 111 above it. The bottom conductive layer 109 and the conductive layer 111 may include conductive materials, such as conductive materials or semiconductor materials. Semiconductor materials include polysilicon, such as doped Miscellaneous polysilicon. The insulating film may include an insulating film 104 and an etch stop layer 106, and the etch stop layer 106 may be formed on the topmost insulating film 104. In one embodiment, the insulating film 104 may include oxide such as silicon oxide, and the etch stop layer 106 may include nitride such as silicon nitride.

Referring to FIG. 2, a patterning process can be performed to form the first trench 110 in the first stacked layer K1. The first trench 110 may expose the side surface of the first stacked layer K1, including the side surface 111S of the conductive layer 111 and the side surface 109S1 of the bottom conductive layer 109, and may expose the upper surface 109S2 of the bottom conductive layer 109. A charge storage layer 112 is formed in the first trench 110. The charge storage layer 112 may be formed on the side surface of the first stacked layer K1 exposed by the first trench 110 and the upper surface 109S2 of the bottom conductive layer 109, and on the upper surface K1S of the first stacked layer K1. The first channel structure CL1 may be formed on the upper surface 112A and the side surface 112B of the charge storage layer 112 exposed by the first trench 110. The charge storage layer 112 located between the first stacked layer K1 (including the side surface 111S of the conductive layer 111 and the side surface 109S1 and the upper surface 109S2 of the bottom conductive layer 109) and the first channel structure CL1 may have an ONO structure or an ONONO structure , ONONONO structure, or silicon oxynitride/silicon nitride/oxide structure. The first channel structure CL1 may include a semiconductor material, including a doped semiconductor material or an undoped semiconductor material. In one embodiment, the material of the first channel structure CL1 includes polysilicon, such as doped polysilicon or undoped polysilicon.

FIG. 2A is a schematic top view of the structure shown in FIG. 2 along the cross section P1. As shown in Figure 2A, the charge storage layer 112 and the first channel structure CL1 in the first trench 110 have a ring shape, wherein the ring shape includes a circle or an ellipse. A channel structure CL1 is, for example, a hollow ring, a solid ring, a semi-hollow ring, or a solid half ring. Figure 2 may be a schematic longitudinal cross-sectional view of the structure shown in Figure 2A along the line AB.

Referring to FIG. 3, an insulating layer 114 can be formed to fill the first trench 110 and on the upper surface CL1S1 of the first channel structure CL1. The insulating layer 114 is formed on the first channel structure CL1 exposed by the first trench 110. In one embodiment, the material of the insulating layer 114 includes oxide such as silicon oxide.

Referring to FIG. 4, the charge storage layer 112, the first channel structure CL1, and the insulating layer 114 above the first stacked layer K1 can be removed by an etch-back process. In an embodiment, the etch-back process may include a chemical mechanical polishing method or other suitable etching methods. This etch-back process can make the structure have a flat upper surface.

Referring to FIG. 5, the charge storage layer 112, the first channel structure CL1, and the upper portion of the insulating layer 114 can be removed from the upper portion to form a recess 116 recessed from the upper surface K1S of the first stacked layer K1. The recess 116 exposes the upper surface 112S of the charge storage layer 112, the upper surface CL1S2 of the first channel structure CL1, and the upper surface 114S of the insulating layer 114. In one embodiment, an etching process with etching selectivity can be used to perform this removal step using the etching stop layer 106 as an etching mask. In this example, the notch 116 can be substantially aligned with the first groove 110. For example, the size of the notch 116 in the first direction D1 may be substantially equal to the size of the first groove 110 in the first direction D1. The size of the notch 116 in the second direction D2 may be substantially equal to the size of the first groove 110 in the second direction D2. In another embodiment, the structure shown in Figure 4 can be The patterning process is used to form the recess 116. In this example, the size/shape of the recess 116 may be different from the first groove 110.

Referring to FIG. 6, a connecting layer CL2 can be formed to fill the recess 116 and located on the upper surface 112S of the charge storage layer 112, the exposed upper surface CL1S2 of the first channel structure CL1, and the upper surface 114S of the insulating layer 114, and are aligned On the side surfaces of the insulating film 104 and the etching stop layer 106, and on the upper surface K1S of the first stacked layer K1. The material of the connection layer CL2 may be the same or different from the material of the first channel structure CL1. The material of the connection layer CL2 may include a conductive material or a semiconductor material. The semiconductor material may include polysilicon material. In one embodiment, the material of the connection layer CL2 includes a doped semiconductor material, such as a doped polysilicon material, such as an N-doped polysilicon material, and its conductivity may be greater than that of an undoped polysilicon material.

Referring to FIG. 7, an etch-back process can be used to remove the portion of the connecting layer CL2 located above the first stacked layer K1. In an embodiment, the etch-back process may include a chemical mechanical polishing method or other suitable etching methods. This etch-back process can make the structure have a flat upper surface.

FIG. 7A is a schematic top view of the structure shown in FIG. 7 along the cross section P2. As shown in FIG. 7A, the connection layer CL2 in the recess 116 has a solid oval shape. Figure 7 may be a schematic longitudinal cross-sectional view of the structure shown in Figure 7A along the line AB, and similar concepts will not be repeated.

Referring to FIG. 8, the stacked structure K includes a first stacked layer K1 and a second stacked layer K2. A top conductive layer 217 and an insulating film 204 are formed on the first stacked layer K1 and the connection layer CL2 to form a second stacked layer K2. The top conductive layer 217 can be Including conductive materials, such as conductive materials or semiconductor materials. The semiconductor material includes polysilicon, such as doped polysilicon. The etch stop layer 206 may be formed on the topmost insulating film 204. In one embodiment, the insulating film 204 may include oxide such as silicon oxide. The etch stop layer 206 may include nitride such as silicon nitride.

Referring to FIG. 9, a patterning process may be performed to form a second trench 210 in the second stacked layer K2 including the top conductive layer 217. The patterning process includes an etching process. The etching process for forming the second trench 210 may use the connection layer CL2 as an etching stop layer. The second trench 210 can expose the side surface of the second stacked layer K2 (including the side surface 217S of the top conductive layer 217 and the side surfaces of the insulating film 204 and the etching stop layer 206) and the upper surface CL2S of the connection layer CL2. The upper surface CL2S of the connection layer CL2 may be substantially aligned with the upper surface K1S of the first stacked layer K1. In one embodiment, the etching process can remove the upper part of the connecting layer CL2, so that the upper surface CL2S of the remaining connecting layer CL2 is lower than the upper surface K1S of the first stacked layer K1. The top conductive layer 217 may include a semiconductor material, including polysilicon, such as undoped polysilicon. .

Referring to FIG. 10, a gate dielectric layer 218 is formed in the second trench 210. The gate dielectric layer 218 may be formed on the side surface and the upper surface K2S of the second stacked layer K2, and on the upper surface CL2S of the connection layer CL2. The gate dielectric layer 218 may also be formed on the side surface of the etch stop layer 106. The first channel layer CL31 may be formed on the gate dielectric layer 218 in the second trench 210 and on the gate dielectric layer 218 on the upper surface K2S of the second stacked layer K2. The first channel layer CL31 is formed on the side surface and the upper surface of the gate dielectric layer 218. The material of the first channel layer CL31 may include a semiconductor material. half The conductive material may include polysilicon material, such as undoped polysilicon. In one embodiment, the gate dielectric layer 218 is a gate oxide dielectric layer and is adjacent to the side surface of the second stacked layer K2 (including the side surface 217S of the top conductive layer 217) and the first channel layer CL31. The gate oxide dielectric layer may include silicon oxide or the like. In a preferred embodiment, the gate dielectric layer 218 only includes a single layer of silicon oxide. In other words, the gate dielectric layer 218 is not a composite layer such as a silicon oxide layer and a silicon nitride composite layer.

Referring to FIG. 11, an etching process can be used to remove part of the first channel layer CL31 and the gate dielectric layer 218 on the upper surface CL2S of the connecting layer CL2 and the upper surface K2S of the second stacked layer K2 to expose the connecting layer CL2 , While leaving the other part of the first channel layer CL31 and the gate dielectric layer 218 on the side surface of the second stacked layer K2. Anisotropic etching can be used for this removal step. In one embodiment, the etching method may include a plasma etching process, and the first channel layer CL31 remaining on the side surface of the gate dielectric layer 218 can prevent the gate dielectric layer 218 from being damaged by the etching process. The etching process can stop at the connection layer CL2.

Referring to FIG. 12, the second channel layer CL32 can be formed on the second stack layer K2, the gate dielectric layer 218, the connection layer CL2, and the first channel layer CL31. The second channel layer CL32 is formed on the side surface of the gate dielectric layer 218 and the upper surface of the connection layer CL2. The material of the second channel layer CL32 may include a semiconductor material. The semiconductor material may include polysilicon material, such as undoped polysilicon.

Referring to FIG. 13, an insulating material 220 is formed on the second channel layer CL32. In an embodiment, the insulating material 220 may include oxide such as silicon oxide.

Please refer to Figure 14, remove part of the insulating material 220 and position the second A part of the second channel layer CL32 above the upper surface K2S of the stacked layer K2 makes the top surface of the insulating material 220 aligned with the surface K2S. An etch-back process can be used for the removal step. The etch-back process may include a chemical mechanical polishing method.

Referring to FIG. 15, the upper portion of the gate dielectric layer 218, the first channel layer CL31, the second channel layer CL32, and the insulating material 220 can be removed from the upper portion of the insulating material 220 to form a concave recessed from the upper surface K2S of the second stacked layer K2.口216. The notch 216 can expose the upper surface of the gate dielectric layer 218, the first channel layer CL31, the second channel layer CL32 and the insulating material 220, and expose the side surfaces of the topmost insulating film 204 and the etching stop layer 206. The second channel structure CL3 includes a semiconductor material, such as a doped semiconductor material or an undoped semiconductor material. In one embodiment, the material of the second channel structure CL3 includes polysilicon, such as doped polysilicon or undoped polysilicon. The second channel structure CL3 includes a first channel layer CL31 and a second channel layer CL32. The second channel structure CL3 includes a semiconductor material, such as a doped semiconductor material or an undoped semiconductor material. In one embodiment, the material of the second channel structure CL3 includes polysilicon, such as doped polysilicon or undoped polysilicon. In one embodiment, an etching process with etching selectivity can be used to perform this removal step using the etching stop layer 206 as an etching mask. In this example, the notch 216 can be substantially aligned with the first groove 110/the notch 116. For example, the size of the notch 216 in the first direction D1 may be substantially equal to the size of the first groove 110/the notch 116 in the first direction D1. The size of the notch 216 in the second direction D2 may be substantially equal to the size of the first groove 110/the notch 116 in the second direction D2. In another embodiment, a patterning process can be performed on the structure shown in FIG. 14 to form the notch 216. In this example, the ruler of notch 216 The size/shape may be different from the first groove 110/notch 116.

FIG. 15A is a schematic top view of the structure shown in FIG. 15 along cross section P3. FIG. 15B is a schematic top view of the structure shown in FIG. 15 along cross section P4. As shown in FIGS. 15A and 15B, the remaining gate dielectric layer 218 and the first channel layer CL31 have a ring shape, for example, an elliptical ring shape (hollow) or an elliptical solid shape. The second channel layer CL32 may have a cup shape, including a cup bottom portion having a solid oval shape as shown in FIG. 15A, and a cup wall portion having a ring shape such as an elliptical ring shape as shown in FIG. 15B. The wall part of the cup abuts on the bottom part of the cup.

Referring to FIG. 16, a connecting layer CL4 may be formed to fill the recess 216 and located on the upper surface K2S of the second stacked layer K2. The material of the connection layer CL4 may include a conductive material such as a conductive material or a semiconductor material. The semiconductor material may include polysilicon material, such as N-type doped polysilicon. In one embodiment, the material of the connection layer CL4 may be the same as that of the connection layer CL2, for example, both are doped polysilicon. In one embodiment, the main body material of the connection layer CL4 can be the same as the first channel structure CL1 and the second channel structure CL2. The difference is that the first channel structure CL1 and the second channel structure CL2 use undoped polysilicon.

Referring to FIG. 17, an etch-back process can be used to remove the portion of the connection layer CL4 located above the second stacked layer K2. In an embodiment, the etch-back process may include a chemical mechanical polishing method or other suitable etching methods. This etch-back process can make the structure have a flat upper surface.

Figure 17A shows the cross-section P5 along the structure shown in Figure 17 Top view schematic. As shown in FIG. 17A, the connection layer CL4 in the recess 216 has a solid oval shape.

Referring to FIG. 18, a patterning process is performed to form the opening 320, so that the stacked structure K is divided into two separate stacked parts. The opening 320 divides the first channel structure CL1, the connection layer CL2, the second channel structure CL3, and the connection layer CL4 into two separate parts. In detail, the opening 320 divides the elliptical structure into two semi-annular structures (C-shaped). The patterning process used to form the opening 320 also simultaneously pattern the conductive layer (including the bottom conductive layer 109 and the conductive layer 111) and the top conductive layer 217 of the first stacked layer K1 into gate electrodes. The gate electrode includes a bottom electrode formed by patterning the bottom conductive layer 109, which can be used as a bottom inversion gate electrode IG. The gate electrode also includes an intermediate electrode formed by patterning the conductive layer 111, which can be used as a word line WL. In addition, the gate electrode also includes a top electrode formed by patterning the top conductive layer 217, which can be used as a selection line. The selection line includes a serial selection line SSL and a ground selection line GSL which are separated from each other. In one embodiment, the gate dielectric layer 218 adjacent to the serial select line SSL/ground select line GSL is a single-layer silicon oxide film, such as a single-layer silicon oxide film, so that it can be avoided during the memory erasing step. The charge is stored in the gate dielectric layer 218 and interferes with the problem of the serial selection line SSL/ground selection line GSL.

The channel structure is electrically coupled to the gate electrode and is located on the side surface of the gate electrode. The channel structure includes a first channel structure CL1 and a second channel structure CL3. The second channel structure CL3 is located on the upper surface of the first channel structure CL1. The connection layer CL2 is located between the first channel structure LL1 and the second channel structure CL3. for example, The connecting layer CL2 is adjacent to the first annular channel layer CL1R of the first channel structure CL1 and the second bottom channel layer CL32B of the second channel structure CL3. The first channel structure CL1 and/or the second channel structure CL3 have a ring shape.

The charge storage layer 112 is located between a portion of the inner surface of the stack structure K and the first channel structure CL1. Part of the charge storage layer 112 is located on the side surface of the bottom inversion gate electrode IG (bottom electrode) corresponding to the word line WL (middle electrode). The gate dielectric layer 218 is located between another part of the inner surface of the stacked structure K and the second channel structure CL3. Part of the gate dielectric layer 218 is located on the side surface corresponding to the serial selection line SSL/ground selection line GSL (top electrode). The etch stop layer 106 is sandwiched between at least one of the series selection line SSL/ground selection line GSL (top electrode) and the word line WL (middle electrode).

FIG. 18A is a schematic top view of the structure shown in FIG. 18 along the cross section P1. FIG. 18B is a schematic top view of the structure shown in FIG. 18 along cross section P6. FIG. 18C is a schematic top view of the structure shown in FIG. 18 along cross section P7. Referring to FIG. 18, FIG. 18A, FIG. 18B, and FIG. 18C, the first channel structure CL1 includes a first bottom channel layer CL1B and two first annular channel layers CL1R. The first annular channel layers CL1R are separated from each other and adjacent to both ends of the first bottom channel layer CL1B. The first bottom channel layer CL1B is located on the upper surface 109S2 and the side surface 109S1 of the bottom inversion gate electrode IG. The first annular channel layer CL1R is adjacent to the first bottom channel layer CL1B and separated from each other by the opening 320. The height (or the size of the third direction D3) of the first annular channel layer CL1R can be defined by the depth of the opening 320. The first bottom channel layer CL1B can be defined as the first channel structure CL1 bit The part below the bottom surface of the opening 320. In one embodiment, the first bottom channel layer CL1B is not divided by the opening 320 and maintains an oval-shaped bottom portion of the cup. In another embodiment, the opening 320 may separate the first bottom channel layer CL1B. The first annular channel layer CL1R is preferably perpendicular to the first bottom channel layer CL1B. The first direction D1, the second direction D2, and the third direction D3 may be different from each other. The first direction D1, the second direction D2, and the third direction D3 may be substantially perpendicular to each other. For example, the first direction D1 may be the X direction, the second direction D2 may be the Y direction, and the third direction D3 may be the Z direction.

FIG. 18D is a schematic top view of the structure shown in FIG. 18 along the cross section P2. Referring to FIGS. 18 and 18D, two connection layers CL2 separated by the opening 320 are respectively on the upper surface CL1S2 of the first annular channel layer CL1R separated from each other of the first channel structure CL1. The two connecting layers CL2 separated from each other have a solid half-ring shape, and the flat side surfaces face each other.

FIG. 18E is a schematic top view of the structure shown in FIG. 18 along the cross section P3. FIG. 18F is a schematic top view of the structure shown in FIG. 18 along cross section P4. Referring to FIG. 18, FIG. 18E, and FIG. 18F, the first channel layer CL31 has a ring shape. The second channel layer CL32 may include two second bottom channel layers CL32B and two second ring-shaped channel layers CL32R. The two second bottom channel layers CL32B are separated from each other. The second bottom channel layer CL32B has a solid semi-circular shape, such as a solid semi-elliptical shape. The two second annular channel layers CL32R are respectively adjacent to the two second bottom channel layers CL32B at opposite ends of each other. The first channel layer CL31 is located between the second channel layer CL32 and the stacked structure K. The second annular channel layer CL32R has a hollow semi-ring shape, for example, a hollow semi-elliptical shape.

Fig. 18G is a schematic top view of the structure shown in Fig. 18 along cross section P5. Referring to FIGS. 18 and 18G, the two connection layers CL4 separated by the opening 320 are located on the upper surface of the second annular channel layer CL32R of the second channel structure CL3. The connection layer CL4 has a semicircular shape, and the flat side surfaces face each other.

In one embodiment, the radial thickness of the connecting layer CL2 in the first direction D1 is greater than the radial thickness of the first annular channel layer CL1R in the first direction D1, and greater than the radial thickness of the second annular channel layer CL32R in the first direction D1. Radial thickness in direction D1.

Please refer to FIG. 19, the insulating wall 322 is used to fill the opening 320. In one embodiment, the insulating wall 322 may include oxide such as silicon oxide.

Referring to FIG. 20, the bit line BL and the common source line CSL can be formed above the stacked structure K, and the bit line BL is electrically connected to the channel structure through the conductive pillars 300, 304 and the conductive layer 302, and the common source The pole line CSL is electrically connected to the channel structure through the conductive pillar 300 to form a NAND memory series. However, the conductive pillars 300 and 304 and the conductive layer 302 can be arranged according to actual requirements, and the present invention is not limited thereto. The memory cells of the NAND memory string are defined between the first channel structure CL1 and the word line WL. The two first annular channel layers CL1R have a first distance N1. The two second annular channel layers CL32R have a second distance N2. The first distance N1 is greater than the second distance N2.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those who have general knowledge in the technical field of the present invention, Various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

300, 304: conductive pillar

302: conductive layer

CL1: The first channel structure

CL2: Connection layer

CL3: Second channel structure

CL31: The first channel layer

CL32: Second channel layer

CL4: Third channel structure

CSL: Common Source Line

D1: First direction

D2: second direction

D3: Third party

GSL: Ground selection line

IG: bottom inversion gate electrode

K: Stacked structure

K1: The first stacked layer

K2: second stacked layer

N1: first distance

N2: second distance

WL: Character line

SSL: Serial selection line

Claims (9)

A memory device includes: a stacked structure on a substrate and including a plurality of gate electrodes and a plurality of insulating films stacked alternately; and a channel structure electrically coupled to the gate electrodes and located on the On the side surface of the gate electrode, the channel structure includes: a first channel structure, including a first bottom channel layer and two first ring-shaped channel layers, the two first ring-shaped channel layers are separated from each other and adjacent to each other On both ends of the first bottom channel layer; and a second channel structure located on an upper surface of the first channel structure, wherein the first channel structure and/or the second channel structure are ring-shaped. As for the memory device described in claim 1, wherein the second channel structure includes: a first channel layer; and a second channel layer, and the second channel layer includes: two second bottom channel layers, The two second bottom channel layers are separated from each other; and two second ring-shaped channel layers are respectively adjacent to the two second bottom channel layers at opposite ends of each other, and the first channel layer is located between the second channel layer and the Between stacked structures. As for the memory device described in claim 2, wherein the two first annular channel layers have a first distance, and the two second annular channel layers have a second distance, wherein the first distance is greater than The second distance. As for the memory device described in item 2 of the scope of patent application, the first channel layer and the two second annular channel layers are hollow ring-shaped, and the two second bottom channel layers are solid semi-elliptical. The memory device described in item 1 of the scope of the patent application further includes a connecting layer located between the first channel structure and the second channel structure. The memory device according to claim 5, wherein the material of the first channel structure and the second channel structure includes a doped semiconductor material or an undoped semiconductor material, and the material of the connection layer includes Doped semiconductor material. The memory device described in claim 1 further includes: a charge storage layer located between a portion of the inner surface of the stacked structure and the first channel structure; and a gate dielectric layer located on the Between another part of the inner surface of the stacked structure and the second channel structure. As for the memory device described in claim 7, wherein the gate electrodes include a stack of a bottom electrode, a plurality of middle electrodes, and a top electrode, and part of the charge storage layer is located between the bottom electrode and the in Part of the gate dielectric layer is located on the side surface corresponding to the top electrode. The memory device described in claim 7 further includes an etching stop layer sandwiched between the top electrode and at least one of the middle electrodes.

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