TWI797465B - Semiconductor chip - Google Patents

Abstract

Provided is a semiconductor chip including: a substrate including an device region, an isolation protection ring region and a seal ring region, the device region and the isolation protection ring region are surrounded by the seal ring region; a first device located in the device region; a second device located in the device region, surrounded by the isolation guard ring region, wherein the operating voltage of the second device is greater than the operating voltage of the first device; an isolation guard ring located in the isolation protection ring region surround the second device; and a protection layer over the device region, the isolation protection ring region and the sealing ring region, and has at least one opening, exposed the top surface of the isolation protection ring. The isolation guard ring includes a first doped region located in the substrate; and a conductive ring stack located above the first doped region.

Description

semiconductor wafer

The present invention relates to an integrated circuit, and more particularly to a semiconductor wafer.

Ultra-high voltage (UHV) components are semiconductor components that are widely used in various electronic products. However, when high-temperature reverse bias (HTRB) tests are performed on high-voltage power components, mobile ions, impurity ions or water vapor in the external environment may penetrate the protective layer and further enter In ultra-high voltage power components, it will affect the surface electric field distribution. In addition, electrical abnormalities and deterioration are more likely to occur in high-temperature and high-pressure environments, and different packaging materials and manufacturing processes will also affect the reliability of UHV components.

An embodiment of the present invention provides a semiconductor chip, which can effectively prevent mobile ions in the external environment from entering ultra-high voltage power components, so as to avoid problems such as electrical abnormality, reliability degradation and instability.

A semiconductor wafer according to an embodiment of the present invention includes: a substrate, including an element region, an isolation protection ring region, and a sealing ring region, and the element region and the isolation protection ring region are surrounded by the sealing ring region; a first element located in In the element area; the second element is located in the element area and is surrounded by the isolation protection ring area, and the operating voltage of the second element is greater than the operating voltage of the first element; the isolation protection ring is located in the In the isolation protection ring area, surrounding the second element; and a protective layer, located on the element area, the isolation protection ring area and the sealing ring area, and has at least one opening, exposed out the top surface of the isolation guard ring. The isolation guard ring includes: a first doped region located in the substrate in the isolation guard ring region; and a conductor ring stack located above the first doped region in the isolation guard ring region.

Based on the above, the embodiment of the present invention separates the active area circuit from the ultra-high voltage power element through the isolation protection ring, effectively preventing mobile ions from entering the ultra-high voltage power element, thereby avoiding problems such as electrical abnormality, reliability degradation and instability.

An embodiment of the present invention provides a semiconductor wafer. In addition to being provided with a sealing ring around the dicing line, the wafer is also provided with an isolation protection ring around components with higher operating voltage (such as ultra-high voltage components). In order to prevent mobile ions, impurity ions and water vapor from migrating into the wafer, and further prevent them from moving and contaminating components with higher operating voltages.

Referring to FIGS. 1A and 1B , an embodiment of the present invention proposes a semiconductor wafer 100 including a substrate 10 , a first device D1 , a second device D2 , an isolation protection ring PR and a sealing ring SR. The substrate 10 includes a device region R1 , a seal ring region R2 and an isolation protection ring region R3 . Seal ring region R2 is on the edge of wafer 100 . The element region R1 and the isolation protection ring region R3 are surrounded by the sealing ring region R2. In some embodiments, the device region R1 includes a first device region R11 and a second device region R12 . In other embodiments, the device region R1 includes a first device region R11 , a second device region R12 and a third device region R13 . The positions and sizes of the first device region R11 , the second device region R12 and the third device region R13 are not limited to those shown in FIG. 1A .

The isolation protection ring area R3 includes an isolation protection ring area R31 and an isolation protection ring area R32. The isolation guard ring region R31 surrounds the second device region R12, and the isolation guard ring region R32 surrounds the third device region R13. In other words, the isolation protection ring region R31 is located between the second device region R12 and the seal ring region R2 , the first device region R11 and the third device region R13 . The isolation protection ring region R32 is located between the third device region R13 and the seal ring region R2 , between the first device region R11 and between the second device region R12 .

The first device D1 and the second device D2 are respectively located in the first device region R11 and the second device region R12 of the substrate 10 . The first element D1 may be, for example, a low voltage or medium voltage element with an operating voltage below 40 volts. The operating voltages of the second element D2 and the third element D3 are higher than the operating voltage of the first element D1. The second element D2 and the third element D3 can be, for example, high-voltage power elements or ultra-high-voltage power elements whose operation voltage is higher than 150 volts. The second element D2 and the third element D3 are, for example, high voltage metal oxide semiconductor elements, junction field effect transistor (JFET) elements or high voltage resistors. The second element D2 and the third element D3 are, for example, the second element D2 on the right side of FIG. 4B and FIG. 4C .

The isolation protection ring PR is located in the isolation protection ring regions R31, R32. The isolation protection ring PR includes isolation protection rings PR1 and PR2. The isolation protection ring PR1 surrounds the second element D2. An isolation guard ring PR2 surrounds the third element D3. The seal ring SR is located in the seal ring region R2. The sealing ring SR surrounds the periphery of the first element D1 , the second element D2 , the third element D3 and the isolation protection ring PR.

Referring to FIGS. 1B and 2B , the isolation protection rings PR1 and PR2 can be single ring P or double rings Pa and Pb respectively. The isolation and protection ring PR with double rings Pa and Pb can further strengthen the blocking effect. The widths of the double rings Pa and Pb may be the same or different. In FIG. 2A , both the isolation protection ring PR1 and the isolation protection ring PR2 are represented by double rings Pa and Pb, however, the present invention is not limited thereto. The number of rings isolating the protection ring PR1 and the isolation protection ring PR2 can be designed according to actual needs, and the number of rings can be the same or different.

Referring to FIGS. 1C , 2C and 3 , the semiconductor wafer 100 of the embodiment of the present invention further includes a protective layer PL. The protection layer PL covers the device region R1 , the seal ring region R2 and the scribe line region R4 before the wafer 100 is diced. The protection layer PL only covers part of the isolation protection ring PR in the isolation protection ring region R3, so that the top surface of the isolation protection ring PR is exposed. The protective layer PL may be single layer, double layer or multilayer. The material of the passivation layer PL includes silicon oxide, silicon nitride, polymer or a combination thereof.

The protection layer PL has an opening OP. The opening OP exposes the top surface of the isolation protection ring PR. The opening OP includes openings OP1 and OP2. The opening OP1 exposes the top surface of the isolation protection ring PR1, and the opening OP2 exposes the top surface of the isolation protection ring PR2. The protection layer PL may further include pad openings (not shown) and the like. The openings OP1 and OP2 can partially or completely expose the top surfaces of the isolation protection rings PR1 and PR2 (not shown). In some embodiments, the opening OP1 or OP2 may be a single connected opening, such as a circular opening, as shown in FIG. 1C . In some embodiments, the opening OP1 or OP2 may be composed of a plurality of disconnected small grooves R, respectively, as shown in FIGS. 1D and 2D . The small groove R can have various shapes, such as rectangle, circle, ellipse and so on.

The opening OP can block the movable ions from laterally moving to the second element D2 and the third element D3 in the second element region R12 and the third element region R13 through the protective layer PL, thus, the second element D2 and the third element D3 can be lifted. The withstand voltage and reliability of the third element D3. In addition, since the top surface of the isolation protection ring PR is not completely covered by the protection layer PL, mobile ions can be directly introduced into the substrate 10 through the isolation protection ring PR. In some embodiments, the opening OP exposes at least 40% of the top area of the isolation guard ring PR. Without the opening OP, the mobile ions cannot be directly introduced into the substrate 10 through the isolation protection ring PR, and the mobile ions cannot be effectively blocked from moving laterally to the ultra-high voltage voltage element through the protection layer.

Referring to FIG. 3 , the isolation protection ring PR and the sealing ring SR according to the embodiment of the present invention include conductor ring stacks 20 and 120 respectively. The conductor ring stacks 20 and 120 are located on the substrate 10 and can be formed simultaneously with the metal interconnection of the device region R1. In some embodiments, the conductor ring stacks 20 and 120 respectively have a plurality of conductor rings V0 , M1 , V1 , M2 , V2 and M3 from bottom to top. The conductor rings V0, M1, V1, M2, V2 and M3 are, for example, the contact windows, the first metal layer, the first via, and the second metal interconnection (not shown) in the device region R1, respectively. layer, the second via, and the third metal layer are located at the same height, and can be respectively connected with the contact window, the first metal layer, the first via, the second metal layer, the second via, A third metal layer is formed simultaneously. Therefore, the conductor ring V0 can also be called a contact plug ring; the conductor rings V1 and V2 can also be called interposer plug rings. The conductor rings M1, M2 and M3 can also be called metal rings. In some other embodiments, the conductor loop stacks 20 and 120 may respectively include more conductor loops or less conductor loops. The conductor ring V0 is electrically connected to the doped region 12 and the lowermost metal ring (conductor ring M1 ). The conductor loops V1 and V2 are located between and electrically connected to two layers of metal loops (conductor loops M1 and M2 , conductor loops M2 and M3 ) that are electrically connected up and down. Materials of the conductor rings V0 , M1 , V1 , M2 , V2 and M3 are, for example, copper, copper-aluminum alloy, aluminum, tungsten, polysilicon, and the like.

The conductor rings V0 , M1 , V1 , M2 , V2 , and M3 are structures extending continuously in the longitudinal direction, and they are not blocked by dielectric layers. The conductor loop V0 of the conductor loop stacks 20 and 120 is formed in the ILD layer 32 . M1 , V1 , M2 , V2 of the conductor ring stacks 20 and 120 are formed in the ILD layers 34 , 36 . The conductor ring M3 is the top conductor ring of the conductor ring stacks 20 and 120 , which is formed on the ILD layer 36 at the same height as the metal pad. Materials of the ILD layer 32 and the interlayer dielectric layers 34 , 36 include silicon oxide, silicon nitride, phosphosilicate glass, borophosphosilicate glass, or low-k materials with a dielectric constant lower than 4.

Although the conductor loops V0 , V1 and V2 in FIG. 3 are shown as double loops or multiple loops, the present invention is not limited thereto, and the conductor loops V0 , V1 and V2 can also be single loops. The conductor loops V0 , V1 and V2 can be aligned or staggered with each other. The widths of the conductor loops M1 , M2 and M3 may be greater than or equal to the width of the conductor loops V0 , V1 and V2 , and completely cover the conductor loops 22 and 26 respectively. The widths of the conductor layers M1 , M2 and M3 may be equal or unequal. The conductor loops M1 , M2 and M3 may completely or partially overlap each other. The numbers and widths of the conductor loops V0 , V1 and V2 of the conductor loop stacks 20 and 120 may be equal or different. The widths of the conductor loops M1 of the conductor loop stacks 20 and 120 may be equal or different. Likewise, the widths M2 and M3 of the conductor ring stacks 20 and 120 may be equal or different.

The protection layer PL is located on the interlayer dielectric layer 36 and the conductor ring M3. Sidewalls and top surfaces of the conductor ring M3 of the conductor ring stack 120 of the seal ring SR are covered by the protection layer PL. The sidewalls of the conductor ring M3 of the conductor ring stack 20 isolating the guard ring PR are covered by the protective layer PL, and the top surface of the conductor ring M3 may be partially covered by the protective layer PL, or completely not covered by the protective layer PL, but covered by the protective layer The opening OP of the PL is exposed.

The isolation protection ring PR and the sealing ring SR also include doped regions 12 and 112 respectively. The doped regions 12 and 112 are located in the substrate 10 . The doped regions 12 and 112 are separated by the isolation structure SI. The doped regions 12 and 112 are electrically connected to the conductor ring V0 isolating the protection ring PR and the sealing ring SR, respectively.

Both the doped region 112 of the sealing ring SR and the substrate 10 have a first conductivity type, such as P type. The doping concentration of the doped region 112 is greater than that of the substrate 10 . The width of the doped region 112 may be equal to or greater than the width of the conductor ring stack 120 .

A well region may also be included between the doped region 12 and the substrate 10 of the isolation protection ring PR, and various aspects thereof will be described in detail below with reference to FIGS. 4A to 4E . For the sake of brevity, FIGS. 4A to 4E do not show the isolation protection ring PR, and its various forms are mainly to ensure that mobile ions can be introduced into the substrate or to integrate it into the original high-voltage element.

Referring to FIGS. 3 and 4A , the doped region 12 may be in the well region 16 of the substrate 10 . The doped region 12 , the well region 16 and the substrate 10 all have a first conductivity type, such as P type. The source region S and the drain region D of the second device D2 (as shown in FIG. 4B ) have a second conductivity type, such as N type. The N-type dopant is phosphorus or arsenic, for example. The P-type dopant is, for example, boron or boron fluoride. The doping concentration of the doped region 12 is greater than that of the well region 16 . The doping concentration of the well region 16 is greater than that of the substrate 10 . The doped region 12 , the well region 16 and the substrate 10 form a resistance, so that mobile ions can flow into the substrate 10 from the conductor ring M3 of the conductor ring stack 20 unidirectionally.

Referring to FIGS. 3 and 4B , the doped region 12 may be in the well region 16 of the substrate 10 . The doped region 12 has a second conductivity type, such as N type; the well region 16 and the substrate 10 have a first conductivity type, such as P type. The doping concentration of the doped region 12 is greater than that of the well region 16 . The doping concentration of the well region 16 is greater than that of the substrate 10 . The doped region 12, the well region 16 and the substrate 10 form a unidirectional diode. The isolation protection ring PR can be made separately from the second device D2 or integrated with the second device D2. In FIG. 4B , the isolation protection ring PR can be fabricated separately from the second device D2 , and the well region 16 is independent and separated from the well region PW of the second device D2 . In FIG. 4C , the isolation protection ring PR is integrated into the second device D2, and the well region 16 is shared with the well region PW of the second device D2, thereby reducing the complexity of the manufacturing process. The well region PW is, for example, the well region PW where the source region S and the doped region B connected to Bulk are located.

Referring to FIG. 4C , the doped region 12 of the isolated guard ring PR shares the well region 16 (PW) with the doped region of the second device D2 . In other words, the doped region 12 of the isolation guard PR, the source region S of the second device D2 and the doped region B connected to Bulk are all disposed in the well region 16 (PW). The source region S in the well region 16 (PW) is located on one side of the gate structure G of the second device D2. The gate structure G partially covers the deep well area DNW of the well area 16 (PW). There is also a well NW in the deep well area DNW, which is located on the other side of the gate structure G. The drain region D is in the well region NW. There is also a top doped region PTOP in the well region DNW located below the isolation structure SI1. The doped region 12, the source region S, the drain region D, the deep well region DNW, and the well region NW have a second conductivity type, such as N type; the doped region B, the well region 16 (PW), and the top doped region PTOP And the substrate 10 has a first conductivity type, such as P type.

Referring to FIG. 4D , the doped region 12 may be in the well region 16 of the substrate 10 . In some embodiments, the doped region 12 and the substrate 10 have the second conductivity type, such as P type; the well region 16 has the first conductivity type, such as N type, thus forming a bidirectional diode.

Referring to FIG. 4E , the substrate 10 has a well region 16 and a doped region 12 therein. Well region 16 includes well regions 16N and 16P. The doped region 12 includes doped regions 12N1 , 12N2 , 12P1 and 12P2 . Well region 16N is adjacent to 16P. The doped regions 12N1 and 12P1 are disposed in the well region 16N. The doped regions 12N2 and 12P2 are disposed in the well region 16P. In some embodiments, the well region 16N, the doped regions 12N1 and 12N2 have the second conductivity type, such as N type; the substrate 10, the well region 16P, and the doped regions 12P1 and 12P2 have the first conductivity type, such as the P type . The doped regions 12N1 , 12P1 , 12N2 and 12P2 may be separated from each other by an isolation structure SI2 . In addition, the doped regions 12N1 and 12P2 are electrically connected; the doped regions 12P1 and 12N2 are electrically connected, thus forming two parallel diodes.

The above-mentioned doped region 12 and the well region 16 can be formed by ion implantation and tempering, wherein the bidirectional diode and the parallel diode can be flexibly selected according to the requirements of the device, for example, the bidirectional diode The polar bodies allow ions to flow into the substrate 10 through forward and reverse channels.

The protection layer on the top surface of the isolation protection ring of the semiconductor wafer in the embodiment of the present invention has an opening, exposing the top surface of the isolation protection ring. The opening can block the mobile ions from laterally moving to the ultra-high voltage voltage element through the protective layer, so the withstand voltage and reliability of the ultra-high voltage voltage element can be improved. In addition, since the top surface of the isolation guard ring is exposed by the opening, mobile ions can be directly introduced into the substrate through the isolation guard ring.

The isolation guard ring also includes a doped region and a well region in the substrate. The doped region and the well region facilitate the introduction of mobile ions into the substrate. The doped region and the well region can be designed as unidirectional diodes, bidirectional diodes or butt-type diodes. In addition, the isolation guard ring can be further integrated with high-voltage components to save chip area and reduce process complexity.

The invention separates the active area circuit from the ultra-high voltage power element through the isolation protection ring, which can effectively prevent mobile ions from entering the ultra-high voltage power element, and avoid problems such as electrical abnormality, reliability degradation and instability.

10: Base 12, 12N1, 12N2, 12P1, 12P2, 112, B: doped area 16, 16N, 16P, DNW, NW, PW: well area 20, 120: conductor ring stacking 22, 26, M1, M2, M3, V0, V1, V2: conductor ring 32: Inner dielectric layer 34, 36: interlayer dielectric layer 100: chip D: Drain area D1: the first element D2: Second component D3: The third element G: gate structure OP, OP1, OP2: opening P, Pa, Pb: Ring PL: protective layer PR, PR1, PR2: isolation protection ring PTOP: top doped region R: small groove R1: component area R11: the first component area R12: Second element area R13: The third component area R2: sealing ring area R3, R31, R32: isolation protection ring area R4: cutting lane area SI, SI1, SI2: isolation structure SR: sealing ring I-I': tangent

FIG. 1A is a top view of various regions of a semiconductor wafer according to a first embodiment of the present invention. FIG. 1B is a top view of a semiconductor wafer not covered with a protective layer according to the first embodiment of the present invention. FIG. 1C is a top view of a semiconductor wafer covered with a protective layer according to the first embodiment of the present invention. 1D is a top view of another semiconductor wafer covered with a protective layer according to the first embodiment of the present invention. 2A is a top view of various regions of a semiconductor wafer according to a second embodiment of the present invention. 2B is a top view of a semiconductor wafer not covered with a protective layer according to a second embodiment of the present invention. FIG. 2C is a top view of a semiconductor wafer covered with a protective layer according to the second embodiment of the present invention. FIG. 2D is a top view of another semiconductor wafer covered with a protective layer according to the second embodiment of the present invention. Fig. 3 is a schematic cross-sectional view of the line I-I' in Fig. 1C. 4A to 4E are schematic cross-sectional views of doped regions of various isolation guard rings and their adjacent second elements according to embodiments of the present invention.

10: Base

12, 112: doping area

20, 120: conductor ring stacking

M1, M2, M3, V0, V1, V2: conductor ring

32: Inner dielectric layer

34, 36: interlayer dielectric layer

100: chip

OP, OP1: opening

PL: protective layer

PR, PR1: isolation protection ring

R1: component area

R2: sealing ring area

R3, R31: isolation protection ring area

R4: cutting lane area

SI: Isolation Structure

SR: sealing ring

Claims (10)

A semiconductor wafer, comprising: a substrate including an element region, an isolation protection ring region and a sealing ring region, the element region and the isolation protection ring region being surrounded by the sealing ring region; a first element located in the element region ; The second element is located in the element area and is surrounded by the isolation protection ring area, and the operating voltage of the second element is greater than the operating voltage of the first element; the isolation protection ring is located in the isolation protection ring area wherein, surrounding the second element, the isolation guard ring includes: a first doped region located in the substrate within the isolation guard ring region; and a conductor ring stack located in the isolation guard ring above the first doped region in the region; and a protection layer, located on the element region, the isolation guard ring region and the seal ring region, and has at least one opening, exposing the isolation guard ring The top surface, wherein the isolation guard ring further includes: a first well region located in the substrate in the isolation guard ring region, wherein the first doped region is located in the first well region, the The substrate and the first well region have a first conductivity type, the first doped region and the source region and drain region of the second element have a second conductivity type, and the source-drain region is located in the In the first well area mentioned above. The semiconductor wafer as claimed in claim 1, wherein the conductor ring stack The stack includes: a plurality of metal rings, which are at the same level as the plurality of metal layers of the second element; a plurality of contact plug rings, which are connected to the first doped region and the plurality of metal rings The lowermost metal ring is electrically connected; and the interposer plug ring is electrically connected to and electrically connected to the upper and lower adjacent two layers of metal rings. The semiconductor wafer according to claim 1, wherein the substrate, the first well region, and the first doped region have the first conductivity type, and the source region and drain region of the second element having the second conductivity type. The semiconductor wafer according to claim 1, wherein the base and the first well region have the first conductivity type, the first doped region and the source region and drain region of the second element having the second conductivity type. The semiconductor wafer according to claim 1, wherein the isolation guard ring is a single-ring structure or a double-ring structure. A semiconductor wafer, comprising: a substrate including an element region, an isolation protection ring region and a sealing ring region, the element region and the isolation protection ring region being surrounded by the sealing ring region; a first element located in the element region ; The second element is located in the element area and is surrounded by the isolation protection ring area, and the operating voltage of the second element is greater than the operating voltage of the first element; the isolation protection ring is located in the isolation protection ring area , wrapping around the second element around the component, the isolation guard ring includes: a first doped region located in the substrate in the isolation guard ring region; and a conductor ring stack, the first doped region located in the isolation guard ring region above the heterogeneous region; and a protection layer, located on the device region, the isolation guard ring region, and the seal ring region, and has at least one opening, exposing the top surface of the isolation guard ring, wherein the substrate and the seal ring region are exposed. The first doped region has a first conductivity type, the first well region and the source region and drain region of the second element have a second conductivity type, wherein the isolation protection ring further includes: a first A well region is located in the substrate within the isolation guard ring region, wherein the first doped region is located in the first well region. A semiconductor wafer, comprising: a substrate including an element region, an isolation protection ring region and a sealing ring region, the element region and the isolation protection ring region being surrounded by the sealing ring region; a first element located in the element region ; The second element is located in the element area and is surrounded by the isolation protection ring area, and the operating voltage of the second element is greater than the operating voltage of the first element; the isolation protection ring is located in the isolation protection ring area wherein, surrounding the second element, the isolation guard ring includes: a first doped region located in the substrate within the isolation guard ring region; and a conductor ring stack, located above the first doped region in the isolation guard ring region; and a protection layer, located on the element region, the isolation guard ring region, and the sealing ring region, and having at least one an opening, exposing the top surface of the isolation protection ring, wherein the base and the first doped region have the first conductivity type, the first well region and the source region and the drain of the second element The region has a second conductivity type, wherein the isolation guard ring further includes: a first well region located in the substrate in the isolation guard ring region, wherein the first doped region is located in the first well region; a second doped region, having the second conductivity type, located in the first well region; a second well region, having the first conductivity type, located in the substrate, and the first well region The well regions are adjacent; the third doped region, having the first conductivity type, is located in the second well region; and the fourth doped region, having the second conductivity type, is located in the second well region , wherein the first doped region is electrically connected to the fourth doped region, and the second doped region is electrically connected to the third doped region. The semiconductor wafer as claimed in claim 7, wherein the conductor ring stack comprises: a plurality of metal rings, which are at the same level as the plurality of metal layers of the second element; a plurality of contact plug rings, which with the first doped region and the plurality of metal rings The lowermost metal ring is electrically connected; and the interposer plug ring is electrically connected to and electrically connected to the upper and lower adjacent two layers of metal rings. The semiconductor wafer according to claim 7, wherein the isolation protection ring is a single-ring structure or a double-ring structure. The semiconductor wafer according to claim 7, wherein the opening is ring-shaped, or consists of a plurality of disconnected grooves.

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