TWI796109B - Package structure and packaging method - Google Patents
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- TWI796109B TWI796109B TW111102577A TW111102577A TWI796109B TW I796109 B TWI796109 B TW I796109B TW 111102577 A TW111102577 A TW 111102577A TW 111102577 A TW111102577 A TW 111102577A TW I796109 B TWI796109 B TW I796109B
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本發明係有關一種封裝結構,特別是省略導線架以降低寄生電阻與寄生電感的一種封裝結構。 The present invention relates to a packaging structure, especially a packaging structure that omits a lead frame to reduce parasitic resistance and parasitic inductance.
參照圖1,其顯示一方形扁平無引腳封裝(Quad Flat No Lead,QFN)的封裝結構100,是現有晶粒101常見的封裝方式,此封裝方式藉由一導線架102(Lead frame)作為承載結構,晶粒101藉由焊接連於導線架102上,之後藉由封裝材料104(Molding compound)進行包覆導線架102以及其上的晶粒101,然後進行切割封裝的晶粒101與導線架102,以產生多個封裝單元。方形扁平無引腳封裝中晶粒101,藉由封裝單元中導線架102的外露部分進行訊號傳遞。
Referring to FIG. 1 , it shows a
方形扁平無引腳封裝的製作技術中,封裝結構有一些難以克服的問題,例如其中導線架102造成高寄生電阻與高寄生電感。參照圖2,當開始導通時,電壓可因導線架102產生的寄生電阻與電感,以形成較長時間的一振鈴效應(Ringing effect),造成訊號傳遞延遲。高頻訊號時寄生電感更會明顯地影響阻抗,此振鈴效應在電流值較高時會十分明顯。
In the manufacturing technology of the QFN package, the package structure has some insurmountable problems, for example, the
參照圖3,為改善此困擾,一先前技術的做法是藉由電路分析套裝軟體進行最佳化運算,將原本導線架中電路的直角轉彎處拉直,藉由縮短電路長度以稍微降低寄生電阻與電感。 Referring to Figure 3, in order to improve this problem, a prior art approach is to use the circuit analysis package software to perform optimization calculations, straighten the right-angled corners of the original lead frame circuit, and slightly reduce the parasitic resistance by shortening the circuit length with inductance.
先前技術中封裝結構中的散熱,多數在設置於導線架上的晶粒上再另設置一散熱材料,以補強散熱能力。例如,圖4顯示美國專利US 7812437的封裝結構10、圖5顯示美國專利US 7164210的封裝結構20、圖6顯示美國專利US 7560309的封裝結構30。此些專利案中,晶粒11、21、31設置於導線架12、22、32上,為封裝材料14、24、34所包覆,在晶粒11、21、31上設置散熱材料15、25、35。重要地,封裝結構10、20、30中,晶粒11、21、31設置於導線架12、22、32上後,才放置散熱材料15、25、35,此些製程繁瑣且任一過程的誤差都可能影響晶粒11、21、31的降溫。前述設置導線架而導致的高寄生電阻與高寄生電感的困擾,在此些專利案中仍難以克服。
For the heat dissipation in the packaging structure in the prior art, a heat dissipation material is mostly provided on the die disposed on the lead frame to enhance the heat dissipation capability. For example, FIG. 4 shows a
針對先前技術的缺點,本發明提供一種封裝結構技術,主要為省略導線架的方式下,可大幅地降低寄生電阻與電感,又具有高散熱效率的效果。 Aiming at the shortcomings of the prior art, the present invention provides a packaging structure technology, which can greatly reduce the parasitic resistance and inductance by omitting the lead frame, and has the effect of high heat dissipation efficiency.
就其中一個觀點言,本發明提供了一種封裝結構,其相較於先前技術,可大幅地降低寄生電阻與電感,又具有高散熱效率的效能。本發明的封裝結構包含:一導熱層;至少一晶粒,包含一訊號收發側與一散熱側,訊號收發側與散熱側互為對面側,散熱側設置於導熱層上;多個金屬凸塊,設置於訊號收發側;以及一封裝材料,包覆晶粒、導熱層上連接晶粒的一側、以及多個金屬凸塊,並露出各金屬凸塊的一側於封裝材料外。 From one point of view, the present invention provides a packaging structure, which can greatly reduce parasitic resistance and inductance compared with the prior art, and has high heat dissipation efficiency. The packaging structure of the present invention includes: a heat conduction layer; at least one crystal grain, including a signal transceiver side and a heat dissipation side, the signal transceiver side and the heat dissipation side are opposite sides, and the heat dissipation side is arranged on the heat conduction layer; a plurality of metal bumps , arranged on the signal receiving and receiving side; and a packaging material, covering the chip, the side connected to the chip on the heat conduction layer, and a plurality of metal bumps, and exposing the side of each metal bump outside the packaging material.
一實施例中,訊號收發側不訊號連結於導線架(Lead frame)。 In one embodiment, the signal transmitting and receiving side is not signal-connected to the lead frame.
一實施例中,導熱層為一高導熱材料所製作。 In one embodiment, the heat conduction layer is made of a high heat conduction material.
一實施例中,導熱層於封裝結構上的外露側(晶粒上連結導熱層的一側的對面側)為平面、起伏狀、或各種幾何形狀的排列矩陣。 In one embodiment, the exposed side of the heat conduction layer on the packaging structure (the side opposite to the side of the die connected to the heat conduction layer) is in a plane, undulating shape, or an arrangement matrix of various geometric shapes.
一實施例中,晶粒之散熱側經由導熱層形成封裝結構中一散熱路徑,將晶粒產生的熱能傳遞至外部。 In one embodiment, the heat dissipation side of the chip forms a heat dissipation path in the package structure through the heat conduction layer, and transfers the heat energy generated by the chip to the outside.
一實施例中,金屬凸塊可電性連結一外接電路板。 In one embodiment, the metal bump can be electrically connected to an external circuit board.
一實施例中,金屬凸塊藉由電鍍製程或植球製程所製造,金屬凸塊的材料包含單一金屬、合金、或複合材料結構。 In one embodiment, the metal bumps are manufactured by an electroplating process or a ball-planting process, and the material of the metal bumps includes a single metal, an alloy, or a composite material structure.
一實施例中,封裝結構包含多個晶粒,金屬凸塊分別設置於各晶粒的訊號收發側,各晶粒的散熱側設置於導熱層上。一實施例中,封裝結構又設有多個繞線於封裝材料外,以分別訊號連接金屬凸塊,封裝結構又包含一封裝堆疊層以包覆繞線與封裝材料。 In one embodiment, the packaging structure includes a plurality of dies, the metal bumps are respectively disposed on the signal receiving and receiving sides of each die, and the heat dissipation side of each die is disposed on the heat conduction layer. In one embodiment, the packaging structure further has a plurality of winding wires outside the packaging material for signal connection to the metal bumps respectively, and the packaging structure further includes a packaging stack layer to cover the winding wires and the packaging material.
另一觀點中,本發明提供一種封裝方法,其包含:提供至少一晶粒,各晶粒包含一訊號收發側與一散熱側,訊號收發側與散熱側互為對面側,多個金屬凸塊設置於訊號收發側;設置一導熱層於散熱側下;提供一封裝材料,包覆導熱層上至少一晶粒、導熱層與金屬凸塊;以及切割包覆封裝材料後至少一晶粒與金屬凸塊,以形成至少一封裝單元,其中各封裝單元包含晶粒、金屬凸塊、切割後導熱層以及切割後封裝材料。 In another aspect, the present invention provides a packaging method, which includes: providing at least one die, each die includes a signal transceiving side and a heat dissipation side, the signal transceiving side and the heat dissipation side are opposite to each other, a plurality of metal bumps Set on the signal transceiver side; set a heat conduction layer under the heat dissipation side; provide a packaging material to cover at least one crystal grain, heat conduction layer and metal bump on the heat conduction layer; and cut at least one crystal grain and metal Bumps to form at least one package unit, wherein each package unit includes a crystal grain, a metal bump, a thermally conductive layer after dicing, and a package material after dicing.
一實施例中,前述的至少一晶粒包含:一晶粒、多個晶粒、或一晶圓上的多個晶粒。 In one embodiment, the aforementioned at least one die includes: a die, a plurality of dies, or a plurality of dies on a wafer.
一實施例中,前述的至少一晶粒為多個晶粒,金屬凸塊分別設置於各晶粒的訊號收發側,各晶粒的散熱側設置於導熱層上,其中封裝方法又包含:設置多個繞線於封裝材料外,以分別訊號連接金屬凸塊;又設置一封裝堆疊層以包覆封裝材料上繞線。 In one embodiment, the aforementioned at least one die is a plurality of dies, the metal bumps are respectively arranged on the signal transmitting and receiving side of each die, and the heat dissipation side of each die is arranged on the heat conduction layer, wherein the packaging method further includes: disposing A plurality of wires are wound outside the packaging material to connect the metal bumps with respective signals; and a packaging stack layer is provided to cover the winding wires on the packaging material.
一實施例中,前述包覆導熱層上晶粒與金屬凸塊的步驟後,又包含:研磨封裝材料與金屬凸塊;以及進行迴銲(Reflow)以修補金屬凸塊。 In one embodiment, after the step of covering the crystal grains and the metal bumps on the thermal conduction layer, further includes: grinding the packaging material and the metal bumps; and performing reflow to repair the metal bumps.
一實施例中,前述設置散熱側於導熱層上的步驟前,導熱層設置於一載板上;以及,各封裝單元形成後,從載板上移出各封裝單元。 In one embodiment, before the step of arranging the heat dissipation side on the heat conduction layer, the heat conduction layer is disposed on a carrier; and, after each package unit is formed, each package unit is removed from the carrier.
底下藉由具體實施例詳加說明,當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。 In the following detailed description by means of specific embodiments, it will be easier to understand the purpose, technical content, characteristics and effects of the present invention.
100,10,20,30:先前封裝結構 100,10,20,30: previous package structure
101,11,21,31:晶粒 101,11,21,31: Grains
102,12,22,32:導線架 102,12,22,32: lead frame
13,23:外接電路板 13,23: External circuit board
104,14,24,34:封裝材料 104,14,24,34: Packaging materials
15,25,35:散熱材料 15,25,35: heat dissipation material
40,50:封裝結構 40,50: package structure
41:導熱層 41: Thermal conduction layer
42,42a,42b,42c:晶粒 42, 42a, 42b, 42c: grain
421,42a1,42b1,42c1:訊號收發側 421, 42a1, 42b1, 42c1: Signal transceiver side
422,42a2,42b2,42c2:散熱側 422,42a2,42b2,42c2: cooling side
43:金屬凸塊 43:Metal bump
44:封裝材料 44: Encapsulation material
45:外接電路板 45: External circuit board
46:載板 46: carrier board
47:繞線 47: Winding
48:金屬堆疊凸塊 48:Metal Stack Bump
49:封裝堆疊層 49: Package stacking layer
PU:封裝單元 PU: Packaging Unit
V:垂直方向 V: vertical direction
圖1至6顯示先前技術中多種封裝結構的相關示意圖。 1 to 6 show related schematic diagrams of various packaging structures in the prior art.
圖7顯示根據本發明一實施例中封裝結構的示意圖。 FIG. 7 shows a schematic diagram of a packaging structure according to an embodiment of the invention.
圖8、9A至9E顯示本發明多個實施例的導熱層的示意圖。 8, 9A to 9E show schematic diagrams of the heat conducting layer of various embodiments of the present invention.
圖10A至10C顯示本發明多個實施例中晶粒與金屬凸塊的示意圖。 10A to 10C show schematic diagrams of dies and metal bumps in various embodiments of the present invention.
圖11顯示本發明一實施例中封裝結構的示意圖。 FIG. 11 shows a schematic diagram of a packaging structure in an embodiment of the present invention.
圖12A至12D顯示本發明一實施例中封裝方法的步驟示意圖。 12A to 12D are schematic diagrams showing steps of a packaging method in an embodiment of the present invention.
圖13A至13E顯示本發明一實施例中封裝方法的步驟示意圖。 13A to 13E are schematic diagrams showing steps of a packaging method in an embodiment of the present invention.
圖14A至14F顯示本發明一實施例中封裝方法的步驟示意圖。 14A to 14F are schematic diagrams showing steps of a packaging method in an embodiment of the present invention.
圖15顯示先前技術與本發明的電性比較結果。 Figure 15 shows the electrical comparison results between the prior art and the present invention.
圖16顯示先前技術與本發明的熱阻比較結果。 Figure 16 shows the thermal resistance comparison results of the prior art and the present invention.
本發明中的圖式均屬示意,主要意在表示各元件組成部分間之相互關係,至於形狀與尺寸則並未依照比例繪製。 The drawings in the present invention are all schematic and mainly intended to show the relationship between components of various components, and the shapes and sizes are not drawn to scale.
相較於先前封裝技術,本案製作過程更可省略導線架,使結構具有較低寄生電阻與電容,其中導熱層更同時兼具放置晶粒與提供散熱路徑的功能,兼具簡化結構、提高訊號傳遞效能、簡化生產流程的果效。 Compared with the previous packaging technology, the manufacturing process of this case can omit the lead frame, so that the structure has lower parasitic resistance and capacitance. The heat conduction layer also has the functions of placing the chip and providing a heat dissipation path, simplifying the structure and improving the signal. The effect of delivering efficiency and simplifying the production process.
參照圖7,其顯示根據本發明一觀點中,所提出一種封裝結構40,包含:一導熱層41;至少一晶粒42,包含一訊號收發側421與一散熱側422,訊號輸出側421與散熱側422互為對面側(例如,圖7中訊號收發側421與散熱側422分別為晶粒42的頂側與底側),散熱側422設置於導熱層41上(不同於先前技術中晶粒放置於導線架上,本發明中晶粒42是以倒置方式設置於導熱層41上);多個金屬凸塊43,設置於訊號收發側421,此封裝結構40內晶粒42藉由金屬凸塊43與封裝結構40外進行訊號連接;以及一封裝材料44,包覆晶粒42、導熱層41上連接晶粒42的一側、以及多個金屬凸塊43。其中,各金屬凸塊43的一側露出於封裝材料41外。圖7顯示包含一晶粒的封裝結構,關於包含多個晶粒的封裝結構,請參照其他實施例的說明。
Referring to FIG. 7 , it shows a
先前技術中,導線架常兼具訊號傳輸與散熱兩功能,即晶粒的訊號收發側與散熱側為同一側。本發明中晶粒42的訊號收發側421與散熱側422非位於晶粒42的同一側,而是在彼此相對的兩側,且訊號收發側421不訊號連結於導線架(Lead frame)。其中,本發明一些實施例中封裝結構,基本上無導線架於其中。
In the prior art, the lead frame often has both functions of signal transmission and heat dissipation, that is, the signal receiving and receiving side of the die is the same side as the heat dissipation side. In the present invention, the
一實施例中,導熱層41為一高導熱材料所製作。導熱層41的材料可包含單一金屬(銅、鋁、陶瓷)、合金(鋁銅合金)、或複合材料結構(鎳包銅、銅板表面為石墨烯塗層)。
In one embodiment, the
一實施例中,導熱層41於封裝結構40的外露側,即導熱層41上連結晶粒42的一側的對面側為平面(例如:實心平面、或平面下有空心管路(圖8))、起伏狀、或各種幾何形狀的排列矩陣(幾何形狀例如:長條圓弧型(圖9A)、長條方排型(圖9B)、長條三角型(圖9C)、獨立錐形突柱(圖9D)、獨立方形突柱(圖9E)、獨立圓形突柱等)。這些導熱層的外露側設計,可增加導熱層41與外部空氣接觸的面積,具加強散熱的效果。
In one embodiment, the exposed side of the
一實施例中,晶粒42之散熱側422經由導熱層41形成封裝結構40中晶粒42與封裝結構40外部間一散熱路徑,將晶粒42產生的熱能傳遞至封裝結構40的外部。封裝結構40中除降低寄生電阻與電感外,較先前技術的導線架有更佳的散熱效果,可藉由導熱層41的材料、厚度與形狀,以調整熱傳量與熱傳效率,而不同於先前技術的導線架中尺寸受限於製造過程中多種限制,其散熱效果的調整彈性較受限。
In one embodiment, the
參照圖10A、10B、10C,一實施例中,依晶粒42的訊號收發側421的垂直方向V的投影,金屬凸塊43可包含多種形狀的選擇,例如:方形(圖10A)、圓形(圖10B)、橢圓形(圖10C)、多邊形等,其形狀可依製造或訊號連線需要而決定其形式。
Referring to FIGS. 10A, 10B, and 10C, in one embodiment, according to the projection in the vertical direction V of the
參閱圖11,一實施例的封裝結構50中,金屬凸塊43可電性連結一外接電路板45(或軟性電路板)。當金屬凸塊43分布過於密集或其他原因,可藉由連結一外接電路板34,以增加各外接訊號接點間的間距(Pitch)。
Referring to FIG. 11 , in a
參閱圖7、11,一實施例中,封裝材料44填滿金屬凸塊43間的空隙。其中,金屬凸塊43之間的訊號收發側421,為封裝材料44所填滿。
Referring to FIGS. 7 and 11 , in one embodiment, the
一實施例中,金屬凸塊43可藉由電鍍製程或植球製程所製作於訊號收發側421上。金屬凸塊43的材料可包含單一金屬(錫、銅)、合金(錫銀合金、錫鉛合金)、或複合材料結構(銅+錫銀合金)。
In one embodiment, the
本發明的封裝結構,可應用於變更傳統方型扁平無引腳封裝(Quad Flat No Lead,QFN)的設計,也可應用於其他傳統封裝結構設計。前述之方型扁平無引腳封裝僅為舉例,使用者可不拘於方型扁平無引腳封裝的應用,凡可省略導線架以及增加導熱層設計的封裝方式,皆可採用本發明提供的技術。 The package structure of the present invention can be applied to change the design of the traditional quad flat no lead package (Quad Flat No Lead, QFN), and can also be applied to the design of other traditional package structures. The aforementioned QFN package is just an example. Users are not limited to the application of QFN package. Any packaging method that can omit the lead frame and increase the design of the heat conduction layer can adopt the technology provided by the present invention. .
參照圖12A至12D,另一觀點中,本發明提供一種封裝方法,其包含:提供至少一晶粒42(圖12A,其中以八個晶粒為例進行說明),各晶
粒42包含一訊號收發側421與一散熱側422,多個金屬凸塊43設置於訊號收發側421,其中金屬凸塊43可包含相同形狀或包含多種形狀;設置一導熱層41於晶粒42的散熱側422於下(圖12B);提供一封裝材料44,包覆導熱層41上至少一晶粒42與金屬凸塊43,並露出金屬凸塊43的一側(圖12C);以及切割(空心箭頭顯示切割方向)包覆封裝材料44後至少一晶粒42、金屬凸塊43以及導熱層41(圖12D),以形成至少一封裝單元PU(圖式以八個封裝單元為例)。各封裝單元PU包含晶粒42、金屬凸塊43、切割後導熱層、以及切割後封裝材料。
Referring to FIGS. 12A to 12D, in another viewpoint, the present invention provides a packaging method, which includes: providing at least one die 42 (in FIG. 12A, eight dies are used as an example for illustration), and each die
一實施例中,當導熱層41為一軟材料,導熱層41預先設置於一載板46上(圖13A)。參照圖13B至13D,本發明提供的封裝方法的步驟又包含:提供至少一晶粒42(圖13B),各晶粒42包含一訊號收發側421與一散熱側422,多個金屬凸塊43設置於訊號收發側421,其中金屬凸塊43可包含相同形狀或包含多種形狀;設置一導熱層41於晶粒42的散熱側422下(圖13C);提供一封裝材料44,包覆導熱層41上至少一晶粒42與金屬凸塊43(圖13D);以及切割(空心箭頭顯示切割方向)包覆封裝材料44後至少一晶粒42、金屬凸塊43以及導熱層41,以形成至少一封裝單元PU,從載板46上移出各封裝單元PU(圖13E)。各封裝單元PU包含晶粒42、金屬凸塊43、切割後導熱層、以及切割後封裝材料。
In one embodiment, when the
一實施例中,前述封裝方法中至少一晶粒包含:一晶粒、多個晶粒、或一晶圓上的多個晶粒。 In one embodiment, the at least one die in the aforementioned packaging method includes: a die, a plurality of dies, or a plurality of dies on a wafer.
一實施例中,同一封裝單元PU可包含多個晶粒。參照圖14A至14F,本發明提供的相關封裝方法的步驟包含:提供多個晶粒42a、42b、42c,金屬凸塊43分別設置於晶粒42a、42b、42c的訊號收發側42a1、42b1、42c1上,晶粒42a、42b、42c的散熱側42a2、42b2、42c2分別設置於導熱層41上(圖14A);提供一封裝材料44,包覆導熱層41上晶粒42a、42b、42c與金屬
凸塊43(圖14B);設置多個繞線47於封裝材料44外,以分別訊號連接金屬凸塊43(圖14C);於繞線47上設置金屬堆疊凸塊48,以電連接繞線47或電連接金屬凸塊43上(圖14D);設置一封裝堆疊層49以包覆封裝材料44上繞線47以及金屬堆疊凸塊48(圖14E);以及切割(空心箭頭顯示切割方向)包覆封裝材料44與封裝堆疊層49後的晶粒42a、42b、42c、金屬凸塊43、金屬堆疊凸塊48以及導熱層41,以形成封裝單元PU。此實施例中,各封裝單元PU可包含不同的晶粒42a、42b、42c(圖14F),其中繞線用於連線各晶粒42a、42b、42c之間。
In one embodiment, the same package unit PU may include multiple dies. Referring to Figures 14A to 14F, the steps of the related packaging method provided by the present invention include: providing a plurality of dies 42a, 42b, 42c, and
一實施例中,前述包覆導熱層41上晶粒42a、42b、42c與金屬凸塊43的步驟後(或包覆封裝堆疊層49與金屬堆疊凸塊48的步驟後),可能需整平表面,然而此整平過程可能傷到金屬凸塊43(或金屬堆疊凸塊48)。因此,前述包覆導熱層41上晶粒42a、42b、42c與金屬凸塊48的步驟後(或包覆封裝堆疊層49與金屬堆疊凸塊48的步驟後),又包含:研磨封裝材料44與金屬凸塊43(或研磨包覆封裝堆疊層49與金屬堆疊凸塊48)、以及進行迴銲(Reflow)以修補金屬凸塊43(或金屬堆疊凸塊48)。
In one embodiment, after the step of covering the dies 42a, 42b, 42c and the metal bumps 43 on the thermally conductive layer 41 (or after the step of covering the
參照圖15,其顯示先前技術的方形扁平無引腳封裝與本發明的省略導線架的封裝結構間的電性模擬比較。根據比較結果,可知本發明封裝結構的電阻與電感,較先前技術的方形扁平無引腳封裝的電阻與電感平均降低達80%以上,其效果顯著。又參照圖16,其顯示先前技術的方形扁平無引腳封裝與本發明的省略導線架的封裝結構間的熱阻模擬比較。根據比較結果,可知本發明的封裝熱阻,較先前技術的方形扁平無引腳封裝的封裝熱阻降低達0.9℃/W。 Referring to FIG. 15 , it shows an electrical simulation comparison between the prior art QFN package and the package structure omitting the lead frame of the present invention. According to the comparison results, it can be seen that the resistance and inductance of the package structure of the present invention are reduced by more than 80% on average compared with the resistance and inductance of the prior art square flat no-lead package, and the effect is remarkable. Referring again to FIG. 16 , it shows a simulated comparison of the thermal resistance between the QFN package of the prior art and the package structure of the present invention omitting the lead frame. According to the comparison results, it can be seen that the thermal resistance of the package of the present invention is reduced by 0.9° C./W compared with the package thermal resistance of the prior art QFN package.
以上已針對實施例來說明本發明,唯以上所述者,僅係為使熟悉本技術者易於了解本發明的內容而已,並非用來限定本發明之權利範圍。在本發明之相同精神下,熟悉本技術者可以思及各種等效變化。例如, 封裝結構上設置不同於圖式中數量的晶粒、或元件放置時有不同的順序、或元件的形狀不同於圖式等,本發明的範圍應涵蓋上述及其他所有等效變化。 The present invention has been described above with reference to the embodiments, but the above description is only for making those skilled in the art understand the contents of the present invention easily, and is not intended to limit the scope of rights of the present invention. Within the same spirit of the present invention, various equivalent changes can be conceived by those skilled in the art. For example, The number of dies different from those shown in the drawings are arranged on the package structure, or the order of placement of components is different, or the shapes of the components are different from those shown in the drawings, etc., the scope of the present invention shall cover the above and all other equivalent changes.
40:封裝結構 40: Package structure
41:導熱層 41: Thermal conduction layer
42:晶粒 42: grain
421:訊號收發側 421: Signal transceiver side
422:散熱側 422: cooling side
43:金屬凸塊 43:Metal bump
44:封裝材料 44: Encapsulation material
Claims (15)
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| TW200947642A (en) * | 2008-05-06 | 2009-11-16 | I Chiun Precision Ind Co Ltd | Package structure and packaging method of light emitting diode |
| TW201347140A (en) * | 2012-05-07 | 2013-11-16 | 立錡科技股份有限公司 | Multi-chip flip chip package module and related manufacturing method |
| TWI729964B (en) * | 2020-11-27 | 2021-06-01 | 力成科技股份有限公司 | Package structure and manufacturing method thereof |
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| US6908784B1 (en) * | 2002-03-06 | 2005-06-21 | Micron Technology, Inc. | Method for fabricating encapsulated semiconductor components |
| US6972964B2 (en) * | 2002-06-27 | 2005-12-06 | Via Technologies Inc. | Module board having embedded chips and components and method of forming the same |
| DE102004047730B4 (en) * | 2004-09-30 | 2017-06-22 | Advanced Micro Devices, Inc. | A method for thinning semiconductor substrates for the production of thin semiconductor wafers |
| US7569422B2 (en) * | 2006-08-11 | 2009-08-04 | Megica Corporation | Chip package and method for fabricating the same |
| KR101147344B1 (en) * | 2010-07-06 | 2012-05-23 | 엘지이노텍 주식회사 | Printed circuit board and Manufacturing method Using the same |
| CN108364876A (en) * | 2017-12-18 | 2018-08-03 | 海太半导体(无锡)有限公司 | A kind of damaged tin ball repair method |
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| TW200947642A (en) * | 2008-05-06 | 2009-11-16 | I Chiun Precision Ind Co Ltd | Package structure and packaging method of light emitting diode |
| TW201347140A (en) * | 2012-05-07 | 2013-11-16 | 立錡科技股份有限公司 | Multi-chip flip chip package module and related manufacturing method |
| TWI729964B (en) * | 2020-11-27 | 2021-06-01 | 力成科技股份有限公司 | Package structure and manufacturing method thereof |
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