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TWI787711B - Integrated circuit structure and formation method thereof - Google Patents

Integrated circuit structure and formation method thereof Download PDF

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TWI787711B
TWI787711B TW110102020A TW110102020A TWI787711B TW I787711 B TWI787711 B TW I787711B TW 110102020 A TW110102020 A TW 110102020A TW 110102020 A TW110102020 A TW 110102020A TW I787711 B TWI787711 B TW I787711B
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line
metal
metallization layer
metallization
metal lines
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TW202147166A (en
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張洸鋐
侯元德
王中興
侯永清
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台灣積體電路製造股份有限公司
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    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • H10W20/42—
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
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    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/853—Complementary IGFETs, e.g. CMOS comprising FinFETs
    • H10W20/43—
    • H10W20/435—
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/337—Design optimisation
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
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    • G06F30/36—Circuit design at the analogue level
    • G06F30/373—Design optimisation
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract

An IC structure includes first, second, third and fourth transistors on a substrate, and first and second metallization layers over the transistors. The first metallization layer has a plurality of first metal lines extending laterally along a first direction and having a first line width measured in a second direction. One or more of the first metal lines are part of a first net electrically connecting the first and second transistors. The second metallization layer has a plurality of second metal lines extending laterally along the second direction and having a second line width measured in the first direction and less than the first line width. One or more of the second metal lines are part of a second net electrically connecting the third and fourth transistors, and a total length of the second net is less than a total length of the first net.

Description

積體電路結構及其形成方法 Integrated Circuit Structure and Formation Method

本公開涉及積體電路結構及其製造方法。 The present disclosure relates to integrated circuit structures and methods of manufacturing the same.

由於各種電子元件(即，電晶體、二極體、電阻器、電容器等)的集積密度不斷地提高，半導體產業經歷了快速的增長。在大多數情況下，集積密度的提高來自最小特徵尺寸的不斷減小，這使得更多的元件可以整合到給定的面積中。 The semiconductor industry has experienced rapid growth due to the increasing packing density of various electronic components (ie, transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in packing density comes from the continuous reduction of the minimum feature size, which allows more components to be integrated into a given area.

依據本公開之部分實施例，提供一種積體電路結構，包含：第一電晶體、第二電晶體、第三電晶體、第四電晶體、第一金屬化層和第二金屬化層。第一電晶體、第二電晶體、第三電晶體和第四電晶體形成在基板上。第一金屬化層在第一電晶體、第二電晶體、第三電晶體和第四電晶體上。第一金屬化層具有沿第一方向橫向地延伸並具有在垂直於第一方向的第二方向上測量的第一線寬的複數個第一金屬線，其中第一金屬線中的一個或複數個是電連接第一電晶體和第二電晶體的第一電路網的一部分。第二金屬 化層在第一金屬化層上，第二金屬化層具有沿第二方向橫向地延伸並具有在第一方向測量的第二線寬的複數個第二金屬線，其中第二金屬線的第二線寬小於第一金屬線的第一線寬，第二金屬線中的一個或複數個是電連接第三電晶體和第四電晶體的第二電路網的一部分，並且第二電路網的總長度小於第一電路網的總長度。 According to some embodiments of the present disclosure, an integrated circuit structure is provided, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a first metallization layer, and a second metallization layer. The first transistor, the second transistor, the third transistor and the fourth transistor are formed on the substrate. The first metallization layer is on the first transistor, the second transistor, the third transistor and the fourth transistor. The first metallization layer has a plurality of first metal lines extending laterally along a first direction and having a first line width measured in a second direction perpendicular to the first direction, wherein one or a plurality of the first metal lines One is part of a first circuit network electrically connecting the first transistor and the second transistor. second metal The metallization layer is on the first metallization layer, and the second metallization layer has a plurality of second metal lines extending laterally along the second direction and having a second line width measured in the first direction, wherein the second metal lines of the second metal lines The second line width is smaller than the first line width of the first metal line, one or more of the second metal lines is a part of the second circuit network electrically connecting the third transistor and the fourth transistor, and the second circuit network The total length is less than the total length of the first circuit network.

依據本公開之部分實施例，提供一種積體電路結構，包含：第一電晶體、第二電晶體、第三電晶體、第四電晶體、第一金屬化層和第二金屬化層。第一電晶體、第二電晶體、第三電晶體和第四電晶體形成在基板上。第一金屬化層在第一電晶體、第二電晶體、第三電晶體和第四電晶體上。第一金屬化層包含沿第一方向橫向地延伸並以第一線至線間距配置的複數個第一金屬線，其中第一金屬線中的一個或複數個是電連接第一電晶體和第二電晶體的第一電路網的一部分。第二金屬化層在第一金屬化層上，第二金屬化層包含沿垂直於第一方向的第二方向橫向地延伸並以第二線至線間距配置的複數個第二金屬線，其中第一線至線間距大於第二線至線間距，第二金屬線中的一個或複數個是連接第三電晶體和第四電晶體的第二電路網的一部分，並且第二電路網的總長度小於第一電路網的總長度。 According to some embodiments of the present disclosure, an integrated circuit structure is provided, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a first metallization layer, and a second metallization layer. The first transistor, the second transistor, the third transistor and the fourth transistor are formed on the substrate. The first metallization layer is on the first transistor, the second transistor, the third transistor and the fourth transistor. The first metallization layer includes a plurality of first metal lines extending laterally along a first direction and arranged at a first line-to-line pitch, wherein one or a plurality of the first metal lines are electrically connected to the first transistor and the first metal line. Part of the first circuit network of two transistors. The second metallization layer is on the first metallization layer, the second metallization layer includes a plurality of second metal lines extending laterally along a second direction perpendicular to the first direction and arranged at a second line-to-line spacing, wherein The first line-to-line spacing is greater than the second line-to-line spacing, one or more of the second metal lines is a part of the second circuit network connecting the third transistor and the fourth transistor, and the total length of the second circuit network The degree is less than the total length of the first circuit network.

依據本公開之部分實施例，提供一種形成積體電路結構的方法，包含：儲存複數個群組化的金屬化層的複數個模型於儲存媒體中；在佈局中，將群組化的金屬化層的模型中的第一個擺置在複數個半導體元件上；在佈局中， 將群組化的金屬化層的模型中的第二個擺置在群組化的金屬化層的模型中的第一個上，其中，群組化的金屬化層的模型中的第二個的最底部的金屬化層的金屬線寬小於群組化的金屬化層的模型中的第一個的最頂部的金屬化層的金屬線寬。佈線第一電路網，使第一電路網至少部分地在群組化的金屬化層的模型中的第一個的最頂部的金屬化層上。佈線第二電路網，使第二電路網至少部分地在群組化的金屬化層的模型中的第二個的最底部的金屬化層上，其中第二電路網的總長度小於第一電路網的總長度。根據佈局製造積體電路。 According to some embodiments of the present disclosure, there is provided a method of forming an integrated circuit structure, including: storing a plurality of models of a plurality of grouped metallization layers in a storage medium; The first of the layer's models is placed on a plurality of semiconductor components; in the layout, placing a second of the models of the grouped metallization layers on a first of the models of the grouped metallization layers, wherein the second of the models of the grouped metallization layers The metal line width of the bottommost metallization layer is smaller than the metal line width of the first topmost metallization layer in the model of grouped metallization layers. Routing the first circuit net at least partially on the topmost metallization layer of a first one of the pattern of grouped metallization layers. routing the second circuit net so that the second circuit net is at least partially on the bottommost metallization layer of a second one of the pattern of grouped metallization layers, wherein the second circuit net has a total length less than that of the first circuit net The total length of the net. Fabricate integrated circuits according to the layout.

100:流程 100: Process

102:步驟 102: Step

104:步驟 104: Step

106:步驟 106: Step

108:步驟 108: Step

110:步驟 110: Steps

112:步驟 112: Step

114:步驟 114: Step

116:步驟 116: Step

118:步驟 118: Step

120:步驟 120: Step

122:步驟 122: Step

200:自動擺置和佈線功能 200: Automatic arrangement and routing function

202:技術文件 202:Technical documents

204:電路網表 204: Circuit netlist

206:元件庫 206: Component library

208:模型庫 208:Model library

209:庫 209: library

210:金屬電阻訊息 210: Metal resistance message

212:程序 212: Procedure

214:程序 214: procedure

216:程序 216: Procedure

218:程序 218: Procedure

220:程序 220: Procedure

300:佈局 300: Layout

300A:積體電路 300A: integrated circuit

301A:基板 301A: Substrate

302A:元件 302A: Components

303A:鰭片 303A: fins

304A:源極/汲極區域 304A: Source/Drain Region

305A:淺溝槽隔離區域 305A: shallow trench isolation area

306A:閘極結構 306A: Gate structure

307A:間隔物 307A: spacer

308A:接觸件 308A: Contact piece

311:金屬線 311: metal wire

312:金屬線 312: metal wire

313:金屬線 313: metal wire

314:金屬線 314: metal wire

315:金屬線 315: metal wire

316:金屬線 316: metal wire

311A:金屬線 311A: metal wire

312A:金屬線 312A: metal wire

313A:金屬線 313A: metal wire

314A:金屬線 314A: metal wire

315A:金屬線 315A: metal wire

316A:金屬線 316A: metal wire

321:通孔 321: through hole

322:通孔 322: through hole

323:通孔 323: through hole

324:通孔 324: through hole

325:通孔 325: through hole

326:通孔 326: through hole

321A:通孔 321A: Through hole

322A:通孔 322A: Through hole

323A:通孔 323A: Through hole

324A:通孔 324A: Through hole

325A:通孔 325A: through hole

326A:通孔 326A: Through hole

330A:互連結構 330A: Interconnect structure

341A:層間介電層 341A: interlayer dielectric layer

351A:金屬間介電層 351A: Intermetal dielectric layer

352A:金屬間介電層 352A: Intermetal dielectric layer

353A:金屬間介電層 353A: Intermetal dielectric layer

354A:金屬間介電層 354A: Intermetal dielectric layer

355A:金屬間介電層 355A: Intermetal dielectric layer

356A:金屬間介電層 356A: Intermetal dielectric layer

361A:金屬間介電層 361A: Intermetal dielectric layer

362A:金屬間介電層 362A: Intermetal dielectric layer

363A:金屬間介電層 363A: Intermetal dielectric layer

364A:金屬間介電層 364A: Intermetal dielectric layer

365A:金屬間介電層 365A: Intermetal dielectric layer

366A:金屬間介電層 366A: Intermetal dielectric layer

400:佈局 400: Layout

400A:積體電路 400A: integrated circuit

401A:基板 401A: Substrate

402A:元件 402A: Components

403A:鰭片 403A: fins

404A:源極/汲極區域 404A: Source/Drain Region

405A:淺溝槽隔離區域 405A: shallow trench isolation area

406A:閘極結構 406A: Gate structure

407A:閘極間隔物 407A: Gate spacer

408A:接觸件 408A: Contact piece

411:金屬線 411: metal wire

412:金屬線 412: metal wire

413:金屬線 413: metal wire

414:金屬線 414: metal wire

415:金屬線 415: metal wire

416:金屬線 416: metal wire

411A:金屬線 411A: metal wire

412A:金屬線 412A: metal wire

413A:金屬線 413A: metal wire

414A:金屬線 414A: metal wire

415A:金屬線 415A: metal wire

416A:金屬線 416A: metal wire

421:通孔 421: Through hole

422:通孔 422: Through hole

423:通孔 423: through hole

424:通孔 424: through hole

425:通孔 425: through hole

426:通孔 426: Through hole

421A:通孔 421A: Through hole

422A:通孔 422A: Through hole

423A:通孔 423A: Through hole

424A:通孔 424A: Through hole

425A:通孔 425A: Through hole

426A:通孔 426A: Through hole

430A:互連結構 430A: Interconnect Structure

441A:層間介電層 441A: interlayer dielectric layer

451A:金屬間介電層 451A: Intermetal dielectric layer

452A:金屬間介電層 452A: Intermetal dielectric layer

453A:金屬間介電層 453A: Intermetal dielectric layer

454A:金屬間介電層 454A: Intermetal dielectric layer

455A:金屬間介電層 455A: Intermetal dielectric layer

456A:金屬間介電層 456A: Intermetal dielectric layer

461A:金屬間介電層 461A: Intermetal Dielectric Layer

462A:金屬間介電層 462A: Intermetal dielectric layer

463A:金屬間介電層 463A: Intermetal dielectric layer

464A:金屬間介電層 464A: Intermetal dielectric layer

465A:金屬間介電層 465A: Intermetal dielectric layer

466A:金屬間介電層 466A: Intermetal dielectric layer

500:佈局 500: layout

500A:積體電路結構 500A: integrated circuit structure

501A:基板 501A: Substrate

502A:元件 502A: Components

503A:鰭片 503A: Fins

504A:源極/汲極區域 504A: Source/Drain Region

505A:淺溝槽隔離區域 505A: shallow trench isolation area

506A:閘極結構 506A: Gate structure

507A:閘極間隔物 507A: Gate spacer

508A:接觸件 508A: Contact piece

511:金屬線 511: metal wire

512:金屬線 512: metal wire

513:金屬線 513: metal wire

514:金屬線 514: metal wire

511A:金屬線 511A: metal wire

512A:金屬線 512A: metal wire

513A:金屬線 513A: metal wire

514A:金屬線 514A: metal wire

521:通孔 521: Through hole

522:通孔 522: Through hole

523:通孔 523: Through hole

524:通孔 524: Through hole

521A:通孔 521A: Through hole

522A:通孔 522A: Through hole

523A:通孔 523A: Through hole

524A:通孔 524A: Through hole

530A:互連結構 530A: Interconnect structure

541A:層間介電層 541A: interlayer dielectric layer

551A:金屬間介電層 551A: Intermetal dielectric layer

552A:金屬間介電層 552A: Intermetal dielectric layer

553A:金屬間介電層 553A: Intermetal dielectric layer

554A:金屬間介電層 554A: Intermetal dielectric layer

561A:金屬間介電層 561A: Intermetal dielectric layer

562A:金屬間介電層 562A: Intermetal dielectric layer

563A:金屬間介電層 563A: Intermetal dielectric layer

564A:金屬間介電層 564A: Intermetal dielectric layer

600:佈局 600: Layout

600A:積體電路結構 600A: integrated circuit structure

615:金屬線 615: metal wire

616:金屬線 616: metal wire

615A:金屬線 615A: metal wire

616A:金屬線 616A: metal wire

625:金屬通孔 625: metal through hole

626:金屬通孔 626: metal through hole

625A:金屬通孔 625A: Metal Through Hole

626A:金屬通孔 626A: Metal Through Hole

630A:互連結構 630A: Interconnect Structure

655A:金屬間介電層 655A: Intermetal dielectric layer

656A:金屬間介電層 656A: Intermetal dielectric layer

665A:金屬間介電層 665A: Intermetal dielectric layer

666A:金屬間介電層 666A: Intermetal dielectric layer

700:佈局 700: layout

700A:積體電路結構 700A: Integrated circuit structure

701A:基板 701A: Substrate

702A:元件 702A: Components

703A:鰭片 703A: fins

704A:源極/汲極區域 704A: Source/Drain Region

705A:淺溝槽隔離區域 705A: Shallow trench isolation region

706A:閘極結構 706A:Gate structure

707A:閘極間隔物 707A: Gate spacer

708A:接觸件 708A: Contact piece

711:金屬線 711: metal wire

712:金屬線 712: metal wire

713:金屬線 713: metal wire

714:金屬線 714: metal wire

715:金屬線 715: metal wire

711A:金屬線 711A: metal wire

712A:金屬線 712A: metal wire

713A:金屬線 713A: metal wire

714A:金屬線 714A: metal wire

715A:金屬線 715A: metal wire

721:通孔 721: Through hole

722:通孔 722: through hole

723:通孔 723: through hole

724:通孔 724: through hole

725:通孔 725: through hole

721A:通孔 721A: Through hole

722A:通孔 722A: Through hole

723A:通孔 723A: Through hole

724A:通孔 724A: Through hole

725A:通孔 725A: Through hole

730A:互連結構 730A: Interconnect Structure

741A:層間介電層 741A: interlayer dielectric layer

751A:金屬間介電層 751A: Intermetal dielectric layer

752A:金屬間介電層 752A: Intermetal dielectric layer

753A:金屬間介電層 753A: Intermetal dielectric layer

754A:金屬間介電層 754A: Intermetal dielectric layer

755A:金屬間介電層 755A: Intermetal dielectric layer

761A:金屬間介電層 761A: Intermetal dielectric layer

762A:金屬間介電層 762A: Intermetal Dielectric Layer

763A:金屬間介電層 763A: Intermetal Dielectric Layer

764A:金屬間介電層 764A: Intermetal Dielectric Layer

765A:金屬間介電層 765A: Intermetal Dielectric Layer

800:佈局 800: layout

800A:積體電路結構 800A: Integrated circuit structure

801A:基板 801A: Substrate

802A:元件 802A: Components

803A:鰭片 803A: fins

804A:源極/汲極區域 804A: Source/Drain Region

805A:淺溝槽隔離區域 805A: Shallow trench isolation region

806A:閘極結構 806A: Gate structure

807A:閘極間隔物 807A: Gate spacer

808A:接觸件 808A: Contact piece

811:金屬線 811: metal wire

812:金屬線 812: metal wire

813:金屬線 813: metal wire

814:金屬線 814: metal wire

815:金屬線 815: metal wire

811A:金屬線 811A: metal wire

812A:金屬線 812A: metal wire

813A:金屬線 813A: metal wire

814A:金屬線 814A: metal wire

815A:金屬線 815A: metal wire

821:通孔 821: Through hole

822:通孔 822: Through hole

823:通孔 823: Through hole

824:通孔 824: through hole

825:通孔 825: through hole

821A:通孔 821A: Through hole

822A:通孔 822A: Through hole

823A:通孔 823A: Through hole

824A:通孔 824A: Through hole

825A:通孔 825A: Through hole

830A:互連結構 830A: Interconnect Structure

841A:層間介電層 841A: interlayer dielectric layer

851A:金屬間介電層 851A: Intermetal dielectric layer

852A:金屬間介電層 852A: Intermetal dielectric layer

853A:金屬間介電層 853A: Intermetal dielectric layer

854A:金屬間介電層 854A: Intermetal dielectric layer

855A:金屬間介電層 855A: Intermetal dielectric layer

861A:金屬間介電層 861A: Intermetal dielectric layer

862A:金屬間介電層 862A: Intermetal dielectric layer

863A:金屬間介電層 863A: Intermetal dielectric layer

864A:金屬間介電層 864A: Intermetal dielectric layer

865A:金屬間介電層 865A: Intermetal dielectric layer

900:佈局 900: layout

900A:積體電路結構 900A: Integrated circuit structure

901A:基板 901A: Substrate

902A:元件 902A: Components

903A:鰭片 903A: fins

904A:源極/汲極區域 904A: Source/Drain Region

905A:淺溝槽隔離區域 905A: Shallow trench isolation region

906A:閘極結構 906A: Gate structure

907A:閘極間隔物 907A: Gate Spacer

908A:接觸件 908A: Contact piece

911:金屬線 911: metal wire

912:金屬線 912: metal wire

913:金屬線 913: metal wire

914:金屬線 914: metal wire

915:金屬線 915: metal wire

916:金屬線 916: metal wire

911A:金屬線 911A: metal wire

912A:金屬線 912A: metal wire

913A:金屬線 913A: metal wire

914A:金屬線 914A: metal wire

915A:金屬線 915A: metal wire

916A:金屬線 916A: metal wire

921:通孔 921: through hole

922:通孔 922: through hole

923:通孔 923: through hole

924:通孔 924: through hole

925:通孔 925: through hole

926:通孔 926: through hole

921A:通孔 921A: Through hole

922A:通孔 922A: Through hole

923A:通孔 923A: Through hole

924A:通孔 924A: Through hole

925A:通孔 925A: Through hole

926A:通孔 926A: Through hole

930A:互連結構 930A: Interconnect Structure

941A:層間介電層 941A: interlayer dielectric layer

951A:金屬間介電層 951A: Intermetal dielectric layer

952A:金屬間介電層 952A: Intermetal dielectric layer

953A:金屬間介電層 953A: Intermetal dielectric layer

954A:金屬間介電層 954A: Intermetal dielectric layer

955A:金屬間介電層 955A: Intermetal dielectric layer

956A:金屬間介電層 956A: Intermetal dielectric layer

961A:金屬間介電層 961A: Intermetal dielectric layer

962A:金屬間介電層 962A: Intermetal dielectric layer

963A:金屬間介電層 963A: Intermetal dielectric layer

964A:金屬間介電層 964A: Intermetallic dielectric layer

965A:金屬間介電層 965A: Intermetal dielectric layer

966A:金屬間介電層 966A: Intermetal Dielectric Layer

1000:佈局 1000: layout

1000A:積體電路結構 1000A: integrated circuit structure

1001A:基板 1001A: Substrate

1002A:元件 1002A: Components

1003A:鰭片 1003A: fins

1004A:源極/汲極區域 1004A: Source/Drain Region

1005A:淺溝槽隔離區域 1005A: Shallow trench isolation region

1006A:閘極結構 1006A: Gate structure

1007A:閘極間隔物 1007A: Gate Spacer

1008A:接觸件 1008A: Contact

1011:金屬線 1011: metal wire

1012:金屬線 1012: metal wire

1013:金屬線 1013: metal wire

1014:金屬線 1014: metal wire

1015:金屬線 1015: metal wire

1016:金屬線 1016: metal wire

1017:金屬線 1017: metal wire

1018:金屬線 1018: metal wire

1011A:金屬線 1011A: metal wire

1012A:金屬線 1012A: metal wire

1013A:金屬線 1013A: metal wire

1014A:金屬線 1014A: metal wire

1015A:金屬線 1015A: metal wire

1016A:金屬線 1016A: metal wire

1017A:金屬線 1017A: metal wire

1018A:金屬線 1018A: Metal wire

1021:通孔 1021: through hole

1022:通孔 1022: through hole

1023:通孔 1023: through hole

1024:通孔 1024: through hole

1025:通孔 1025: through hole

1026:通孔 1026: through hole

1027:通孔 1027: through hole

1028:通孔 1028: through hole

1021A:通孔 1021A: Through hole

1022A:通孔 1022A: Through hole

1023A:通孔 1023A: Through hole

1024A:通孔 1024A: Through hole

1025A:通孔 1025A: Through hole

1026A:通孔 1026A: Through hole

1027A:通孔 1027A: Through hole

1028A:通孔 1028A: Through hole

1030A:互連結構 1030A: Interconnect structure

1041A:層間介電層 1041A: interlayer dielectric layer

1051A:金屬間介電層 1051A: Intermetal dielectric layer

1052A:金屬間介電層 1052A: Intermetal dielectric layer

1053A:金屬間介電層 1053A: Intermetal dielectric layer

1054A:金屬間介電層 1054A: Intermetal dielectric layer

1055A:金屬間介電層 1055A: Intermetal dielectric layer

1056A:金屬間介電層 1056A: Intermetal dielectric layer

1057A:金屬間介電層 1057A: Intermetal dielectric layer

1058A:金屬間介電層 1058A: Intermetal dielectric layer

1061A:金屬間介電層 1061A: Intermetal dielectric layer

1062A:金屬間介電層 1062A: Intermetal dielectric layer

1063A:金屬間介電層 1063A: Intermetal dielectric layer

1064A:金屬間介電層 1064A: Intermetal dielectric layer

1065A:金屬間介電層 1065A: Intermetal dielectric layer

1066A:金屬間介電層 1066A: Intermetal dielectric layer

1067A:金屬間介電層 1067A: Intermetal dielectric layer

1068A:金屬間介電層 1068A: Intermetal dielectric layer

1101:程序 1101: Procedure

1102:程序 1102: procedure

1103:程序 1103: procedure

1104:程序 1104: procedure

1200:電子設計自動化系統 1200: Electronic Design Automation Systems

1202:處理器 1202: Processor

1204:儲存媒體 1204: storage media

1206:指令集 1206: instruction set

1207:設計佈局 1207: Design layout

1208:匯流排 1208: Bus

1209:設計規則檢查平台 1209: Design rule checking platform

1210:輸入/輸出介面 1210: input/output interface

1212:網路介面 1212: Network interface

1214:網路 1214: network

1216:使用者介面 1216: user interface

1220:積體電路製造商 1220:Manufacturer of integrated circuits

1222:積體電路製造工具 1222: Integrated circuit manufacturing tools

1230:遮罩室 1230: mask room

1232:遮罩製造工具 1232: Mask Maker Tool

GD:閘極介電層 GD: gate dielectric layer

GM:閘極金屬層 GM: gate metal layer

Group_1:模型 Group_1: Model

Group_2:模型 Group_2: Model

Group_3:模型 Group_3: Model

Group_4:模型 Group_4: Model

Group_5:模型 Group_5: Model

Group_6:模型 Group_6: Model

Group_7:模型 Group_7: Model

Group_8:模型 Group_8: Model

Group_9:模型 Group_9: Model

Group_10:模型 Group_10: Model

Group_11:模型 Group_11: Model

Group_12:模型 Group_12: Model

Group_13:模型 Group_13: Model

Group_14:模型 Group_14: Model

Group_15:模型 Group_15: Model

Group_16:模型 Group_16: Model

Group_17:模型 Group_17: Model

H31:線高 H31: line height

H32:線高 H32: line height

H33:線高 H33: line height

H34:線高 H34: line height

H35:線高 H35: line height

H36:線高 H36: line height

H51:線高 H51: line height

H52:線高 H52: line height

H53:線高 H53: line height

H54:線高 H54: line height

H65:線高 H65: line height

H66:線高 H66: line height

H71:線高 H71: line height

H72:線高 H72: line height

H73:線高 H73: line height

H74:線高 H74: line height

H75:線高 H75: line height

H81:線高 H81: line height

H82:線高 H82: line height

H83:線高 H83: line height

H84:線高 H84: line height

H85:線高 H85: line height

H91:線高 H91: line height

H92:線高 H92: line height

H93:線高 H93: line height

H94:線高 H94: line height

H95:線高 H95: line height

H96:線高 H96: line height

H101:線高 H101: line height

H102:線高 H102: line height

H103:線高 H103: line height

H104:線高 H104: line height

H105:線高 H105: line height

H106:線高 H106: line height

H107:線高 H107: line height

H108:線高 H108: line height

M1:金屬化層 M1: metallization layer

M2:金屬化層 M2: metallization layer

M3:金屬化層 M3: metallization layer

M4:金屬化層 M4: metallization layer

M5:金屬化層 M5: metallization layer

M6:金屬化層 M6: metallization layer

M7:金屬化層 M7: metallization layer

M8:金屬化層 M8: metallization layer

M1A:金屬化層 M1A: metallization layer

M2A:金屬化層 M2A: metallization layer

M3A:金屬化層 M3A: metallization layer

M4A:金屬化層 M4A: metallization layer

M5A:金屬化層 M5A: metallization layer

M6A:金屬化層 M6A: metallization layer

M7A:金屬化層 M7A: metallization layer

M8A:金屬化層 M8A: metallization layer

N1:電路網 N1: circuit network

N2:電路網 N2: circuit network

S31:線至線間距 S31: Line-to-Line Spacing

S32:線至線間距 S32: Line-to-Line Spacing

S33:線至線間距 S33: Line-to-Line Spacing

S34:線至線間距 S34: Line-to-Line Spacing

S35:線至線間距 S35: Line-to-Line Spacing

S36:線至線間距 S36: Line-to-Line Spacing

S51:線至線間距 S51: Line-to-Line Spacing

S52:線至線間距 S52: Line-to-Line Spacing

S53:線至線間距 S53: Line-to-Line Spacing

S54:線至線間距 S54: Line-to-Line Spacing

S65:線至線間距 S65: Line-to-Line Spacing

S66:線至線間距 S66: Line-to-Line Spacing

S71:線至線間距 S71: Line-to-Line Spacing

S72:線至線間距 S72: Line-to-Line Spacing

S73:線至線間距 S73: Line-to-Line Spacing

S74:線至線間距 S74: Line-to-Line Spacing

S75:線至線間距 S75: Line-to-Line Spacing

S81:線至線間距 S81: Line-to-Line Spacing

S82:線至線間距 S82: Line-to-Line Spacing

S83:線至線間距 S83: Line-to-Line Spacing

S84:線至線間距 S84: Line-to-Line Spacing

S85:線至線間距 S85: Line-to-Line Spacing

S91:線至線間距 S91: Line-to-Line Spacing

S92:線至線間距 S92: Line-to-Line Spacing

S93:線至線間距 S93: Line-to-Line Spacing

S94:線至線間距 S94: Line-to-Line Spacing

S95:線至線間距 S95: Line-to-Line Spacing

S96:線至線間距 S96: Line-to-Line Spacing

S101:線至線間距 S101: Line-to-Line Spacing

S102:線至線間距 S102: Line-to-Line Spacing

S103:線至線間距 S103: Line-to-Line Spacing

S104:線至線間距 S104: Line-to-Line Spacing

S105:線至線間距 S105: Line-to-Line Spacing

S106:線至線間距 S106: Line-to-Line Spacing

S107:線至線間距 S107: Line-to-Line Spacing

S108:線至線間距 S108: Line-to-Line Spacing

W31:線寬 W31: Line width

W32:線寬 W32: Line width

W33:線寬 W33: Line width

W34:線寬 W34: Line width

W35:線寬 W35: Line width

W36:線寬 W36: Line width

W51:線寬 W51: Line width

W52:線寬 W52: Line width

W53:線寬 W53: Line width

W54:線寬 W54: Line width

W65:線寬 W65: Line width

W66:線寬 W66: Line width

W71:線寬 W71: Line width

W72:線寬 W72: Line width

W73:線寬 W73: Line width

W74:線寬 W74: Line width

W75:線寬 W75: Line width

W81:線寬 W81: Line width

W82:線寬 W82: Line width

W83:線寬 W83: Line width

W84:線寬 W84: Line width

W85:線寬 W85: Line width

W91:線寬 W91: Line width

W92:線寬 W92: Line width

W93:線寬 W93: Line width

W94:線寬 W94: Line width

W95:線寬 W95: Line width

W96:線寬 W96: Line width

W101:線寬 W101: Line width

W102:線寬 W102: Line width

W103:線寬 W103: Line width

W104:線寬 W104: Line width

W105:線寬 W105: Line width

W106:線寬 W106: Line width

W107:線寬 W107: Line width

W108:線寬 W108: Line width

X:方向 X: direction

Y:方向 Y: Direction

Z:方向 Z: Direction

當結合附圖閱讀時，根據以下詳細描述可以最好地理解本公開的各方面。應理解，根據行業中的標準實踐，各種特徵未按比例繪製。實際上，為了清楚起見，可以任意地增加或減小各種特徵的尺寸。 Aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It should be understood that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity.

第1圖是根據部分實施例，用於製造積體電路的示例性製造流程的流程圖。 FIG. 1 is a flowchart of an exemplary fabrication process for fabricating integrated circuits in accordance with some embodiments.

第2圖是根據部分實施例中，自動擺置和佈線(automatic placement and routing,APR)功能的示意圖。 FIG. 2 is a schematic diagram of an automatic placement and routing (APR) function according to some embodiments.

第3A圖是在本公開的部分實施例中，包括群組化的金屬化層之示例性模型的佈局的立體圖。 Figure 3A is a perspective view of the layout of an exemplary model including grouped metallization layers in some embodiments of the present disclosure.

第3B圖是繪示第3A圖的佈局中，金屬化層之間的金屬線線寬差異的示意圖。 FIG. 3B is a schematic diagram illustrating the difference in line width of metal lines between metallization layers in the layout of FIG. 3A .

第3C圖是根據本公開的部分實施例，使用第3A圖的佈局製造之積體電路結構的剖面圖。 Figure 3C is a cross-sectional view of an integrated circuit structure fabricated using the layout of Figure 3A in accordance with some embodiments of the present disclosure.

第4A圖是繪示在具有與第3A圖的佈局相似之金屬化層的佈局中佈線示例性電路網的示意圖。 FIG. 4A is a schematic diagram illustrating routing an exemplary circuit net in a layout having metallization layers similar to the layout of FIG. 3A.

第4B圖是根據本公開的部分實施例，使用第4A圖的佈局製造之積體電路結構的剖面圖。 FIG. 4B is a cross-sectional view of an integrated circuit structure fabricated using the layout of FIG. 4A in accordance with some embodiments of the present disclosure.

第5A圖是在本公開的部分實施例中，包括群組化的金屬化層之示例性模型的佈局的立體圖。 Figure 5A is a perspective view of the layout of an exemplary model including grouped metallization layers in some embodiments of the present disclosure.

第5B圖是繪示第5A圖的佈局中，金屬化層之間的金屬線線寬差異的示意圖。 FIG. 5B is a schematic diagram illustrating the difference in line width of metal lines between metallization layers in the layout of FIG. 5A .

第5C圖是根據本公開的部分實施例，使用第5A圖的佈局製造的積體電路結構的剖面圖。 FIG. 5C is a cross-sectional view of an integrated circuit structure fabricated using the layout of FIG. 5A in accordance with some embodiments of the present disclosure.

第6A圖是在本公開的部分實施例中，包括群組化的金屬化層之示例性模型的佈局的立體圖。 Figure 6A is a perspective view of the layout of an exemplary model including grouped metallization layers in some embodiments of the present disclosure.

第6B圖是繪示第6A圖的佈局中，金屬化層之間的金屬線線寬差異的示意圖。 FIG. 6B is a schematic diagram illustrating the difference in line width of metal lines between metallization layers in the layout of FIG. 6A.

第6C圖是根據本公開的部分實施例，使用第6A圖的佈局製造之積體電路結構的剖面圖。 FIG. 6C is a cross-sectional view of an integrated circuit structure fabricated using the layout of FIG. 6A in accordance with some embodiments of the present disclosure.

第7A圖是在本公開的部分實施例中，包括群組化的金屬化層之示例性模型的佈局的立體圖。 Figure 7A is a perspective view of a layout of an exemplary model including grouped metallization layers in some embodiments of the present disclosure.

第7B圖是繪示第7A圖的佈局中，金屬化層之間的金屬線線寬差異的示意圖。 FIG. 7B is a schematic diagram illustrating the difference in line width of metal lines between metallization layers in the layout of FIG. 7A.

第7C圖是根據本公開的部分實施例，使用第7A圖的佈局製造之積體電路結構的剖面圖。 FIG. 7C is a cross-sectional view of an integrated circuit structure fabricated using the layout of FIG. 7A in accordance with some embodiments of the present disclosure.

第8A圖是在本公開的部分實施例中，包括群組化的金屬化層之示例性模型的佈局的立體圖。 Figure 8A is a perspective view of the layout of an exemplary model including grouped metallization layers in some embodiments of the present disclosure.

第8B圖是繪示第8A圖的佈局中，金屬化層之間的金屬線線寬差異的示意圖。 FIG. 8B is a schematic diagram illustrating the difference in line width of metal lines between metallization layers in the layout of FIG. 8A .

第8C圖是根據本公開的部分實施例，使用第8A圖的佈局製造之積體電路結構的剖面圖。 FIG. 8C is a cross-sectional view of an integrated circuit structure fabricated using the layout of FIG. 8A in accordance with some embodiments of the present disclosure.

第9A圖是在本公開的部分實施例中，包括群組化的金屬化層之示例性模型的佈局的立體圖。 Figure 9A is a perspective view of the layout of an exemplary model including grouped metallization layers in some embodiments of the present disclosure.

第9B圖是繪示第9A圖的佈局中，金屬化層之間的金屬線線寬差異的示意圖。 FIG. 9B is a schematic diagram illustrating the difference in line width of metal lines between metallization layers in the layout of FIG. 9A .

第9C圖是根據本公開的部分實施例，使用第9A圖的佈局製造之積體電路結構的剖面圖。 FIG. 9C is a cross-sectional view of an integrated circuit structure fabricated using the layout of FIG. 9A in accordance with some embodiments of the present disclosure.

第10A圖是在本公開的部分實施例中，包括群組化的金屬化層之示例性模型的佈局的立體圖。 FIG. 10A is a perspective view of a layout of an exemplary model including grouped metallization layers in some embodiments of the present disclosure.

第10B圖是繪示第10A圖的佈局中，金屬化層之間的金屬線線寬差異的示意圖。 FIG. 10B is a schematic diagram illustrating the difference in metal line width between metallization layers in the layout of FIG. 10A.

第10C圖是根據本公開的部分實施例，使用第10A圖的佈局製造之積體電路結構的剖面圖。 FIG. 10C is a cross-sectional view of an integrated circuit structure fabricated using the layout of FIG. 10A in accordance with some embodiments of the present disclosure.

第11圖是繪示根據本公開的部分實施例中，自動擺置和佈線功能的一部分的流程圖。 FIG. 11 is a flowchart illustrating a portion of an automatic placement and routing function in accordance with some embodiments of the present disclosure.

第12圖是根據本公開的部分實施例中，電子設計自動化(electronic design automation,EDA)系統的示意圖。 FIG. 12 is a schematic diagram of an electronic design automation (EDA) system according to some embodiments of the present disclosure.

以下公開提供了用於實現所提供的主題的不同特徵的許多不同的實施例或示例。以下描述元件和配置的特定示例以簡化本公開。當然，這些僅僅是示例，而無意於進行限制。例如，在下面的描述中，在第二特徵之上或上方形成第一特徵可以包括第一特徵和第二特徵以直接接觸形成的實施例，並且還可以包括在第一特徵和第二特徵之間形成附加特徵，使得第一特徵和第二特徵可以不直接接觸的實施例。另外，本公開可以在各個示例中重複參考數字和/或文字。此重複是出於簡單和清楚的目的，並且其本身並不指示所討論的各種實施例和/或配置之間的關係。 The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first feature and the second feature are formed in direct contact, and may also include embodiments where the first feature and the second feature are formed in direct contact. An embodiment in which an additional feature is formed between such that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or words in various examples. This repetition is for simplicity and clarity and by itself does not indicate a relationship between the various embodiments and/or configurations discussed.

更甚者，空間相對的詞彙(例如，「低於」、「下方」、「之下」、「上方」、「之上」等相關詞彙)於此用以簡單描述如圖所示之元件或特徵與另一元件或特徵的關係。在使用或程序時，除了圖中所繪示的轉向之外，這些空間相對的詞彙涵蓋元件的不同的轉向。再者，這些元件可旋轉(旋轉90度或其他角度)，且在此使用的空間相對描述語可作對應的解讀。 Furthermore, spatially relative terms (eg, relative terms such as "below", "below", "under", "above", "above", etc.) are used herein to simply describe elements as shown or The relationship of a feature to another element or feature. These spatially relative terms encompass different orientations of elements in use or procedure other than the orientation depicted in the figures. Furthermore, these elements may be rotated (rotated by 90 degrees or other angles), and the spatially relative descriptors used herein shall be interpreted accordingly.

積體電路包括許多元件(例如，電晶體、電阻器和電容器)。這些元件最初彼此隔離，隨後使用形成在覆蓋這些電路元件的複數個金屬化層中的金屬線彼此互連。金屬線連接各個元件以構成一個電路單元(cell)，包括向此元件供電，並在全局範圍內(即，在晶片層次)將各個元件彼此連接，以實現積體電路的預期功能。單元擺置 (cell placement)和金屬線的佈線(routing)是積體電路總體設計過程的一部分。 Integrated circuits include many components (eg, transistors, resistors, and capacitors). These elements are initially isolated from each other and then interconnected to each other using metal lines formed in a plurality of metallization layers covering the circuit elements. Metal wires connect various components to form a circuit unit (cell), including supplying power to the component, and globally (ie, at the wafer level) connecting various components to each other, so as to realize the intended function of the integrated circuit. Unit placement (cell placement) and metal line routing (routing) are part of the overall design process of integrated circuits.

在積體電路製造中，隨著先進技術節點(例如，10奈米(nm)、7nm、5nm、3nm技術節點)的發展，發生了元件縮小(或「微縮」)過程。在元件縮小或微縮過程中，積體電路或其佈局從較大的尺寸縮小為較小的尺寸。縮小積體電路和積體電路佈局，以便將更多的元件裝配到基板上，以提高後代半導體元件的性能。縮小積體電路和積體電路佈局，以降低功耗並適應積體電路中較小尺寸的元件。 In integrated circuit manufacturing, as advanced technology nodes (eg, 10 nanometer (nm), 7nm, 5nm, 3nm technology nodes) are advanced, a process of component shrinkage (or "scaling") occurs. In component scaling or scaling, an integrated circuit or its layout is reduced from a larger size to a smaller size. Shrinking ICs and IC layouts to fit more components onto a substrate to improve the performance of future generations of semiconductor components. Shrinking ICs and IC layouts to reduce power consumption and accommodate smaller sized components in ICs.

當使積體電路中的元件縮小時，用於連接元件的互連金屬線也沿至少一維縮小。因此，在部分實施例中，元件的縮小伴隨著互連金屬線之線寬的減小。然而，線寬的減小會導致由金屬線形成的電路網(即，在半導體元件的節點或端子之間共同地形成電路的導電路徑)的電阻增大，這將降低積體電路的性能(例如，電阻電容延遲(RC delay))。因此，與下部金屬化層中那些較細的線(即，具有較小的線寬)相比，一些上部金屬化層中的金屬線被設計為較粗的線(即，具有較大的線寬)，以減輕由較細的線產生之電阻電容延遲的影響。為了減少長電路網的電阻，自動擺置和佈線(automatic placement and routing(APR))程序可以將長電路網佈線在較粗的金屬線上。然而，將長電路網佈線在上部金屬化層之較粗的金屬線上會伴隨著用於到達上部金屬化層之更多的通孔，這 反過來會降低如上所述之較粗的線的益處。本公開的實施例描述了一種在下部金屬化層中設計和製造較粗的金屬線的方法，此方法將允許佈線器在下部金屬化層上佈線長電路網，從而降低了長電路網中的電阻。 When the components in an integrated circuit are scaled down, the interconnect metal lines used to connect the components are also scaled down in at least one dimension. Therefore, in some embodiments, device scaling is accompanied by a reduction in the line width of the interconnecting metal lines. However, the reduction in line width results in an increase in the resistance of the circuit net formed by the metal lines (i.e., the conductive paths that collectively form a circuit between the nodes or terminals of the semiconductor element), which will degrade the performance of the integrated circuit ( For example, resistor capacitor delay (RC delay)). Thus, some metal lines in the upper metallization layer are designed as thicker lines (i.e., with larger line width) than those thinner lines (i.e., with smaller line width) in the lower metallization layer. wide) to mitigate the effects of resistive-capacitive delays caused by thinner lines. To reduce the resistance of long nets, an automatic placement and routing (APR) program can route long nets on thicker wires. However, routing long nets on thicker metal lines in the upper metallization layer comes with more vias for reaching the upper metallization layer, which This in turn reduces the benefit of thicker wires as described above. Embodiments of the present disclosure describe a method of designing and fabricating thicker metal lines in the lower metallization layer, which will allow routers to route long nets on the lower metallization layer, thereby reducing the resistance.

第1圖是根據部分實施例用於製造積體電路的示例性製造流程100的流程圖。製造流程100利用至少一個電子設計自動化(electronic design automation,EDA)工具和至少一個製造工具來執行流程100中的一個或多個步驟。在部分實施例中，此流程100中的步驟可以由不同的企業來執行(例如，設計室、遮罩室和/或半導體元件製造商/製造廠)，這些企業在與積體電路相關的設計、開發、製造週期和/或服務方面相互影響。在部分實施例中，設計室、遮罩室和製造廠中的兩個或更多個由單個較大的公司擁有，因此，流程100可以由單個企業執行。在部分實施例中，設計室、遮罩室和製造廠中的兩個或更多個在公共設施中共存，因此，可以使用公共資源來執行流程100。第1圖所示的流程100是示例性的。修改流程100中的步驟(例如，改變步驟的順序、分割步驟以及刪除或添加步驟)均在本公開的預期範圍內。 FIG. 1 is a flowchart of an exemplary fabrication process 100 for fabricating integrated circuits in accordance with some embodiments. The manufacturing process 100 utilizes at least one electronic design automation (EDA) tool and at least one manufacturing tool to perform one or more steps in the process 100 . In some embodiments, the steps in this process 100 may be performed by different enterprises (e.g., design houses, mask houses, and/or semiconductor device manufacturers/fabs) that are involved in the design of integrated circuits. , development, manufacturing cycle and/or service aspects. In some embodiments, two or more of the design studio, mask house, and fabrication facility are owned by a single larger company, and thus, process 100 may be performed by a single enterprise. In some embodiments, two or more of the design room, the mask room, and the manufacturing plant co-exist in a common facility, so that common resources can be used to perform process 100 . The process 100 shown in Figure 1 is exemplary. It is within the contemplated scope of the present disclosure to modify steps in process 100 (eg, change the order of steps, split steps, and delete or add steps).

最初，在流程100的系統設計步驟102中為目標晶片的系統架構提供了高階描述。在步驟102，根據設計規範決定晶片功能以及性能要求。晶片功能由相應的示意功能模組或區塊表示。另外，可以尋求優化或性能折衷以在可接受的成本和功率水平上達到設計規範。 Initially, a high-level description is provided for the system architecture of the target wafer in system design step 102 of process 100 . In step 102, chip function and performance requirements are determined according to design specifications. Chip functions are represented by corresponding schematic functional modules or blocks. Additionally, optimization or performance tradeoffs may be sought to achieve design specifications at acceptable cost and power levels.

在流程100的邏輯設計步驟104，使用硬體描述語言(hardware description language)在暫存器轉移層次(register transfer level,RTL)中描述功能模組或區塊。通常使用市售的語言工具(例如，Verilog或VHDL)。在部分實施例中，在邏輯設計步驟104中執行初步功能檢查，以驗證所實現的功能是否符合系統設計步驟102中提出的規範。 In the logic design step 104 of the process 100, a hardware description language (hardware description language) is used to describe the functional modules or blocks in the register transfer level (RTL). Typically a commercially available language tool (eg, Verilog or VHDL) is used. In some embodiments, a preliminary functional check is performed in the logic design step 104 to verify whether the implemented functions conform to the specifications proposed in the system design step 102 .

隨後，在流程100的合成(synthesis)步驟106，將暫存器轉移層次描述中的模組轉換為電路網表數據(netlist data)，並在其中建立每個功能模組的電路結構(例如，邏輯閘極和暫存器)。在部分實施例中，進行邏輯閘極和暫存器到標準元件庫(standard cell library)中可用元件的技術映射(technology mapping)。此外，提供電路網表數據以在邏輯閘層次(gate-level)描述晶片的功能關係。在部分實施例中，電路網表數據從邏輯閘層次視圖轉換為電晶體層次(transistor-level)視圖。 Subsequently, in the synthesis (synthesis) step 106 of the process 100, the modules in the register transfer hierarchy description are converted into circuit netlist data (netlist data), and the circuit structure of each functional module is established therein (for example, logic gates and scratchpads). In some embodiments, technology mapping of logic gates and registers to cells available in a standard cell library is performed. In addition, circuit netlist data is provided to describe the functional relationship of the chip at the gate-level. In some embodiments, circuit netlist data is converted from a gate-level view to a transistor-level view.

隨後，在佈局前模擬(pre-layout simulation)步驟108驗證邏輯閘層次電路網表數據。在步驟108的驗證過程中，如果某些功能在模擬中未能通過驗證，則流程100可以暫時中止或可以返回到步驟102或104以進行進一步的修改。在佈局前模擬步驟108之後，晶片設計已經透過初步驗證，並且完成前端設計過程。接下來，進行後端實體設計過程。 Subsequently, a pre-layout simulation step 108 verifies the gate-level circuit netlist data. During the verification process of step 108, if some functions fail to pass the verification in the simulation, the process 100 may be temporarily suspended or may return to step 102 or 104 for further modification. After the pre-layout simulation step 108, the chip design has passed preliminary verification and the front-end design process is complete. Next, proceed to the back-end entity design process.

在擺置和佈線步驟110，實現了代表在前端設計流程中所決定之晶片的實體架構。佈局開發依次涉及擺置(placement)程序和佈線(routing)程序。在擺置程序中決定積體電路晶片的元件(例如，電晶體)之詳細結構和相關的幾何形狀比例。在擺置程序之後，將佈線不同元件之間的互連。擺置和佈線程序均符合設計規則檢查(design rule check,DRC)的要求，從而滿足晶片的製造要求。在部分實施例中，在數位電路的擺置和佈線步驟中執行時脈樹合成(clock tree synthesis,CTS)程序，其中將時脈產生器(clock generators)和電路結合到設計中。在部分實施例中，在初步佈局程序之後執行佈線後程序，以便解決初步佈局程序的時序問題。一旦完成了擺置和佈線步驟110，就建立了擺置和佈線的佈局，並相應地生成了電路網表以及關於擺置和佈線的數據。 In a place and route step 110, a physical architecture representing the chip determined in the front-end design flow is realized. Layout development involves, in turn, a placement program and a routing program. The detailed structure and associated geometrical proportions of the components (eg transistors) of the IC chip are determined during the placement process. After the placement procedure, the interconnections between the different components are routed. Both the placement and routing procedures meet the requirements of design rule check (DRC), thereby meeting the manufacturing requirements of the chip. In some embodiments, a clock tree synthesis (CTS) process is performed during the digital circuit placement and routing steps, where clock generators and circuits are incorporated into the design. In some embodiments, a post-routing procedure is performed after the preliminary placement procedure to resolve timing issues of the preliminary placement procedure. Once the place and route step 110 is completed, the place and route layout is established and a circuit netlist is generated accordingly along with data about the place and route.

在流程100的參數提取步驟112中，進行佈局參數提取(layout parameter extraction,LPE)程序，以從由擺置和佈線步驟110產生的佈局中得出與佈局相關的參數(例如，寄生電阻和電容)。隨後，生成佈局後(post-layout)電路網表數據，其包括與佈局相關的參數。 In the parameter extraction step 112 of the process 100, a layout parameter extraction (layout parameter extraction, LPE) program is performed to obtain layout-related parameters (for example, parasitic resistance and capacitance) from the layout generated by the placement and routing step 110 ). Subsequently, post-layout circuit netlist data including layout-related parameters is generated.

在流程100的佈局後模擬步驟114，可以考慮使用先前步驟中獲取的參數來執行實體驗證。進行電晶體層次行為的模擬，以檢查晶片性能是否滿足系統規格的要求。在部分實施例中，執行佈局後模擬以最小化在晶片製造過 程中電路相關的問題或佈局困難的可能性。 In the post-layout simulation step 114 of the process 100, entity verification may be performed taking into account the parameters obtained in the previous steps. Simulations of transistor-level behavior are performed to check that die performance meets system specifications. In some embodiments, post-layout simulations are performed to minimize the possibility of circuit-related problems or layout difficulties during the process.

接下來，在流程100的步驟116中，決定佈局後電路網表(netlist)是否符合設計規範。如果符合，則在步驟118接受電路設計，然後可以結束設計。積體電路晶片是根據認可的佈局後電路網表製造的。然而，如果佈局後模擬的結果是不理想的，則流程100循環回到先前的步驟以調整功能或結構。例如，流程100可以循環回到擺置和佈線步驟110，並在擺置和佈線步驟110中重新佈局，以從實體角度解決問題。可替代地，若問題不能在後端實體設計過程中解決，則流程100可以退回到更早的步驟102或104，以從功能層次改寫晶片設計。 Next, in step 116 of the process 100, it is determined whether the circuit netlist (netlist) after layout meets the design specification. If so, the circuit design is accepted at step 118 and the design can then be finalized. Integrated circuit chips are fabricated according to approved post-layout circuit netlists. However, if the results of the post-layout simulation are unsatisfactory, the process 100 loops back to the previous steps to adjust the function or structure. For example, the process 100 may loop back to the place and route step 110 and re-layout in the place and route step 110 to solve the problem from a physical perspective. Alternatively, if the problem cannot be resolved during the back-end physical design process, the process 100 may return to earlier steps 102 or 104 to rewrite the chip design from a functional level.

在流程100的遮罩製造步驟120，基於在步驟118接受的佈局後電路網表製造一個或複數個光罩。例如，遮罩室使用在步驟118中接受的佈局來製造一個或多個光罩(可互換地稱為遮罩)，以根據佈局製造積體電路晶片的各個層。在部分實施例中，遮罩室執行遮罩數據準備，其將設計佈局翻譯成代表性數據文件(representative data file，RDF)。遮罩數據準備將代表性數據文件提供給遮罩寫入器。遮罩寫入器將代表性數據文件轉換為基板上的圖像以形成光罩。光罩是圖案化的遮罩，用於允許特定波長範圍內的光通過，同時阻擋特定波長範圍外的光，以在光敏層(例如，晶片上的光阻層)上形成特徵圖案。在部分實施例中，多層佈局電路網表可以使用複數個光罩，其中在相應的光罩中建立每一層中的特徵圖案。因此，在 隨後的積體電路製造步驟122中，可透過微影方法將光罩上佈局特徵的幾何形狀比例轉移到光敏層上。 At mask fabrication step 120 of process 100 , one or more reticles are fabricated based on the post-layout circuit netlist received at step 118 . For example, the mask house fabricates one or more photomasks (interchangeably referred to as masks) using the layout accepted in step 118 to fabricate the various layers of the integrated circuit wafer according to the layout. In some embodiments, the mask room performs mask data preparation, which translates the design layout into a representative data file (RDF). Mask data preparation provides a representative data file to the mask writer. Mask writers convert representative data files into images on substrates to form reticles. A photomask is a patterned mask used to allow light within a specific wavelength range to pass while blocking light outside a specific wavelength range to form a pattern of features on a photosensitive layer (eg, a photoresist layer on a wafer). In some embodiments, a multi-layer layout circuit netlist may use a plurality of reticles in which the feature patterns in each layer are created in corresponding reticles. Thus, in In the subsequent integrated circuit fabrication step 122, the geometric proportions of the layout features on the mask can be transferred to the photosensitive layer by lithography.

在流程100的積體電路製造步驟122中，使用在遮罩製造步驟120中製造的光罩，以在晶片上製造積體電路。製造可以涉及各種半導體製造程序(例如，微影、蝕刻、沉積和熱擴散程序)。在部分實施例中，可以在積體電路製造步驟122的中間或最後步驟中使用測試程序，以確保所製造的積體電路的實體和功能完整性。分割程序用於將晶片分離為單獨的積體電路晶片(或晶粒)。如此，就完成了積體電路晶片的製造。 In the integrated circuit fabrication step 122 of the process 100, the photomask produced in the mask fabrication step 120 is used to fabricate the integrated circuit on the wafer. Fabrication may involve various semiconductor fabrication procedures (eg, lithography, etching, deposition, and thermal diffusion procedures). In some embodiments, testing procedures may be used during intermediate or final steps of the integrated circuit fabrication step 122 to ensure the physical and functional integrity of the fabricated integrated circuit. Singulation procedures are used to separate the wafer into individual integrated circuit wafers (or dies). In this way, the fabrication of the integrated circuit chip is completed.

第2圖是根據部分實施例的自動擺置和佈線功能200的示意圖。自動擺置和佈線功能200可以對應於第1圖中的步驟110的擺置和佈線程序。第2圖所示的自動擺置和佈線功能中的程序是示例性的。對程序的一些修改(例如，改變程序的順序、分割程序以及刪除或添加程序)都在本公開的預期範圍內。 FIG. 2 is a schematic diagram of an automatic placement and routing function 200 according to some embodiments. The automatic place and route function 200 may correspond to the place and route procedure of step 110 in FIG. 1 . The program in the automatic placement and routing function shown in Figure 2 is exemplary. Some modifications to the programs (eg, changing the order of the programs, dividing the programs, and deleting or adding programs) are within the contemplated scope of the present disclosure.

最初，自動擺置和佈線功能200接收或提供與半導體製造過程、電路網表數據204和元件庫206有關的技術文件202。例如，在自動擺置和佈線庫/數據庫208中定義了多個群組化的金屬化層的模型，以擴展或補充設計規則，從而為自動擺置和佈線功能200建立群組化的金屬化層模型的庫。接收或提供金屬電阻訊息210以用於分析群組化的金屬化層的模型。在程序212中，基於金屬電阻訊息210分析群組化的金屬化層的模型。此分析包括諸如 基於金屬電阻訊息210計算由群組化的金屬化層的每個模型產生的電阻、電容和/或信號延遲。 Initially, the automated place and route function 200 receives or provides technical files 202 related to semiconductor manufacturing processes, circuit netlist data 204 and component libraries 206 . For example, multiple grouped metallization layer models are defined in the auto-place and route library/database 208 to extend or supplement the design rules to create grouped metallization for the auto-place and route function 200 A library of layer models. Metal resistance information 210 is received or provided for analysis of the grouped metallization model. In process 212 , a model of the grouped metallization layers is analyzed based on the metal resistance information 210 . This analysis includes things like The resistance, capacitance and/or signal delay produced by each model of the grouped metallization layers is calculated based on the metal resistance information 210 .

自動擺置和佈線功能200包括擺置程序214，以基於技術文件202、電路網表204、標準元件庫206和/或從程序212生成之群組化的金屬化層的模型的分析結果，將元件擺置在佈局中。作為示例而非限制，在擺置程序214中，將邏輯閘極的映射元件和電路塊的暫存器擺置在佈局中的特定位置。 The automatic placement and routing function 200 includes a placement program 214 to place Components are placed in layouts. By way of example and not limitation, in the placement process 214, the mapping elements of the logic gates and the registers of the circuit blocks are placed at specific locations in the layout.

自動擺置和佈線功能200還包括在擺置程序214之後在佈局上執行時脈樹合成程序216。在時脈樹合成程序216期間，將時脈訊號產生器(clock signal generators)擺置在佈局中，並且對佈局中的節點執行時序分析，以確保時序分配符合規範要求。在部分實施例中，時脈樹合成工具可以自動設計時脈樹，以將時脈訊號分配給響應於時脈訊號脈衝而改變狀態的複數個時脈元件(例如，正反器、暫存器和/或鎖存器)。時脈樹合成工具會試圖使時脈訊號從(接收來自外部源的時脈信號的)積體電路輸入端子傳播到每個時脈元件的距離相等，並以此方式對形成時脈樹的導體進行佈局。時脈樹合成工具可以在樹的分支點擺置緩衝器或放大器，以驅動分支點下游的所有緩衝器或時脈元件。基於對時脈樹的每個分支中的信號路徑延遲的估計，時脈樹合成工具可以透過在時脈樹的選定分支中插入附加的緩衝器來調整時脈樹的平衡，以調整這些分支中的路徑延遲，以確保時脈樹幾乎同時地將每個時 脈訊號脈衝傳送到每個時脈元件。 The automatic place and route function 200 also includes performing a clock tree synthesis procedure 216 on the layout after the placement procedure 214 . During the clock tree synthesis process 216, clock signal generators are placed in the layout and timing analysis is performed on the nodes in the layout to ensure that the timing assignments meet specification requirements. In some embodiments, a clock tree synthesis tool can automatically design a clock tree to distribute clock signals to a plurality of clock elements (e.g., flip-flops, registers, etc.) that change state in response to clock signal pulses. and/or latches). Clock tree synthesis tools attempt to equalize the distance that the clock signal propagates from the input terminal of the integrated circuit (receiving the clock signal from an external source) to each clock element, and in this way align the conductors that form the clock tree. Make a layout. Clock tree synthesis tools place buffers or amplifiers at branch points in the tree to drive all buffers or clock elements downstream of the branch point. Based on an estimate of the signal path delay in each branch of the clock tree, the clock tree synthesis tool can adjust the balance of the clock tree by inserting additional buffers in selected branches of the clock tree to adjust the path delays to ensure that the clock tree converts each clock nearly simultaneously Pulse signal pulses are sent to each clock element.

自動擺置和佈線功能200還包括佈線程序218，此佈線程序218基於技術文件202、電路網表204、標準元件庫206和/或基於由程序212產生之群組化的金屬化層的模型的分析結果來佈線金屬線以連接元件中的元件(例如，電晶體)。例如，在佈線程序218中，從庫208中選擇群組化的金屬化層中的一個或複數個模型，以便在佈局中將金屬化佈線層堆疊在元件(例如，電晶體)上。 The automatic placement and routing function 200 also includes a routing program 218 based on the technical file 202, the circuit netlist 204, the standard component library 206, and/or based on the model of the grouped metallization layers generated by the program 212. The results are analyzed to route metal lines to connect elements (eg, transistors) in the component. For example, in routing program 218, one or more models of grouped metallization layers are selected from library 208 to stack metallization routing layers on components (eg, transistors) in layout.

在自動擺置和佈線功能200的程序220中，對從程序218生成的擺置和佈線的佈局進行優化。優化包括諸如檢查擺置和佈線的佈局是否滿足合格的電路相關特性(例如，寄生電阻和電容)、製造標準和/或設計規範，然後，如果檢查結果不理想，則重複擺置程序214、時脈樹合成程序216和佈線程序，直到檢查結果合格為止。例如，初始佈局程序218從庫208中選擇群組化的金屬化層中的一個或複數個模型(例如，如第3A圖所示的模型Group_1和Group_2)，並且如果優化程序220中的檢查結果是不理想的，則自動擺置和佈線功能200可以循環回到佈線程序218以選擇其他群組化的金屬化層模型(例如，如第5A圖所示的模型Group_3和Group_4)以替換先前選擇的模型(例如，如第3A圖所示的模型Group_1和Group_2)。一旦完成自動擺置和佈線功能200，就可以基於優化的擺置和佈線的佈局來製造積體電路晶片(例如，如第1圖所示，透過執行製造流程100中的步驟112至 122)。 In a program 220 of the automatic place and route function 200, the placement and routing generated from the program 218 is optimized. Optimization includes, for example, checking whether the placement and routing layout meets acceptable circuit-related characteristics (e.g., parasitic resistance and capacitance), manufacturing standards, and/or design specifications, and then repeating the placement procedure 214 if the check result is not satisfactory. The vein tree synthesis program 216 and the wiring program until the inspection result is qualified. For example, initial layout program 218 selects one or more models of grouped metallization layers from library 208 (e.g., models Group_1 and Group_2 as shown in FIG. is not ideal, the auto-place and route function 200 may loop back to the route program 218 to select other grouped metallization layer models (e.g., models Group_3 and Group_4 as shown in FIG. 5A) to replace the previous selection models (for example, models Group_1 and Group_2 as shown in Figure 3A). Once the automatic place and route function 200 is completed, the integrated circuit die can be fabricated based on the optimized place and route layout (e.g., as shown in FIG. 122).

第3A圖至第10C圖繪示群組化的金屬化層的各種示例性模型和使用相應的模型製造的積體電路結構。這些模型是非限制性的示例，並且可以在第2圖所示的模型庫208中定義。自動擺置和佈線功能200可首先從模型庫208中選擇模型的任何組合，然後，如果優化程序220的檢查結果不理想，則可將選擇好的模型中的一個或多個用模型庫208中的一個或多個其他模型替換。這些示例性模型和相應的積體電路結構將在下面更詳細地描述。 3A-10C illustrate various exemplary models of grouped metallization layers and integrated circuit structures fabricated using the corresponding models. These models are non-limiting examples and may be defined in model library 208 shown in FIG. 2 . The automatic placement and routing function 200 can first select any combination of models from the model library 208, and then, if the inspection result of the optimization program 220 is not satisfactory, one or more of the selected models can be used in the model library 208. One or more other model replacements for . These exemplary models and corresponding integrated circuit structures are described in more detail below.

第3A圖是在本公開的部分實施例中包括群組化的金屬化層的示例性模型的佈局300的立體圖。第3B圖繪示在第3A圖的佈局中，金屬化層之間的金屬線線寬差異的示意圖。佈局300可用於製造如第3C圖所示的積體電路300A(亦可稱之為積體電路結構)。 FIG. 3A is a perspective view of a layout 300 of an exemplary model including grouped metallization layers in some embodiments of the present disclosure. FIG. 3B is a schematic diagram illustrating the difference in metal line width between metallization layers in the layout of FIG. 3A. The layout 300 can be used to fabricate an integrated circuit 300A (also referred to as an integrated circuit structure) as shown in FIG. 3C.

佈局300包括第一組金屬化層模型Group_1和第二組金屬化層模型Group_2，其中第二組金屬化層模型Group_2堆疊在第一組金屬化層模型Group_1上。可以在庫208中定義這些模型Group_1和Group_2(如第2圖所示)。第一組金屬化層模型Group_1包括第一金屬化層M1、位於第一金屬化層M1上的第二金屬化層M2和位於第二金屬化層M2上的第三金屬化層M3。 The layout 300 includes a first group of metallization layer models Group_1 and a second group of metallization layer models Group_2, wherein the second group of metallization layer models Group_2 is stacked on the first group of metallization layer models Group_1. These models Group_1 and Group_2 may be defined in library 208 (shown in FIG. 2 ). The first metallization layer model Group_1 includes a first metallization layer M1 , a second metallization layer M2 on the first metallization layer M1 , and a third metallization layer M3 on the second metallization layer M2 .

如第3A圖和第3B圖所示，第一金屬化層M1包括水平互連(例如，在半導體元件(例如，電晶體)上方水平或橫向地延伸的複數個第一金屬線311)，以及垂直 互連(例如，在第一金屬線311和半導體元件之間垂直地延伸的金屬通孔321)。如此，金屬通孔321在第一金屬線311和半導體元件之間提供電連接。如第3A圖所示，第一金屬線311沿著佈局300的第一方向(例如，X方向)延伸，並且沿著佈局300的第二方向(例如，Y方向)彼此間隔開。在部分實施例中，第二方向Y垂直於第一方向X。每個第一金屬線311均具有在Y方向上測量的第一線寬(line width)W31，並且每個第一金屬線311與相鄰的第一金屬線311在Y方向上以第一線至線間距(line-to-line spacing)S31間隔開。 As shown in FIGS. 3A and 3B, the first metallization layer M1 includes horizontal interconnects (for example, a plurality of first metal lines 311 extending horizontally or laterally above the semiconductor element (eg, transistor), and vertical An interconnection (eg, a metal via 321 extending vertically between the first metal line 311 and the semiconductor element). As such, the metal via 321 provides an electrical connection between the first metal line 311 and the semiconductor element. As shown in FIG. 3A , the first metal lines 311 extend along a first direction (eg, X direction) of the layout 300 and are spaced apart from each other along a second direction (eg, Y direction) of the layout 300 . In some embodiments, the second direction Y is perpendicular to the first direction X. Each first metal line 311 has a first line width (line width) W31 measured in the Y direction, and each first metal line 311 is separated from adjacent first metal lines 311 by a first line in the Y direction. Spaced apart by line-to-line spacing S31.

第二金屬化層M2也包括水平互連(例如，在第一金屬化層M1上方水平或橫向地延伸的複數個第二金屬線312)，以及垂直互連(例如，在第二金屬線312和第一金屬線311之間垂直地延伸的金屬通孔322)。因此，金屬通孔322在第二金屬線312和第一金屬線311之間提供電連接。第二金屬線312在Y方向上延伸並且在X方向上彼此間隔開。換句話說，第二金屬線312在垂直於第一金屬線311的長度方向上延伸。每個第二金屬線312均具有在X方向上測量的第一線寬W32，並且每個第二金屬線312與相鄰的第二金屬線312在X方向上相隔第二線至線間距S32。 The second metallization layer M2 also includes horizontal interconnections (for example, a plurality of second metal lines 312 extending horizontally or laterally above the first metallization layer M1), and vertical interconnections (for example, a plurality of second metal lines 312 extending above the first metallization layer M1). and the metal via 322 vertically extending between the first metal line 311). Thus, the metal via 322 provides an electrical connection between the second metal line 312 and the first metal line 311 . The second metal lines 312 extend in the Y direction and are spaced apart from each other in the X direction. In other words, the second metal line 312 extends in a direction perpendicular to the length of the first metal line 311 . Each second metal line 312 has a first line width W32 measured in the X direction, and each second metal line 312 is separated from adjacent second metal lines 312 by a second line-to-line spacing S32 in the X direction .

第三金屬化層M3也包括水平互連(例如，在第二金屬化層M2上方水平或橫向地延伸的複數個第二金屬線313)，以及垂直互連(例如，在第三金屬線313和第二 金屬線312之間垂直地延伸的金屬通孔323)。因此，金屬通孔323提供了在第三金屬線313和第二金屬線312之間的電連接。第三金屬線313沿著X方向延伸並且沿著Y方向彼此間隔開(如第3A圖所示)。換句話說，第三金屬線313在垂直於第二金屬線312的長度方向並且平行於第一金屬線311的長度方向上延伸。每個第三金屬線313均具有在Y上測量的第三線寬W33，並且每個第三金屬線313在Y方向上與相鄰的第二金屬線312間隔開第三線至線間距S33。 The third metallization layer M3 also includes horizontal interconnections (for example, a plurality of second metal lines 313 extending horizontally or laterally above the second metallization layer M2), and vertical interconnections (for example, in the third metal line 313 and second Metal vias 323 extending vertically between the metal lines 312). Thus, the metal via 323 provides an electrical connection between the third metal line 313 and the second metal line 312 . The third metal lines 313 extend along the X direction and are spaced apart from each other along the Y direction (as shown in FIG. 3A ). In other words, the third metal line 313 extends perpendicular to the length direction of the second metal line 312 and parallel to the length direction of the first metal line 311 . Each third metal line 313 has a third line width W33 measured in Y, and each third metal line 313 is spaced apart from an adjacent second metal line 312 by a third line-to-line spacing S33 in the Y direction.

第一金屬線311的第一線寬W31小於第二金屬線312的第二線寬W32，並且第二線寬W32小於第三金屬線313的第三線寬W33。此外，第一金屬線311的第一線至線間距S31小於第二金屬線312的第二線至線間距S32，並且第二線至線間距S32小於第三金屬線313的第三線至線間距S33。因此，第一金屬化層M1的佈線密度大於上面的金屬化層M2和M3的佈線密度，這將有助於連接在第一金屬化層M1下方按比例縮小的元件(例如，處於10nm、7nm、5nm或3nm技術節點的電晶體)。此外，由於上面的金屬化層M2和M3的線寬W32和W33大於下面的金屬化層M1的線寬W31，所以上面的金屬化層M2和M3有助於降低電路網的電阻。 The first line width W31 of the first metal line 311 is smaller than the second line width W32 of the second metal line 312 , and the second line width W32 is smaller than the third line width W33 of the third metal line 313 . In addition, the first line-to-line spacing S31 of the first metal line 311 is smaller than the second line-to-line spacing S32 of the second metal line 312 , and the second line-to-line spacing S32 is smaller than the third line-to-line spacing of the third metal line 313 S33. Therefore, the wiring density of the first metallization layer M1 is greater than the wiring density of the metallization layers M2 and M3 above, which will facilitate the connection of components scaled down below the first metallization layer M1 (for example, at 10nm, 7nm , 5nm or 3nm technology node transistors). In addition, since the upper metallization layers M2 and M3 have line widths W32 and W33 greater than the line width W31 of the lower metallization layer M1, the upper metallization layers M2 and M3 help reduce the resistance of the circuit net.

在部分實施例中，作為示例而非限制，第一金屬線311的線高(line height)H31(如第3A圖所示，在垂直於X-Y平面的Z方向上測量)小於第二金屬線312的 線高H32，並且第三金屬線313的線高H33與第二金屬線312的線高相同。在部分實施例中，作為示例而非限制，第一金屬線311的線高H31大於通孔321的通孔高度，第二金屬線312的線高H32大於通孔322的通孔高度，並且第三金屬線313的線高H33大於通孔323的通孔高度。 In some embodiments, as an example and not a limitation, the line height (line height) H31 of the first metal line 311 (as shown in FIG. 3A, measured in the Z direction perpendicular to the X-Y plane) is smaller than the second metal line 312 of The line height H32, and the line height H33 of the third metal line 313 is the same as that of the second metal line 312 . In some embodiments, as an example and not limitation, the line height H31 of the first metal line 311 is greater than the through hole height of the through hole 321, the line height H32 of the second metal line 312 is greater than the through hole height of the through hole 322, and the second The line height H33 of the three metal lines 313 is greater than the via hole height of the via hole 323 .

第二組金屬化層模型Group_2包括第四金屬化層M4、在第四金屬化層M4上的第五金屬化層M5和在第五金屬化層M5上的第六金屬化層M6。 The second metallization layer model Group_2 includes a fourth metallization layer M4, a fifth metallization layer M5 on the fourth metallization layer M4, and a sixth metallization layer M6 on the fifth metallization layer M5.

如第3A圖和第3B圖所示，第四金屬化層M4包括水平互連(例如，在第三金屬化層M3上方水平或橫向地延伸的複數個第四金屬線314)，以及垂直互連(例如，在第四金屬線314和第三金屬線313之間垂直地延伸的金屬通孔324)。如此，金屬通孔324提供了第四金屬線314和第三金屬線313之間的電連接。如第3A圖所示，第四金屬線314沿著X方向延伸，並且沿Y方向彼此間隔開。每個第四金屬線314均具有在X方向上測量的第四線寬W34，並且每個第四金屬線314在X方向上與相鄰的第四金屬線314間隔開第四線至線間距S34。 As shown in FIG. 3A and FIG. 3B, the fourth metallization layer M4 includes horizontal interconnections (for example, a plurality of fourth metal lines 314 extending horizontally or laterally above the third metallization layer M3), and vertical interconnections connection (for example, a metal via 324 extending vertically between the fourth metal line 314 and the third metal line 313). As such, the metal via 324 provides an electrical connection between the fourth metal line 314 and the third metal line 313 . As shown in FIG. 3A, the fourth metal lines 314 extend along the X direction and are spaced apart from each other along the Y direction. Each fourth metal line 314 has a fourth line width W34 measured in the X direction, and each fourth metal line 314 is spaced apart from adjacent fourth metal lines 314 by a fourth line-to-line spacing in the X direction S34.

第五金屬化層M5也包括水平互連(例如，在第四金屬化層M4上方水平或橫向地延伸的複數個第五金屬線315)，以及垂直互連(例如，在第五金屬線315和第四金屬線314之間垂直地延伸的金屬通孔325)。因此，金屬通孔325在第五金屬線315和第四金屬線314之間提 供電連接。第五金屬線315沿著X方向延伸並且沿著Y方向彼此間隔開。換句話說，第五金屬線315在垂直於第四金屬線314、第二金屬線312的長度方向並且平行於第三金屬線313、第一金屬線311的長度方向上延伸。每個第五金屬線315均具有在Y方向上測量的第一線寬W35，並且每個第五金屬線315在X方向上與相鄰的第五金屬線315隔開第五線至線間距S35。 The fifth metallization layer M5 also includes horizontal interconnections (eg, a plurality of fifth metal lines 315 extending horizontally or laterally above the fourth metallization layer M4), and vertical interconnections (eg, a plurality of fifth metal lines 315 extending above the fourth metallization layer M4). and the metal via 325 vertically extending between the fourth metal line 314). Therefore, the metal via 325 provides a gap between the fifth metal line 315 and the fourth metal line 314. Power connection. The fifth metal lines 315 extend along the X direction and are spaced apart from each other along the Y direction. In other words, the fifth metal line 315 extends perpendicular to the length direction of the fourth metal line 314 and the second metal line 312 and parallel to the length direction of the third metal line 313 and the first metal line 311 . Each fifth metal line 315 has a first line width W35 measured in the Y direction, and each fifth metal line 315 is separated from adjacent fifth metal lines 315 by a fifth line-to-line spacing in the X direction S35.

第六金屬化層M6也包括水平互連(例如，在第五金屬化層M5上方水平或橫向地延伸的複數個第六金屬線316)，以及垂直互連(例如，在第六金屬線316和第五金屬線315之間垂直地延伸的金屬通孔326)。因此，金屬通孔326在第六金屬線316和第五金屬線315之間提供電連接。第六金屬線316沿著Y方向延伸並且沿著X方向彼此間隔開(如第3A圖所示)。換句話說，第六金屬線316在垂直於第五金屬線315、第三金屬線313、第一金屬線311的長度方向並且平行於第四金屬線314、第二金屬線312的長度方向上延伸。每個第六金屬線316均具有在X方向上測量的第六線寬W36，並且每個第六金屬線316在X方向上與相鄰的第二金屬線312間隔開第六線至線間距S36。 The sixth metallization layer M6 also includes horizontal interconnections (for example, a plurality of sixth metal lines 316 extending horizontally or laterally above the fifth metallization layer M5), and vertical interconnections (for example, a plurality of sixth metal lines 316 extending above the fifth metallization layer M5). and the metal via 326 extending vertically between the fifth metal line 315). Accordingly, the metal via 326 provides an electrical connection between the sixth metal line 316 and the fifth metal line 315 . The sixth metal lines 316 extend along the Y direction and are spaced apart from each other along the X direction (as shown in FIG. 3A ). In other words, the sixth metal line 316 is perpendicular to the length direction of the fifth metal line 315 , the third metal line 313 , and the first metal line 311 and parallel to the length direction of the fourth metal line 314 and the second metal line 312 extend. Each sixth metal line 316 has a sixth line width W36 measured in the X direction, and each sixth metal line 316 is spaced apart from an adjacent second metal line 312 in the X direction by a sixth line-to-line spacing S36.

第四金屬線314的第四線寬W34小於第五金屬線315的第五線寬W35，並且第五線寬W35小於第六金屬線316的第六線寬W36。此外，第四金屬線314的第四線至線間距S34小於第五金屬線315的第五線至線間距 S35，並且第五線至線間距S35小於第六金屬線316的第六線至線間距S36。因此，第四金屬化層M4的佈線密度大於上面的金屬化層M5和M6的佈線密度，從而有助於佈線更多的電路網。此外，由於上面的金屬化層M5和M6的線寬W35和W36大於下面的金屬化層M4的線寬W34，所以上面的金屬化層M5和M6可以有助於降低電路網的電阻。 The fourth line width W34 of the fourth metal line 314 is smaller than the fifth line width W35 of the fifth metal line 315 , and the fifth line width W35 is smaller than the sixth line width W36 of the sixth metal line 316 . In addition, the fourth line-to-line spacing S34 of the fourth metal line 314 is smaller than the fifth line-to-line spacing of the fifth metal line 315 S35 , and the fifth line-to-line spacing S35 is smaller than the sixth line-to-line spacing S36 of the sixth metal line 316 . Therefore, the wiring density of the fourth metallization layer M4 is greater than the wiring density of the upper metallization layers M5 and M6, thereby facilitating wiring of more circuit nets. In addition, since the upper metallization layers M5 and M6 have line widths W35 and W36 greater than the line width W34 of the lower metallization layer M4, the upper metallization layers M5 and M6 can help reduce the resistance of the circuit net.

在部分實施例中，第三金屬線313的第三線寬W33大於在第三金屬線313上方的第四金屬線314的第四線寬W34。因此，第三金屬線313具有比第四金屬線314低的電阻。如此，可以在第三金屬化層M3上佈線較長的電路網(即，較長的導電路徑)，以減小較長的電路網的電阻，並且可以在其他的金屬化層上佈線較短的電路網(即，較短的導電路徑)。 In some embodiments, the third line width W33 of the third metal line 313 is larger than the fourth line width W34 of the fourth metal line 314 above the third metal line 313 . Therefore, the third metal line 313 has a lower resistance than the fourth metal line 314 . In this way, longer circuit nets (ie, longer conductive paths) can be routed on the third metallization layer M3 to reduce the resistance of the longer circuit nets, and shorter circuits can be routed on other metallization layers. network of circuits (ie, shorter conductive paths).

在部分實施例中，作為示例而非限制，第四金屬線314的線高H34(如第6A圖所示，在垂直於X-Y平面的Z方向上測量)小於第五金屬線315的線高H35，並且第六金屬線316的線高H36與第五金屬線315的線高相同。在部分實施例中，作為示例而非限制，第四金屬線314的線高H34大於通孔324的通孔高度，第五金屬線315的線高H35大於通孔325的通孔高度，並且第六金屬線316的線高H36大於通孔326的通孔高度。 In some embodiments, as an example and not a limitation, the line height H34 of the fourth metal line 314 (as shown in FIG. 6A, measured in the Z direction perpendicular to the X-Y plane) is smaller than the line height H35 of the fifth metal line 315 , and the line height H36 of the sixth metal line 316 is the same as that of the fifth metal line 315 . In some embodiments, as an example and not a limitation, the line height H34 of the fourth metal line 314 is greater than the via hole height of the via hole 324, the line height H35 of the fifth metal line 315 is greater than the via hole height of the via hole 325, and The line height H36 of the six metal lines 316 is greater than the via height of the via 326 .

在部分實施例中，第一金屬線311的第一線寬W31和第一線間距S31分別與第四金屬線314的第四線 寬W34和第四線間距S34相同，第二金屬線312的第二線寬W32和第二線間距S32分別與第五金屬線315的第五線寬W35和第五線間距S35相同，並且第三金屬線313的第三線寬W33和第三線間距S33分別與第六金屬線316的第六線寬W36和第六線間距S36相同。作為示例而非限制，金屬線311至316的線寬可以滿足關係式W31=W34<W32=W35<W33=W36，並且金屬線311至316的線至線間距可以滿足關係式S31=S34<S32=S35<S33=S36。此外，金屬線311至316的線高可以滿足關係式H31=H34<H32=H33=H35=H36。 In some embodiments, the first line width W31 and the first line spacing S31 of the first metal line 311 are respectively the same as the fourth line of the fourth metal line 314 The width W34 and the fourth line spacing S34 are the same, the second line width W32 and the second line spacing S32 of the second metal line 312 are respectively the same as the fifth line width W35 and the fifth line spacing S35 of the fifth metal line 315, and the second The third line width W33 and the third line spacing S33 of the third metal line 313 are respectively the same as the sixth line width W36 and sixth line spacing S36 of the sixth metal line 316 . As an example and not limitation, the line width of the metal lines 311 to 316 may satisfy the relationship W31=W34<W32=W35<W33=W36, and the line-to-line spacing of the metal lines 311 to 316 may satisfy the relationship S31=S34<S32 =S35<S33=S36. In addition, the line heights of the metal lines 311 to 316 can satisfy the relationship H31=H34<H32=H33=H35=H36.

第3C圖是根據本公開的部分實施例使用佈局300製造的積體電路結構300A的剖面圖，因此，積體電路結構300A繼承了佈局300中那些圖案的幾何形狀比例(如下面更詳細的描述)。如第1圖所示，可以在製造流程100的步驟122在製造廠中製造積體電路結構300A。積體電路結構300A是用於促進本公開的說明之非限制性示例。 FIG. 3C is a cross-sectional view of an integrated circuit structure 300A fabricated using layout 300 in accordance with some embodiments of the present disclosure. Thus, integrated circuit structure 300A inherits the geometrical proportions of those patterns in layout 300 (as described in more detail below). ). As shown in FIG. 1 , integrated circuit structure 300A may be fabricated in a fab at step 122 of fabrication process 100 . Integrated circuit structure 300A is a non-limiting example used to facilitate the description of the present disclosure.

在部分實施例中，積體電路結構300A可以包括基板301A。基板301A可以包括諸如摻雜或未摻雜的塊狀矽或者絕緣體上半導體(semiconductor-on-insulator,SOI)基板的主動層。通常，絕緣體上半導體基板包括形成在絕緣體層上的半導體材料(例如，矽)層。絕緣體層可以是諸如掩埋氧化物(buried oxide,BOX)層或氧化矽層。絕緣體層設置 在基板(例如，矽或玻璃基板)上。替代地，基板301A可以包括另一種元素半導體(例如，鍺)；化合物半導體(包括，碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和/或銻化銦)；合金半導體(包括，矽鍺(SiGe)、磷砷化鎵(GaAsP)、砷銦化鋁(AlInAs)、砷鎵化鋁(AlGaAs)、砷銦化鎵(GaInAs)、磷銦化鎵(GaInP)和/或磷砷銦化鎵(GaInAsP))；或其組合。也可以使用其他基板(例如，多層或梯度基板)。 In some embodiments, the integrated circuit structure 300A may include a substrate 301A. The substrate 301A may include an active layer such as doped or undoped bulk silicon or a semiconductor-on-insulator (SOI) substrate. Typically, a semiconductor-on-insulator substrate includes a layer of semiconductor material (eg, silicon) formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. Insulator layer settings On a substrate (eg, a silicon or glass substrate). Alternatively, the substrate 301A may include another elemental semiconductor (eg, germanium); a compound semiconductor (including, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide); an alloy semiconductor (including, silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP) and/or or gallium indium arsenide phosphide (GaInAsP)); or a combination thereof. Other substrates (eg, multilayer or gradient substrates) may also be used.

在基板301A上形成一個或複數個主動和/或被動元件302A(在第3C圖中繪示為單個電晶體)。一個或複數個主動和/或被動元件302A可以包括各種N型金屬氧化物半導體(N-type metal-oxide semiconductor,NMOS)和/或P型金屬氧化物半導體(P-type metal-oxide semiconductor,PMOS)元件，例如，電晶體、電容器、電阻器、二極體、光電二極體、保險絲等)。本領域具通常知識者將理解，提供以上示例僅出於說明的目的，並不意味著以任何方式限制本公開。還可以形成適合於給定應用的其他電路。 One or more active and/or passive devices 302A (shown as a single transistor in FIG. 3C ) are formed on the substrate 301A. One or a plurality of active and/or passive elements 302A may include various N-type metal-oxide semiconductors (NMOS) and/or P-type metal-oxide semiconductors (P-type metal-oxide semiconductor, PMOS) ) components such as transistors, capacitors, resistors, diodes, photodiodes, fuses, etc.). Those of ordinary skill in the art will appreciate that the above examples are provided for illustrative purposes only and are not meant to limit the present disclosure in any way. Other circuits may also be formed as appropriate for a given application.

在所繪示的實施例中，元件302A是鰭式場效應電晶體(fin field-effect transistors,FinFET)，此鰭式場效應電晶體是在被稱為鰭片之半導體突起303A的鰭狀條中形成的三維金屬氧化物半導體場效應電晶體結構。第3C圖所示的橫截面是沿著鰭片的長軸在與源極/汲極區域304A之間的電流流動方向平行的方向上截取的。 可以透過使用微影和蝕刻技術對基板301A進行圖案化來形成鰭片303A。例如，可以使用間隔物圖像轉印(spacer image transfer,SIT)圖案化技術。在此方法中，在基板上方形成犧牲層並使用合適的微影和蝕刻製程對其進行圖案化以形成心軸。使用自對準製程在心軸旁邊形成間隔物。然後透過適當的選擇性蝕刻製程去除犧牲層。然後，每個剩餘的間隔物可以作為硬遮罩，以在基板301A中蝕刻溝槽(例如，使用反應性離子蝕刻(reactive ion etching,RIE))來圖案化各個鰭片303A。第3C圖繪示單個鰭片303A，然而，基板301A可以包括任何數量的鰭片。 In the illustrated embodiment, the elements 302A are fin field-effect transistors (FinFETs) formed in fin-shaped strips called fins of semiconductor protrusions 303A. The three-dimensional metal-oxide-semiconductor field-effect transistor structure. The cross-section shown in FIG. 3C is taken along the long axis of the fin in a direction parallel to the direction of current flow between the source/drain regions 304A. Fins 303A may be formed by patterning substrate 301A using lithography and etching techniques. For example, a spacer image transfer (SIT) patterning technique may be used. In this method, a sacrificial layer is formed over a substrate and patterned using suitable lithography and etching processes to form mandrels. Spacers are formed alongside the mandrels using a self-aligned process. The sacrificial layer is then removed by a suitable selective etching process. Each remaining spacer may then serve as a hard mask to etch trenches (eg, using reactive ion etching (RIE)) in the substrate 301A to pattern the individual fins 303A. FIG. 3C depicts a single fin 303A, however, the substrate 301A may include any number of fins.

在第3C圖中繪示圍繞鰭片303A的下部形成的淺溝槽隔離(shallow trench isolation,STI)區域305A。可以透過沉積一種或多種介電材料(例如，氧化矽)以完全地填充鰭片周圍的溝槽，接著使介電材料的頂表面下陷來形成淺溝槽隔離區域305A。淺溝槽隔離區域305A之介電材料的沉積可以使用高密度電漿化學氣相沉積(high density plasma chemical vapor deposition,HDP-CVD)、低壓化學氣相沉積(low-pressure chemical vapor deposition,LPCVD)、次大氣壓化學氣相沉積(sub-atmospheric chemical vapor deposition,SACVD)、可流動化學氣相沉積(flowable chemical vapor deposition,FCVD)、旋轉塗佈和/或類似的製程或其組合。在沉積之後，可以執行退火製程 或固化製程。在一些情況下，淺溝槽隔離區域305A可以包括襯墊(例如，透過氧化矽表面而生長的熱氧化物襯墊)。下陷製程可以使用例如平坦化製程(例如，化學機械平坦化(chemical mechanical polish,CMP))，隨後可以使用選擇性蝕刻製程(例如，濕式蝕刻、乾式蝕刻或其組合)以使淺溝槽隔離區域305A中的介電材料的頂表面凹陷，使得鰭片303A的上部從周圍的絕緣淺溝槽隔離區域305A突出。在部份情況下，也可以透過平坦化製程去除用於形成鰭片303A之圖案化的硬遮罩。 A shallow trench isolation (STI) region 305A formed around the lower portion of the fin 303A is shown in FIG. 3C. The shallow trench isolation region 305A may be formed by depositing one or more dielectric materials (eg, silicon oxide) to completely fill the trenches around the fins, followed by recessing the top surface of the dielectric material. The deposition of the dielectric material in the shallow trench isolation region 305A can use high density plasma chemical vapor deposition (high density plasma chemical vapor deposition, HDP-CVD), low pressure chemical vapor deposition (low-pressure chemical vapor deposition, LPCVD) , sub-atmospheric chemical vapor deposition (SACVD), flowable chemical vapor deposition (flowable chemical vapor deposition, FCVD), spin coating and/or similar processes or combinations thereof. After deposition, an annealing process can be performed or curing process. In some cases, STI region 305A may include a liner (eg, a thermal oxide liner grown through a silicon oxide surface). The undercut process may use, for example, a planarization process (eg, chemical mechanical polish (CMP)), followed by a selective etch process (eg, wet etch, dry etch, or a combination thereof) to isolate the shallow trenches. The top surface of the dielectric material in region 305A is recessed such that the upper portion of fin 303A protrudes from the surrounding insulating shallow trench isolation region 305A. In some cases, the patterned hard mask used to form the fin 303A may also be removed through a planarization process.

在部分實施例中，第3C圖所示的鰭式場效應電晶體元件302A的閘極結構306A可以是使用後閘極製程(gate-last process)流程形成的高介電常數金屬閘極(high-k metal gate,HKMG)閘極結構。在後閘極製程流程中，在形成淺溝槽隔離區域305A之後形成犧牲虛設閘極結構(未繪示)。虛設閘極結構可以包括虛設閘極介電質、虛設閘極和硬遮罩。首先，可以沉積虛設閘極介電材料(例如，氧化矽、氮化矽等)。接下來，可以在虛設閘極介電質上沉積虛設閘極材料(例如，非晶矽、多晶矽等)，然後使其平坦化(例如，透過化學機械平坦化)。可以在虛設閘極材料上形成硬遮罩層(例如，氮化矽、碳化矽等)。然後，可透過對硬遮罩進行圖案化，並使用適當的微影和蝕刻技術將此圖案轉移到虛設閘極介電質和虛設閘極材料上，來形成虛設閘極結構。虛設閘極結構可以沿著突出鰭片的複數個側面延伸，並且在淺溝槽隔離區域 305A的表面上方的鰭片之間延伸。如以下更詳細地描述的，虛設閘極結構可以由如第3C圖所示的高介電常數金屬閘極閘極結構306A代替。可以使用任何合適的方法(例如，化學氣相沉積、電漿增強化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)、原子層沉積(atomic layer deposition,ALD)、電漿增強原子層沉積(plasma-enhanced atomic layer deposition,PEALD)等，或透過半導體表面的熱氧化或其組合)來沉積用於形成虛設閘極結構和硬遮罩的材料。 In some embodiments, the gate structure 306A of the FinFET device 302A shown in FIG. 3C may be a high-k metal gate (high- k metal gate, HKMG) gate structure. In the gate-last process flow, a sacrificial dummy gate structure (not shown) is formed after the STI region 305A is formed. The dummy gate structure may include a dummy gate dielectric, a dummy gate, and a hard mask. First, a dummy gate dielectric material (eg, silicon oxide, silicon nitride, etc.) can be deposited. Next, a dummy gate material (eg, amorphous silicon, polysilicon, etc.) may be deposited on the dummy gate dielectric, which is then planarized (eg, by chemical mechanical planarization). A hard mask layer (eg, silicon nitride, silicon carbide, etc.) may be formed on the dummy gate material. Dummy gate structures can then be formed by patterning the hard mask and transferring this pattern onto the dummy gate dielectric and dummy gate material using appropriate lithography and etching techniques. The dummy gate structure can extend along multiple sides of the protruding fin and in the shallow trench isolation region 305A extends between the fins above the surface. As described in more detail below, the dummy gate structure may be replaced by a high-k metal gate structure 306A as shown in FIG. 3C. Any suitable method can be used (for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition (plasma-enhanced chemical vapor deposition, PECVD), atomic layer deposition (atomic layer deposition, ALD), plasma-enhanced atomic layer deposition ( plasma-enhanced atomic layer deposition (PEALD), etc., or through thermal oxidation of the semiconductor surface, or a combination thereof) to deposit materials for forming dummy gate structures and hard masks.

如第3C圖所示，使鰭式場效應電晶體302A的源極/汲極區域304A和間隔物307A形成為例如與虛設閘極結構自對準。可以在虛設閘極圖案化完成之後進行間隔物介電層的沉積和各向異性蝕刻以形成間隔物307A。間隔物介電層可以包括一種或多種介電質(例如，氧化矽、氮化矽、氮氧化矽、碳化矽、碳氮化矽等或其組合)。各向異性蝕刻製程從虛設閘極結構的頂部上方去除間隔物介電層，從而留下沿著虛設閘極結構的側壁橫向地延伸到鰭片303A之部分表面的間隔物307A。 As shown in FIG. 3C, the source/drain regions 304A and spacers 307A of the FinFET 302A are formed, eg, self-aligned with the dummy gate structure. Deposition of a spacer dielectric layer and anisotropic etching to form spacers 307A may be performed after dummy gate patterning is complete. The spacer dielectric layer may include one or more dielectrics (eg, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, etc., or combinations thereof). The anisotropic etch process removes the spacer dielectric layer from over the top of the dummy gate structure, leaving spacers 307A extending laterally along the sidewalls of the dummy gate structure to a portion of the surface of fin 303A.

源極/汲極區域304A是與半導體鰭片303A直接接觸的半導體區域。在部分實施例中，源極/汲極區域304A可以包括高度摻雜的區域和相對輕度摻雜的汲極(lightly-doped drain,LDD)延伸區域。通常，使用間隔物307A將高度摻雜的區域與虛設閘極結構間隔開， 而輕度摻雜的汲極區域可以在形成間隔物307A之前形成，因此會在間隔物307A下方延伸，並且在部分實施例中，進一步延伸至虛設閘極結構下方之半導體鰭片303A的一部分。可以透過諸如離子佈植製程佈植摻雜劑(例如，砷(As)、磷(P)、硼(B)、銦(In)等)來形成輕度摻雜的汲極區域。 The source/drain regions 304A are semiconductor regions that are in direct contact with the semiconductor fins 303A. In some embodiments, the source/drain region 304A may include a highly doped region and a relatively lightly-doped drain (LDD) extension region. Typically, spacers 307A are used to separate the highly doped regions from the dummy gate structures, The lightly doped drain region may be formed before the spacer 307A and thus extends under the spacer 307A and, in some embodiments, further extends to a portion of the semiconductor fin 303A below the dummy gate structure. The lightly doped drain region can be formed by implanting dopants (eg, arsenic (As), phosphorus (P), boron (B), indium (In), etc.) by a process such as ion implantation.

源極/汲極區域304A可以包括磊晶生長的區域。例如，在形成輕度摻雜的汲極區域之後，可以形成間隔物307A，隨後，可以透過先蝕刻鰭片303A以形成凹槽，然後，透過選擇性磊晶生長(selective epitaxial growth,SEG)製程在凹槽中沉積晶體半導體材料來形成與間隔物307A自對準之高度摻雜的源極和汲極區域(其中選擇性磊晶生長製成可以填充凹槽並且可以進一步延伸超過鰭片303A的原始表面以形成凸起的源極/汲極磊晶結構)。晶體半導體材料可以是元素的(例如，矽(Si)或鍺(Ge)等)，或者是合金的(例如，矽碳(Si1-xCx)或矽鍺(Si1-xGex)等)。選擇性磊晶生長製程可以使用任何合適的磊晶生長方法(例如，氣相磊晶/固相磊晶/液相磊晶或金屬有機化學氣相沉積或分子束磊晶等)。可在選擇性磊晶生長期間原位或在選擇性磊晶生長之後執行離子佈植製程(或其組合)，將高劑量(例如，約1014cm-2至1016cm-2)的摻雜劑引入到高度摻雜的源極/汲極區域304A中。 The source/drain regions 304A may include epitaxially grown regions. For example, after forming the lightly doped drain region, the spacer 307A can be formed, and then, the groove can be formed by first etching the fin 303A, and then, through a selective epitaxial growth (SEG) process Crystalline semiconductor material is deposited in the grooves to form highly doped source and drain regions self-aligned with the spacers 307A (wherein selective epitaxial growth is made to fill the grooves and extend further beyond the fins 303A). pristine surface to form a raised source/drain epitaxial structure). Crystalline semiconductor materials can be elemental (for example, silicon (Si) or germanium (Ge), etc.), or alloyed (for example, silicon carbon (Si 1-x C x ) or silicon germanium (Si 1-x Ge x ) Wait). The selective epitaxial growth process can use any suitable epitaxial growth method (for example, vapor phase epitaxy/solid phase epitaxy/liquid phase epitaxy or metal organic chemical vapor deposition or molecular beam epitaxy, etc.). The ion implantation process (or a combination thereof) can be performed in situ during selective epitaxial growth or after selective epitaxial growth, and high doses (eg, about 10 14 cm −2 to 10 16 cm −2 ) of doped Dopants are introduced into the highly doped source/drain regions 304A.

一旦形成源極/汲極區域304A，就在源極/汲極區 域304A上沉積第一層間介電層(例如，層間介電層341A的下部)。在部分實施例中，可以在沉積層間介電材料之前沉積合適的介電質(例如，氮化矽、碳化矽等或其組合)的接觸蝕刻停止層(contact etch stop layer,CESL)(未繪示)。可以執行平坦化製程(例如，化學機械平坦化)以從虛設閘極上方去除過量的層間介電材料和任何剩餘的硬遮罩材料以形成一頂表面，其中，虛設閘極材料的此頂表面被暴露並且可以與第一層間介電層的頂表面實質上共平面。接著，可形成如第3C圖所示的高介電常數金屬閘極閘極結構306A。高介電常數金屬閘極閘極結構306A的形成步驟包括先使用一種或多種蝕刻技術去除虛設閘極結構，從而在各個間隔物307A之間形成溝槽。接下來，沉積包括一種或多種介電質的替代閘極介電層GD，隨後沉積包括一種或多種金屬的替代閘極金屬層GM以完全地填充溝槽。可以使用諸如化學機械平坦化製程從第一層間介電質的頂表面上方去除閘極結構層的多餘部分。所得到的結構(如第3C圖所示)可以包括嵌入在相應的間隔物307A之間之高介電常數金屬閘極閘極層GD和GM的剩餘部分。 Once the source/drain region 304A is formed, the source/drain region A first ILD layer (eg, the lower portion of ILD layer 341A) is deposited over region 304A. In some embodiments, a contact etch stop layer (CESL) (not shown) of a suitable dielectric (eg, silicon nitride, silicon carbide, etc., or a combination thereof) may be deposited prior to depositing the interlayer dielectric material. Show). A planarization process (eg, chemical mechanical planarization) may be performed to remove excess ILD material and any remaining hard mask material from above the dummy gate to form a top surface, wherein the top surface of the dummy gate material is exposed and may be substantially coplanar with the top surface of the first interlayer dielectric layer. Next, a high-k metal gate structure 306A as shown in FIG. 3C may be formed. The step of forming the high-k metal gate structure 306A includes first removing the dummy gate structure using one or more etching techniques to form trenches between the respective spacers 307A. Next, a replacement gate dielectric layer GD comprising one or more dielectrics is deposited, followed by a replacement gate metal layer GM comprising one or more metals to completely fill the trenches. Excess portions of the gate structure layer may be removed from above the top surface of the first ILD using a process such as chemical mechanical planarization. The resulting structure (shown in FIG. 3C ) may include the remainder of the high-k metal gate layers GD and GM embedded between respective spacers 307A.

閘極介電層GD包括諸如高介電常數介電材(例如，金屬的氧化物和/或金屬的矽酸鹽(例如，鉿(Hf)、鋁(Al)、鋯(Zr)、鑭(La)、鎂(Mg)、鋇(Ba)、鈦(Ti)和其他金屬的氧化物和/或矽酸鹽)、氮化矽、氧化矽等、或其組合或其多層)。在部分實施例中，閘極金屬層GM 可以是多層金屬閘極疊層，其包括依次地形成在閘極介電層GD之上的阻障層、功函數層和閘極填充層。阻障層的示例材料包括氮化鈦(TiN)、氮化鉭(TaN)、鈦(Ti)、鉭(Ta)等或它們的多層組合。對於p型場效應電晶體，功函數層可以包括氮化鈦(TiN)、氮化鉭(TaN)、釕(Ru)、鉬(Mo)、鋁(Al)；對於n型場效應電晶體，功函數層可以包括鈦(Ti)、銀(Ag)、鋁化鉭(TaAl)、碳鋁化鉭(TaAlC)、氮鋁化鈦(TiAlN)、碳化鉭(TaC)、氮碳化鉭(TaCN)、氮矽化鉭(TaSiN)、錳(Mn)、鋯(Zr)。可以使用其他合適的功函數材料或其組合或其多層。填充溝槽的其餘部分的閘極填充層可以包括諸如銅(Cu)、鋁(Al)、鎢(W)、鈷(Co)、釕(Ru)等的金屬或者其組合或者其多層。可以透過任何合適的方法(例如，化學氣相沉積、電漿增強化學氣相沉積、物理氣相沉積、原子層沉積、電漿增強原子層沉積、電化學電鍍(electrochemical plating,ECP)、無電鍍(electroless plating)和/或類似的方法)來沉積形成閘極結構的材料。 The gate dielectric layer GD includes such as high dielectric constant dielectric material (for example, metal oxide and/or metal silicate (for example, hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum ( La), magnesium (Mg), barium (Ba), titanium (Ti) and other metal oxides and/or silicates), silicon nitride, silicon oxide, etc., or combinations or multilayers thereof). In some embodiments, the gate metal layer GM There may be a multi-layer metal gate stack including a barrier layer, a work function layer and a gate fill layer sequentially formed over the gate dielectric layer GD. Exemplary materials for the barrier layer include titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), tantalum (Ta), etc., or multilayer combinations thereof. For p-type field effect transistors, the work function layer may include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al); for n-type field effect transistors, The work function layer can include titanium (Ti), silver (Ag), tantalum aluminide (TaAl), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbide nitride (TaCN) , tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr). Other suitable work function materials or combinations or layers thereof may be used. The gate fill layer filling the remainder of the trench may include a metal such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), etc., or a combination or multiple layers thereof. Can be by any suitable method (for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma enhanced atomic layer deposition, electrochemical plating (electrochemical plating, ECP), electroless plating (electroless plating) and/or similar methods) to deposit the material that forms the gate structure.

在形成高介電常數金屬閘極結構306A之後，在第一層間介電層上方沉積第二層間介電層，並且將第一層間介電層和第二層間介電層一起稱為層間介電層341A(如第3C圖所示)。在部分實施例中，形成第一層間介電層和第二層間介電層的絕緣材料可包括氧化矽、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼矽酸鹽玻璃 (borosilicate glass,BSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass,BPSG)、未摻雜的矽酸鹽玻璃(undoped silicate glass,USG)、低介電常數介電質(例如，氟矽酸鹽玻璃(fluorosilicate glass,FSG)、碳氧化矽(silicon oxycarbide,SiOCH)、碳摻雜的氧化物(carbon-doped oxide,CDO)、可流動的氧化物或多孔的氧化物(例如，乾凝膠/氣凝膠)等或它們的組合)。可以使用任何合適的方法(例如，化學氣相沉積、物理氣相沉積(physical vapor deposition,PVD)、原子層沉積、電漿增強原子層沉積、電漿增強化學氣相沉積、次大氣壓化學氣相沉積、可流動化學氣相沉積、旋轉塗佈等或其組合)來沉積用於形成第一層間介電層和第二層間介電層的介電材料。 After forming the high-k metal gate structure 306A, a second interlayer dielectric layer is deposited over the first interlayer dielectric layer, and the first interlayer dielectric layer and the second interlayer dielectric layer are collectively referred to as an interlayer dielectric layer. Dielectric layer 341A (shown in FIG. 3C). In some embodiments, the insulating material forming the first interlayer dielectric layer and the second interlayer dielectric layer may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (borosilicate glass, BSG), borophosphosilicate glass (BPSG), undoped silicate glass (undoped silicate glass, USG), low dielectric constant dielectric (for example, fluorosilicate Glass (fluorosilicate glass, FSG), silicon oxycarbide (SiOCH), carbon-doped oxide (carbon-doped oxide, CDO), flowable oxide or porous oxide (for example, xerogel/ aerogels), etc. or a combination thereof). Any suitable method (e.g., chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, sub-atmospheric chemical vapor deposition) can be used. deposition, flowable chemical vapor deposition, spin coating, etc., or combinations thereof) to deposit the dielectric material used to form the first interlayer dielectric layer and the second interlayer dielectric layer.

接觸件308A分別地形成在鰭式場效應電晶體302A的閘極結構306A和源極/汲極區域304A上方。可以使用微影、蝕刻和沈積技術來形成接觸件308A。例如，圖案化的遮罩可以形成在層間介電層341A上方，並且可以使用此圖案化的遮罩蝕刻延伸穿過層間介電層341A以暴露閘極結構306A和源極/汲極區域304A的開口。之後，可以在層間介電層341A中的開口中形成導電襯墊。隨後，用導電填充材料填充此開口。襯墊包括阻障金屬，此阻障金屬用於減少導電材料從接觸件308A向外擴散到周圍的介電材料中。在部分實施例中，襯墊可包括兩個阻障金屬層。第一阻障金屬與源極/汲極區域304A中的半導體材料 接觸，並且隨後可以與源極/汲極區域304A中高度摻雜的半導體產生化學反應以形成低電阻歐姆接觸，此後可去除未反應的金屬。例如，如果源極/汲極區域304A中高度摻雜的半導體是矽或矽鍺合金半導體，則第一阻障金屬可以包括鈦(Ti)、鎳(Ni)、鉑(Pt)、鈷(Co)、其他合適的金屬或其合金。導電襯墊的第二阻障金屬層可以另外地包括其他金屬(例如，氮化鈦(TiN)、氮化鉭(TaN)、鉭(Ta)或其他合適的金屬或其合金)。可以使用任何可接受的沉積技術(例如，化學氣相沉積、原子層沉積、電漿增強原子層沉積、電漿增強化學氣相沉積、物理氣相沉積、電化學電鍍、無電鍍等或其任何組合)，將導電填充材料(例如，鎢(W)、鋁(Al)、鈷(Cu)、釕(Ru)、鎳(Ni)、鈷(Co)、它們的合金或其組合等)沉積在導電襯層上以填充接觸開口。接下來，可以使用平坦化製程(例如，化學機械平坦化)以從層間介電層341A的表面上方去除所有導電材料的多餘部分。所得的導電插塞延伸到層間介電層341A中並構成接觸件308A，從而形成到電子元件(例如，第3C圖所示的三閘極鰭式場效應電晶體302A)的電極的物理和電連接。在部分實施例中，繪示為垂直連接器的源極/汲極接觸件308A可以延伸以形成橫向地傳輸電流的導線。 Contacts 308A are formed over gate structure 306A and source/drain regions 304A of FinFET 302A, respectively. Contacts 308A may be formed using lithography, etching and deposition techniques. For example, a patterned mask may be formed over interlayer dielectric layer 341A, and the patterned mask extending through interlayer dielectric layer 341A may be used to etch to expose gate structures 306A and source/drain regions 304A. Open your mouth. Thereafter, a conductive pad may be formed in the opening in the interlayer dielectric layer 341A. Subsequently, this opening is filled with a conductive filling material. The liner includes a barrier metal that is used to reduce the out-diffusion of conductive material from the contact 308A into the surrounding dielectric material. In some embodiments, the liner may include two barrier metal layers. The first barrier metal and the semiconductor material in the source/drain region 304A contact, and may subsequently chemically react with the highly doped semiconductor in the source/drain region 304A to form a low resistance ohmic contact, after which unreacted metal may be removed. For example, if the highly doped semiconductor in the source/drain region 304A is silicon or a silicon-germanium alloy semiconductor, the first barrier metal may include titanium (Ti), nickel (Ni), platinum (Pt), cobalt (Co ), other suitable metals or alloys thereof. The second barrier metal layer of the conductive liner may additionally include other metals (eg, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), or other suitable metals or alloys thereof). Any acceptable deposition technique (e.g., chemical vapor deposition, atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, electrochemical plating, electroless plating, etc., or any Combination), the conductive filling material (for example, tungsten (W), aluminum (Al), cobalt (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), their alloys or combinations thereof, etc.) is deposited on the conductive liner to fill the contact openings. Next, a planarization process (eg, chemical mechanical planarization) may be used to remove all excess portions of conductive material from above the surface of the interlayer dielectric layer 341A. The resulting conductive plug extends into the interlayer dielectric layer 341A and constitutes a contact 308A, thereby forming a physical and electrical connection to an electrode of an electronic component (eg, a tri-gate FinFET 302A shown in FIG. 3C ). . In some embodiments, the source/drain contacts 308A, shown as vertical connectors, may extend to form conductive lines that carry current laterally.

在形成接觸件308A之後，可以根據積體電路設計所採用的後端(back-end-of-line,BEOL)方案，在層間介電層341A上方垂直堆疊地形成包括複數個互連 層的互連結構330A。互連結構330A使一個或多個主動和/或被動元件302A電連接，以在積體電路結構300A內形成功能性電路。互連結構330A可以包括金屬化層M1A至M6A，這些金屬化層M1A至M6A使用佈局300的金屬化層M1至M6(如第3A圖和3B所示)的佈局圖案製造，因此，金屬化層M1A至M6A繼承了佈局300的佈局圖案的幾何形狀比例(如下面更詳細描述的)。 After the contact 308A is formed, according to the back-end-of-line (BEOL) scheme adopted by the integrated circuit design, a plurality of interconnections including a plurality of interconnections can be vertically stacked on the interlayer dielectric layer 341A. layer interconnect structure 330A. Interconnect structure 330A electrically connects one or more active and/or passive components 302A to form a functional circuit within integrated circuit structure 300A. Interconnect structure 330A may include metallization layers M1A to M6A fabricated using the layout pattern of metallization layers M1 to M6 of layout 300 (shown in FIGS. 3A and 3B ), thus, the metallization layers M1A through M6A inherit the geometrical proportions of the layout pattern of layout 300 (as described in more detail below).

金屬化層M1A至M6A分別地包括金屬間介電(inter-metal dielectric,IMD)層351A至356A和金屬間介電層361A至366A。金屬間介電層361A至366A形成在相應的金屬間介電層351A至356A之上。金屬化層M1A至M6A包括水平互連(例如，分別在金屬間介電層361A至366A中水平或橫向地延伸的金屬線311A至316A)，以及垂直互連(例如，分別在金屬間介電層351A至356A中垂直地延伸的金屬通孔321A至326A)。可將金屬化層M1A至M6A的形成稱為後端製程。 The metallization layers M1A to M6A respectively include inter-metal dielectric (IMD) layers 351A to 356A and inter-metal dielectric layers 361A to 366A. The intermetal dielectric layers 361A to 366A are formed over the corresponding intermetal dielectric layers 351A to 356A. Metallization layers M1A to M6A include horizontal interconnects (eg, metal lines 311A to 316A extending horizontally or laterally in IMD layers 361A to 366A, respectively), and vertical interconnects (eg, metal lines 311A to 316A in IMD layers 361A to 366A, respectively). vertically extending metal vias 321A-326A in layers 351A-356A). The formation of the metallization layers M1A to M6A may be referred to as a back-end process.

金屬化層M1A至M6A可以使用任何合適的方法(例如，單鑲嵌製程、雙鑲嵌製程等)形成。作為示例而非限制，金屬化層M1A的製造包括在層間介電層341A上方形成金屬間介電層351A，使用在佈局300中具有通孔321的佈局圖案的光罩對金屬間介電層351A進行圖案化以在金屬間介電層351A中形成通孔開口，在通孔開口中沉積一種或多種金屬，平坦化(例如，使用化學機械平 坦化)一種或多種金屬直到到達金屬間介電層351A的頂表面，以在通孔開口中留下金屬通孔321A，在金屬通孔321A上方形成金屬間介電層361A，使用在佈局300中具有金屬線311的佈局圖案的另一光罩對金屬間介電層361A進行圖案化以在金屬間介電層361A中形成溝槽，將一種或多種金屬沉積到金屬間介電層361A中的溝槽中，然後，平坦化(例如，使用化學機械平坦化)一種或多種金屬直到到達金屬間介電層361A的頂表面為止，以將金屬線311A留在金屬間介電層361A中的溝槽中。其他金屬化層M2A至M6A的製造類似於金屬化層M1A的製造，因此，為了簡潔起見不重複。 Metallization layers M1A to M6A may be formed using any suitable method (eg, single damascene process, dual damascene process, etc.). By way of example and not limitation, fabrication of metallization layer M1A includes forming IMD layer 351A over ILD layer 341A using a photomask having a layout pattern of vias 321 in layout 300 for IMD layer 351A. Patterning is performed to form via openings in IMD layer 351A, one or more metals are deposited in the via openings, planarization (e.g., using chemical mechanical planarization) Tanning) one or more metals until reaching the top surface of IMD layer 351A to leave metal via 321A in the via opening, forming IMD layer 361A over metal via 321A, used in layout 300 Another photomask with the layout pattern of the metal lines 311 in the IMD layer 361A is patterned to form trenches in the IMD layer 361A, and one or more metals are deposited into the IMD layer 361A Then, planarize (for example, using chemical mechanical planarization) one or more metals until reaching the top surface of the intermetal dielectric layer 361A, so as to leave the metal line 311A in the intermetal dielectric layer 361A in the trench. The production of the other metallization layers M2A to M6A is similar to the production of the metallization layer M1A and is therefore not repeated for the sake of brevity.

在部分實施例中，層間介電層341A和金屬間介電層351A至356A、361A至366A可以包括設置在這些金屬特徵之間具有低介電常數(例如，介電常數小於約4.0或甚至小於2.0)的介電材料。在部分實施例中，層間介電層和金屬間介電層可以由諸如磷矽酸鹽玻璃、硼磷矽酸鹽玻璃、氟矽酸鹽玻璃、碳氧化矽(SiOxCy)、旋轉塗佈玻璃、旋轉塗佈聚合物、氧化矽、氮氧化矽和它們的組合等製成，並且其可透過任何合適的方法(例如，旋轉塗佈、化學氣相沉積、電漿增強化學氣相沉積等)形成。金屬線311A至316A和金屬通孔321A至326A可以包括導電材料(例如，銅、鋁、鎢和其組合等)。在部分實施例中，金屬線311A至316A和金屬通孔321A至326A可以進一步包括一個或複數個阻障層/黏合層(未繪示)以 保護相應的金屬間介電層351A至356A和361A至366A免受金屬擴散(例如，銅擴散)和金屬毒化(metallic poisoning)的影響。一個或複數個阻障層/黏合層可以包括鈦、氮化鈦、鉭、氮化鉭等，並且可以使用物理氣相沉積、化學氣相沉積、原子層沉積等形成。儘管第3C圖所示的金屬線311A至316A和金屬通孔321A至326A具有垂直的側壁，然而，它們也可以具有錐形的側壁(如第3C圖中的金屬線311A和金屬通孔321A中的虛線所示)。這是因為在金屬間介電層351A至356A和361A至366A中形成通孔開口和溝槽的蝕刻製程可能會導致在通孔開口和溝槽中的錐形側壁。 In some embodiments, the interlayer dielectric layer 341A and the intermetal dielectric layers 351A to 356A, 361A to 366A may include metals having a low dielectric constant (eg, a dielectric constant of less than about 4.0 or even less than 2.0) Dielectric material. In some embodiments, the interlayer dielectric layer and the intermetal dielectric layer can be made of such as phosphosilicate glass, borophosphosilicate glass, fluorosilicate glass, silicon oxycarbide (SiO x Cy ), spin-coated Fabric glass, spin-on polymer, silicon oxide, silicon oxynitride, and combinations thereof, etc., and it can be made by any suitable method (for example, spin-coating, chemical vapor deposition, plasma-enhanced chemical vapor deposition etc.) formed. Metal lines 311A to 316A and metal vias 321A to 326A may include a conductive material (eg, copper, aluminum, tungsten, combinations thereof, etc.). In some embodiments, the metal lines 311A to 316A and the metal vias 321A to 326A may further include one or more barrier layers/adhesion layers (not shown) to protect the corresponding IMD layers 351A to 356A and 361A. Up to 366A is immune to metal diffusion (eg, copper diffusion) and metal poisoning. The barrier/adhesion layer or layers may include titanium, titanium nitride, tantalum, tantalum nitride, etc., and may be formed using physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like. Although metal lines 311A to 316A and metal vias 321A to 326A shown in FIG. 3C have vertical sidewalls, they may also have tapered sidewalls (as in metal line 311A and metal via 321A in FIG. 3C ). shown by the dotted line). This is because the etch process that forms the via openings and trenches in the IMD layers 351A-356A and 361A-366A may result in tapered sidewalls in the via openings and trenches.

金屬線311A至316A和金屬通孔321A至326A具有與佈局300中相應的金屬線311至316和金屬通孔321至326相同的幾何形狀比例。更詳細地，金屬線311A、313A和315A沿第一方向(例如，如第3A圖的立體圖所示的X方向)延伸並且沿第二方向(例如，如第3A圖的立體圖所示的Y方向)彼此間隔開。金屬線312A、314A和316A沿著第二方向(如第3A圖所示的Y方向)延伸並且沿著第一方向(如第3A圖所示的X方向)彼此間隔開。因此，金屬線311A、313A和315A的長度方向垂直於金屬線312A、314A和316A的長度方向。 Metal lines 311A to 316A and metal vias 321A to 326A have the same geometrical proportions as corresponding metal lines 311 to 316 and metal vias 321 to 326 in layout 300 . In more detail, the metal lines 311A, 313A, and 315A extend along a first direction (for example, the X direction as shown in the perspective view of FIG. 3A ) and extend along a second direction (for example, the Y direction as shown in the perspective view of FIG. 3A ). ) are spaced apart from each other. The metal lines 312A, 314A, and 316A extend along a second direction (Y direction as shown in FIG. 3A ) and are spaced apart from each other along a first direction (X direction as shown in FIG. 3A ). Therefore, the length direction of the metal lines 311A, 313A, and 315A is perpendicular to the length direction of the metal lines 312A, 314A, and 316A.

如第3A圖所示，金屬線311A、313A、315A具有在Y方向上測量之相應的線寬W31、W33、W35， 並且在Y方向上以相應的線至線間距S31、S33、S35配置。如第3A圖所示，金屬線312A、314A、316A具有在X方向上測量之相應的線寬W32、W34、W36，並且在X方向上以相應的線至線間距S32、S34、S36配置。 As shown in FIG. 3A, metal lines 311A, 313A, 315A have corresponding line widths W31, W33, W35 measured in the Y direction, And arranged in the Y direction with corresponding line-to-line spacings S31 , S33 , S35 . As shown in FIG. 3A, metal lines 312A, 314A, 316A have respective line widths W32, W34, W36 measured in the X direction and are arranged at respective line-to-line spacings S32, S34, S36 in the X direction.

金屬線311A的線寬W31小於金屬線312A的線寬W32，並且線寬W32小於金屬線313A的線寬W33。此外，金屬線311A的線至線間距S31小於金屬線312A的線至線間距S32，並且線至線間距S32小於金屬線313A的線至線間距S33。因此，下面的金屬化層M1A的佈線密度大於上面的金屬化層M2A和M3A的佈線密度，這將有助於連接在金屬化層M1A下方的鰭式場效應電晶體302A。此外，由於上面的金屬化層M2A和M3A的線寬W32和W33大於下面的金屬化層M1A的線寬W31，所以上面的金屬化層M2A和M3A有助於降低電路網的電阻。 The line width W31 of the metal line 311A is smaller than the line width W32 of the metal line 312A, and the line width W32 is smaller than the line width W33 of the metal line 313A. In addition, the line-to-line spacing S31 of the metal line 311A is smaller than the line-to-line spacing S32 of the metal line 312A, and the line-to-line spacing S32 is smaller than the line-to-line spacing S33 of the metal line 313A. Therefore, the wiring density of the lower metallization layer M1A is greater than the wiring density of the upper metallization layers M2A and M3A, which will facilitate the connection of the FinFET 302A below the metallization layer M1A. In addition, since the upper metallization layers M2A and M3A have line widths W32 and W33 greater than the line width W31 of the lower metallization layer M1A, the upper metallization layers M2A and M3A help reduce the resistance of the circuit net.

此外，金屬線312A、313A的線寬W32、W33大於在金屬線313A上方延伸的金屬線314A的線寬W34。因此，金屬線312A、313A具有比金屬線314A低的電阻。如此，可以在金屬化層M3A和/或金屬化層M2A上佈線較長的電路網(即，較長的導電路徑)以減小較長的電路網的電阻，並且可以在金屬化層M4A上佈線較短的電路網(即，較短的導電路徑)。 Furthermore, the line widths W32 , W33 of the metal lines 312A, 313A are larger than the line width W34 of the metal line 314A extending above the metal line 313A. Therefore, the metal lines 312A, 313A have a lower resistance than the metal line 314A. In this way, longer circuit nets (ie, longer conductive paths) can be wired on the metallization layer M3A and/or metallization layer M2A to reduce the resistance of the longer circuit nets, and can be routed on the metallization layer M4A Route shorter nets (ie, shorter conductive paths).

此外，金屬線315A的線寬W35大於金屬線314A的線寬W34，並且金屬線316A的線寬W36大於 線寬W35。此外，金屬線314A的線至線間距S34小於金屬線315A的線至線間距S35、金屬線316A的線至線間距S36、金屬線313A的線至線間距S33和金屬線312A的線至線間距S32。因此，金屬化層M4A的佈線密度大於上面的金屬化層M5A和M6A以及下面的金屬化層M3A和M2A的佈線密度，這將有助於在金屬化層M4A上佈線比在金屬化層M2A、M3A、M5A和M6A上更多的電路網。此外，由於上面的金屬化層M5A和M6A的線寬W35、W36大於下面的金屬化層M4A的線寬W34，所以上面的金屬化層M5A和M6A可以有助於降低電路網的電阻。 In addition, the line width W35 of the metal line 315A is greater than the line width W34 of the metal line 314A, and the line width W36 of the metal line 316A is greater than Line width W35. In addition, the line-to-line spacing S34 of the metal line 314A is smaller than the line-to-line spacing S35 of the metal line 315A, the line-to-line spacing S36 of the metal line 316A, the line-to-line spacing S33 of the metal line 313A, and the line-to-line spacing of the metal line 312A. S32. Therefore, the wiring density of the metallization layer M4A is greater than the wiring density of the upper metallization layers M5A and M6A and the lower metallization layers M3A and M2A, which will help the wiring density on the metallization layer M4A to be higher than that on the metallization layers M2A, M2A, and M2A. More circuit nets on M3A, M5A and M6A. In addition, since the upper metallization layers M5A and M6A have line widths W35, W36 greater than the line width W34 of the lower metallization layer M4A, the upper metallization layers M5A and M6A can help reduce the resistance of the circuit net.

第4A圖繪示在佈局400中(佈局400中的金屬化層類似於佈局300中的金屬化層)佈線示例性長電路網N1和示例性短電路網N2的示意圖。佈局400可用於製造如第4B圖所示的積體電路400A(亦可稱之為積體電路結構)。 FIG. 4A shows a schematic diagram of routing an exemplary long net N1 and an exemplary short net N2 in a layout 400 (metallization layers in layout 400 are similar to metallization layers in layout 300 ). The layout 400 can be used to fabricate an integrated circuit 400A (also referred to as an integrated circuit structure) as shown in FIG. 4B.

如上所述，佈局400包括第一組金屬化層模型Group_1和堆疊在第一組金屬化層模型Group_1上方的第二組金屬化層模型Group_2。第一組金屬化層模型Group_1包括第一金屬化層M1、位於第一金屬化層M1上方的第二金屬化層M2和位於第二金屬化層M2上方的第三金屬化層M3。第二組金屬化層模型Group_2包括第四金屬化層M4、在第四金屬化層M4上方的第五金屬化層M5和在第五金屬化層M5上方的第六金屬化層M6。金屬 化層M1至M6中的金屬線411至416和金屬通孔421至426的幾何形狀比例與第3A圖至第3B圖所示之佈局300中的金屬線311至316和金屬通孔321至326的幾何形狀比例相同，因此，為了簡潔起見不再重複。 As described above, the layout 400 includes a first group of metallization layer models Group_1 and a second group of metallization layer models Group_2 stacked above the first group of metallization layer models Group_1. The first metallization layer model Group_1 includes a first metallization layer M1 , a second metallization layer M2 above the first metallization layer M1 , and a third metallization layer M3 above the second metallization layer M2 . The second metallization layer model Group_2 includes a fourth metallization layer M4, a fifth metallization layer M5 above the fourth metallization layer M4, and a sixth metallization layer M6 above the fifth metallization layer M5. Metal The geometric proportions of metal lines 411-416 and metal vias 421-426 in layers M1-M6 are the same as those of metal lines 311-316 and metal vias 321-326 in layout 300 shown in FIGS. 3A-3B. The proportions of the geometric shapes are the same and, therefore, are not repeated for the sake of brevity.

連接兩個半導體元件的長電路網N1佈線在金屬化層M3上，而不是佈線在上面的金屬化層(例如，第六金屬化層M6)上。因此，減少了用於長電路網N1的通孔數量。例如，在所繪示的佈局400中，長電路網N1佈線在第三金屬化層M3上，此長電路網N1使用六個通孔(例如，兩個通孔421、兩個通孔422和兩個通孔423)。相反地，如果長電路網N1佈線在第六金屬化層M6上，則此長電路網N1會使用十二個通孔(例如，兩個通孔421、兩個通孔422、兩個通孔423、兩個通孔424、兩個通孔425和兩個通孔426)，這將導致電阻增加。因此，在比上面的金屬化層低的金屬化層上佈線長電路網N1可以使長電路網N1的電阻減小。此外，因為連接其他半導體元件的短電路網N2的長度(例如，電路網之金屬線的總長度)比長電路網N1的長度短，所以可以在比金屬化層M3更高的金屬化層上佈線短電路網N2。作為示例而非限制，因為與長電路網N1相比，短電路網N2對信號延遲的擔憂較為寬鬆，因此將短電路網N2佈線在比金屬化層M3高且具有比金屬化層M3的金屬線線寬和線至線間距小的金屬化層M4上。 The long circuit net N1 connecting the two semiconductor components is routed on the metallization layer M3, but not on the metallization layer above (for example, the sixth metallization layer M6). Therefore, the number of via holes for the long circuit net N1 is reduced. For example, in the illustrated layout 400, a long circuit net N1 is routed on the third metallization layer M3 using six vias (eg, two vias 421, two vias 422 and two through holes 423). On the contrary, if the long circuit net N1 is routed on the sixth metallization layer M6, then this long circuit net N1 will use twelve vias (for example, two vias 421, two vias 422, two vias 423, two vias 424, two vias 425, and two vias 426), which will result in increased resistance. Therefore, wiring the long circuit net N1 on a metallization layer lower than the metallization layer above can reduce the resistance of the long circuit net N1. In addition, because the length of the short circuit net N2 (for example, the total length of the metal lines of the circuit net) connected to other semiconductor elements is shorter than the length of the long circuit net N1, it can be formed on a higher metallization layer than the metallization layer M3. Wiring short circuit network N2. By way of example and not limitation, because short-circuit net N2 has less signal delay concerns than long-circuit net N1, short-circuit net N2 is routed higher and with a metal On metallization layer M4 with small line width and line-to-line spacing.

第4B圖是根據本公開的部分實施例使用佈局 400製造的積體電路結構400A的剖面圖，因此，積體電路結構400A繼承了佈局400中那些圖案的幾何形狀比例。可以在第1圖所示的製造流程100的步驟122中製造積體電路結構400A。積體電路結構400A是用於促進本公開的說明的非限制性示例。 Figure 4B is a layout used according to some embodiments of the present disclosure 400 is a cross-sectional view of fabricated integrated circuit structure 400A, and thus integrated circuit structure 400A inherits the geometric proportions of those patterns in layout 400 . The integrated circuit structure 400A may be fabricated in step 122 of the fabrication flow 100 shown in FIG. 1 . Integrated circuit structure 400A is a non-limiting example used to facilitate the description of the present disclosure.

積體電路結構400A包括四個元件402A，電連接兩個元件402A的長電路網N1和連接兩個元件402A的短電路網N2。在所繪示的實施例中，元件402A是鰭式場效應電晶體，每個鰭式場效應電晶體包括從基板401A突出並且具有由淺溝槽隔離區域405A橫向地圍繞其下部的鰭片403A，在鰭片403A中形成的源極/汲極區域404A，橫向地在源極/汲極區域404A之間的高介電常數金屬閘極閘極結構406A和在閘極結構406A的相對側壁上的閘極間隔物407A。基板401A、鰭片403A、源極/汲極區域404A、淺溝槽隔離區域405A、閘極結構406A和閘極間隔物407A的示例材料和製造與先前關於第3C圖所討論的鰭式場效應電晶體302A相似，因此，為了簡潔起見不再重複。 The integrated circuit structure 400A includes four elements 402A, a long circuit net N1 electrically connecting the two elements 402A, and a short circuit net N2 electrically connecting the two elements 402A. In the illustrated embodiment, elements 402A are FinFETs each comprising a fin 403A protruding from a substrate 401A and having a lower portion laterally surrounded by a shallow trench isolation region 405A, in Source/drain regions 404A formed in fins 403A, high-k metal gate structures 406A laterally between source/drain regions 404A and gate structures on opposing sidewalls of gate structures 406A pole spacer 407A. The example materials and fabrication of substrate 401A, fins 403A, source/drain regions 404A, shallow trench isolation regions 405A, gate structures 406A, and gate spacers 407A are similar to the FinFETs previously discussed with respect to FIG. 3C. Crystal 302A is similar and, therefore, not repeated for brevity.

積體電路結構400A還包括在鰭式場效應電晶體402A上方的層間介電層441A，以及延伸穿過層間介電層441A以到達鰭式場效應電晶體402A的閘極結構406A和/或源極/汲極區域404A的接觸件408A。層間介電層441A和接觸件408A的示例性材料和製造與先前關於第3C圖所討論的層間介電層341A和接觸件308A的示例 性材料和製造相似，因此，為了簡潔起見不再重複。 The integrated circuit structure 400A also includes an interlayer dielectric layer 441A over the FinFET 402A, and a gate structure 406A and/or source/ Contact 408A of drain region 404A. Exemplary materials and fabrication of interlayer dielectric layer 441A and contact 408A are the same as the example of interlayer dielectric layer 341A and contact 308A previously discussed with respect to FIG. 3C. The general materials and fabrication are similar and, therefore, not repeated for brevity.

積體電路結構400A還包括互連結構430A，此互連結構包括使用如第4A圖所示的佈局400的金屬化層M1至M6的佈局圖案製造的複數個金屬化層M1A至M6A，並且因此金屬化層M1A至M6A繼承佈局400中金屬化層M1至M6的佈局圖案的幾何形狀比例。金屬化層M1A至M6A分別地包括金屬間介電層451A至456A和461A至466A。金屬間介電層461A至466A形成在相應的金屬間介電層451A至456A之上。金屬化層M1A至M6A包括水平互連(例如，分別在金屬間介電層461A至466A中水平或橫向地延伸的金屬線411A至416A)，以及垂直互連(例如，分別在金屬間介電層451A至456A中垂直地延伸的金屬通孔421A至426A)。積體電路結構400A的金屬化層M1A至M6A的示例材料和製造與先前關於第3C圖所討論的積體電路結構300A的示例性材料和製造相似，因此，為了簡潔起見不再重複。 The integrated circuit structure 400A also includes an interconnect structure 430A comprising a plurality of metallization layers M1A to M6A fabricated using the layout pattern of the metallization layers M1 to M6 of the layout 400 as shown in FIG. 4A, and thus Metallization layers M1A-M6A inherit the geometrical proportions of the layout pattern of metallization layers M1-M6 in layout 400 . Metallization layers M1A to M6A include intermetal dielectric layers 451A to 456A and 461A to 466A, respectively. The intermetal dielectric layers 461A to 466A are formed over the corresponding intermetal dielectric layers 451A to 456A. Metallization layers M1A to M6A include horizontal interconnects (eg, metal lines 411A to 416A extending horizontally or laterally in IMD layers 461A to 466A, respectively), and vertical interconnects (eg, metal lines 411A to 416A respectively in IMD layers 461A to 466A), vertically extending metal vias 421A-426A in layers 451A-456A). The example materials and fabrication of the metallization layers M1A-M6A of the integrated circuit structure 400A are similar to the example materials and fabrication of the integrated circuit structure 300A previously discussed with respect to FIG. 3C and, therefore, are not repeated for brevity.

連接兩個鰭式場效應電晶體402A的長電路網N1佈線在金屬化層M3A上，而不是佈線在上面的金屬化層(例如，第六金屬化層M6A)上。因此，減少了用於長電路網N1的通孔數量。例如，在所繪示的積體電路結構400A中，將長電路網N1佈線在第三金屬化層M3A上，此長電路網N1會使用六個通孔(例如，兩個通孔421A、兩個通孔422A和兩個通孔423A)。相反地，如果將長電路網N1佈線在第六金屬化層M6A上，則此長電路網 N1會使用十二個通孔(例如，兩個通孔421A、兩個通孔422A、兩個通孔423A、兩個通孔424A、兩個通孔425A和兩個通孔426A)，這將導致電阻增加。因此，在比上面的金屬化層低的金屬化層上佈線長電路網N1可以減小長電路網N1的電阻。此外，因為連接其他鰭式場效應電晶體402A的短電路網N2的長度(例如，電路網之金屬線的總長度)比長電路網N1的長度短，所以可以在比金屬化層M3更高的金屬化層上佈線短電路網N2。作為示例而非限制，由於與長電路網N1相比，短電路網N2對信號延遲的擔憂較為寬鬆，因此可將短電路網N2佈線在比金屬化層M3高並且具有比金屬化層M3A的金屬線線寬和線至線間距小的金屬化層M4A上。 The long net N1 connecting the two FinFETs 402A is routed on the metallization layer M3A, but not on the metallization layer above (eg, the sixth metallization layer M6A). Therefore, the number of via holes for the long circuit net N1 is reduced. For example, in the illustrated integrated circuit structure 400A, a long net N1 is routed on the third metallization layer M3A, and this long net N1 uses six vias (eg, two vias 421A, two vias 421A, through holes 422A and two through holes 423A). Conversely, if the long circuit network N1 is wired on the sixth metallization layer M6A, the long circuit network N1 would use twelve vias (e.g., two vias 421A, two vias 422A, two vias 423A, two vias 424A, two vias 425A, and two vias 426A), which would resulting in an increase in resistance. Therefore, routing the long circuit net N1 on a metallization layer lower than the metallization layer above can reduce the resistance of the long circuit net N1. In addition, because the length of the short circuit net N2 (for example, the total length of the metal lines of the circuit net) connected to other FinFETs 402A is shorter than the length of the long circuit net N1, it can be used at a higher level than the metallization layer M3. The short circuit net N2 is wired on the metallization layer. By way of example and not limitation, since short-circuit net N2 has less signal delay concerns than long-circuit net N1, short-circuit net N2 can be routed higher than metallization layer M3 and has a lower Metal line width and line-to-line spacing are small on the metallization layer M4A.

第5A圖是在本公開的部分實施例中包括群組化的金屬層之其他示例性模型的佈局500的立體圖。第5B圖繪示在第5A圖的佈局中，金屬化層之間的金屬線線寬差異的示意圖。佈局500可用於製造如第5C圖所示的積體電路結構500A。 FIG. 5A is a perspective view of a layout 500 of other exemplary models including grouped metal layers in some embodiments of the present disclosure. FIG. 5B is a schematic diagram illustrating the difference in metal line width between metallization layers in the layout of FIG. 5A. Layout 500 may be used to fabricate integrated circuit structure 500A as shown in FIG. 5C.

佈局500包括第三組金屬化層模型Group_3和堆疊在第三組金屬化層模型Group_3上的第四組金屬化層模型Group_4。模型Group_3和Group_4與先前關於第3A圖和第3B圖所討論的模型Group_1和Group_2不同，並且也可以在庫208中定義(如第2圖所示)。模型Group_3僅包括兩個金屬化層(例如，第一金屬化層M1和在第一金屬化層M1之上的第二金屬化 層M2)。模型Group_4也僅包括兩個金屬化層(例如，在第二金屬化層M2上方的第三金屬化層M3和在第三金屬化層M3上方的第四金屬化層M4)。 The layout 500 includes a third group of metallization layer models Group_3 and a fourth group of metallization layer models Group_4 stacked on the third group of metallization layer models Group_3. Models Group_3 and Group_4 are distinct from models Group_1 and Group_2 previously discussed with respect to FIGS. 3A and 3B , and may also be defined in library 208 (as shown in FIG. 2 ). Model Group_3 includes only two metallization layers (for example, a first metallization layer M1 and a second metallization layer above the first metallization layer M1 layer M2). Model Group_4 also includes only two metallization layers (eg, a third metallization layer M3 above the second metallization layer M2 and a fourth metallization layer M4 above the third metallization layer M3 ).

金屬化層M1至M4包括水平互連(例如，水平或橫向地延伸的金屬線511至514)，以及相應的垂直互連(例如，分別垂直地延伸的金屬通孔521至524)。金屬線511和金屬線513沿著第一方向(例如，如第5A圖的立體圖所示的X方向)延伸，並且沿著第二方向(例如，如第5A圖的立體圖所示的Y方向)彼此間隔開。金屬線512和514沿著第二方向(如第5A圖所示的Y方向)延伸並且沿著第一方向(如第5A圖所示的X方向)彼此間隔開。因此，金屬線511和513的長度方向垂直於金屬線512和514的長度方向。 Metallization layers M1 to M4 include horizontal interconnects (eg, metal lines 511 to 514 extending horizontally or laterally), and corresponding vertical interconnects (eg, metal vias 521 to 524 extending vertically, respectively). The metal wires 511 and 513 extend along a first direction (for example, the X direction shown in the perspective view of FIG. 5A ), and extend along a second direction (for example, the Y direction shown in the perspective view of FIG. 5A ). spaced apart from each other. The metal lines 512 and 514 extend along the second direction (the Y direction shown in FIG. 5A ) and are spaced apart from each other along the first direction (the X direction shown in FIG. 5A ). Therefore, the length direction of the metal lines 511 and 513 is perpendicular to the length direction of the metal lines 512 and 514 .

金屬線511、513具有在Y方向上測量之對應的線寬W51、W53，並且以在Y方向上測量之對應的線至線間距S51、S53配置。金屬線512、514具有在X方向上測量之對應的線寬W52、W54，並且以在X方向上測量之對應的線至線間距S52、S54配置。金屬線511、513的線寬W51、W53小於金屬線512、514的線寬W52、W54。金屬線511、513的線至線間距S51、S53小於金屬線512、514的線至線間距S52、S54。因此，金屬化層M1的佈線密度大於金屬化層M2的佈線密度，這將有助於連接在第一金屬化層M1下面按比例縮小尺寸的元件(例如，在10nm、7nm、5nm或3nm技術節點處的電 晶體)。此外，因為金屬線512的線寬W52大於在金屬線512上方的金屬線513的線寬W53，所以金屬線512的電阻低於金屬線513的電阻。以此方式，可以在金屬化層M2上佈線較長的電路網(即，金屬線總長度較長的電路網)，以減小較長的電路網的電阻，並且可以在金屬化層M3上佈線較短的電路網(即，金屬線總長度較短的電路網)。 The metal lines 511 , 513 have corresponding line widths W51 , W53 measured in the Y direction, and are arranged with corresponding line-to-line spacings S51 , S53 measured in the Y direction. The metal lines 512, 514 have corresponding line widths W52, W54 measured in the X direction and are arranged with corresponding line-to-line spacings S52, S54 measured in the X direction. The line widths W51 and W53 of the metal lines 511 and 513 are smaller than the line widths W52 and W54 of the metal lines 512 and 514 . The line-to-line spacing S51 , S53 of the metal lines 511 , 513 is smaller than the line-to-line spacing S52 , S54 of the metal lines 512 , 514 . Therefore, the wiring density of the metallization layer M1 is greater than that of the metallization layer M2, which will facilitate the connection of components that are scaled down below the first metallization layer M1 (for example, in 10nm, 7nm, 5nm or 3nm technology electricity at the node crystal). In addition, since the wire width W52 of the metal line 512 is larger than the line width W53 of the metal line 513 above the metal line 512 , the resistance of the metal line 512 is lower than that of the metal line 513 . In this way, a longer circuit net (that is, a circuit net with a longer total length of metal lines) can be routed on the metallization layer M2 to reduce the resistance of the longer circuit net, and can be routed on the metallization layer M3 Nets with shorter wiring (i.e., nets with shorter overall wire lengths).

在部分實施例中，金屬線511的線寬W51和線至線間距S51與金屬線513的線寬W53和線至線間距S53相同，並且線寬金屬線512的線寬W52和線至線間距S52與金屬線514的線寬W54和線至線間距S54相同。換句話說，群組化的金屬化層模型Group_3和Group_4可以具有相同的尺寸參數(例如，相同的金屬化層數量、在相應的金屬化層中相同的線寬和相同的線間距)。例如，模型Group_3的金屬化層M1具有與模型Group_4的金屬化層M3相同的線寬和線間距，並且模型Group_3的金屬化層M2具有與模型Group_4的金屬化層M4相同的線寬和線間距。然而，在部份其他實施例中，金屬化層M1的線寬W51和線至線間距S51可以不同於金屬化層M3的線寬W53和線至線間距S53，並且金屬化層M2的線寬W52和線至線間距S52可以不同於金屬化層M4的線寬W54和線至線間距S54。 In some embodiments, the line width W51 and line-to-line spacing S51 of the metal line 511 are the same as the line width W53 and line-to-line spacing S53 of the metal line 513, and the line width W52 and line-to-line spacing of the metal line 512 are the same. S52 is the same as the line width W54 and the line-to-line spacing S54 of the metal line 514 . In other words, the grouped metallization layer models Group_3 and Group_4 may have the same size parameters (eg, the same number of metallization layers, the same line width and the same line spacing in the corresponding metallization layers). For example, metallization layer M1 of model Group_3 has the same line width and line spacing as metallization layer M3 of model Group_4, and metallization layer M2 of model Group_3 has the same line width and line spacing as metallization layer M4 of model Group_4 . However, in some other embodiments, the line width W51 and the line-to-line spacing S51 of the metallization layer M1 may be different from the line width W53 and the line-to-line spacing S53 of the metallization layer M3, and the line width of the metallization layer M2 W52 and line-to-line spacing S52 may be different from line width W54 and line-to-line spacing S54 of metallization layer M4.

在部分實施例中，作為示例而非限制，金屬線511、513的線高H51、H53(如第5A圖所示在垂直於X-Y 平面的Z方向上測量的高度)小於金屬線512、514的線高H52、H54。在部分實施例中，作為示例而非限制，金屬線511、513的線高H51、H53小於通孔521至524的通孔高度，但是金屬線512、514的線高H52、H54大於通孔521至524的通孔高度。如做為示例而非限制之第5A圖和第5B圖的實施例所示，金屬線511至514的線寬可以滿足關係式W51=W53<W52=W54，金屬線511至514的線至線間距可以滿足關係式S51=S53<S52=S54，並且金屬線511至514的線高可以滿足關係式H51=H53<H52=H54。 In some embodiments, as an example and not a limitation, the line heights H51, H53 of the metal lines 511, 513 (as shown in FIG. The height measured in the Z direction of the plane) is smaller than the line heights H52, H54 of the metal lines 512, 514. In some embodiments, as an example and not limitation, the line heights H51, H53 of the metal lines 511, 513 are smaller than the via heights of the via holes 521 to 524, but the line heights H52, H54 of the metal lines 512, 514 are greater than the via hole 521 to a via height of 524. As shown in the embodiments of Fig. 5A and Fig. 5B as an example and not limiting, the line width of the metal lines 511 to 514 can satisfy the relationship W51=W53<W52=W54, and the line-to-line of the metal lines 511 to 514 The spacing can satisfy the relationship S51=S53<S52=S54, and the line heights of the metal lines 511 to 514 can satisfy the relationship H51=H53<H52=H54.

第5C圖是根據本公開的部分實施例使用佈局500製造的積體電路結構500A的剖面圖，因此，積體電路結構500A繼承了佈局500中那些圖案的幾何形狀比例(如下面更詳細的訊息)。如第1圖所示，可以在製造流程100的步驟122中在製造廠中製造積體電路結構500A。積體電路結構500A是用於促進本公開說明的非限制性示例。 FIG. 5C is a cross-sectional view of an integrated circuit structure 500A fabricated using layout 500 in accordance with some embodiments of the present disclosure. Thus, integrated circuit structure 500A inherits the geometrical proportions of those patterns in layout 500 (as described in more detail below. ). As shown in FIG. 1 , integrated circuit structure 500A may be fabricated in a fab in step 122 of fabrication process 100 . Integrated circuit structure 500A is a non-limiting example used to facilitate the description of the present disclosure.

積體電路結構500A包括可以是鰭式場效應電晶體的元件502A，此鰭式場效應電晶體包括從基板501A突出並具有由淺溝槽隔離區域505A橫向地圍繞其下部的鰭片503A，形成在鰭片503A中的源極/汲極區域504A，橫向地在源極/汲極區域504A之間的高介電常數金屬閘極閘極結構和在閘極結構506A的相對側壁上的閘極間隔物507A。基板501A、鰭片503A、源極/汲極區域504A、 淺溝槽隔離區域505A、閘極結構506A和閘極間隔物507A的示例材料和製造與先前關於第3C圖中所討論的鰭式場效應電晶體302A相似，因此，為了簡潔起見不再重複。 The integrated circuit structure 500A includes an element 502A which may be a FinFET comprising a fin 503A protruding from a substrate 501A and having a lower portion laterally surrounded by a shallow trench isolation region 505A formed on the fin 503A. Source/drain regions 504A in sheet 503A, high-k metal gate structures laterally between source/drain regions 504A and gate spacers on opposing sidewalls of gate structures 506A 507A. substrate 501A, fins 503A, source/drain regions 504A, The example materials and fabrication of shallow trench isolation regions 505A, gate structures 506A, and gate spacers 507A are similar to those previously discussed with respect to FIG. 3C for FinFET 302A and, therefore, are not repeated for brevity.

積體電路結構500A還包括在鰭式場效應電晶體502A之上的層間介電層541A，以及延伸穿過層間介電層541A以到達鰭式場效應電晶體502A的閘極結構506A和/或源極/汲極區域504A的接觸件508A。層間介電層541A和接觸件508A的示例性材料和製造與先前關於第3C圖所討論的層間介電層341A和接觸件308A的示例性材料和製造相似，因此，為了簡潔起見不再重複。 The integrated circuit structure 500A also includes an interlayer dielectric layer 541A over the FinFET 502A, and a gate structure 506A and/or source extending through the interlayer dielectric layer 541A to the FinFET 502A. Contact 508A of /drain region 504A. Exemplary materials and fabrication of interlayer dielectric layer 541A and contacts 508A are similar to those previously discussed with respect to FIG. 3C and, therefore, are not repeated for brevity. .

積體電路結構500A還包括互連結構530A，此互連結構530A包括複數個金屬化層M1A至M4A，其使用如第5A圖所示之佈局500的金屬化層M1至M4的佈局圖案製造，並且因此金屬化層M1A至M4A繼承佈局500中金屬化層M1至M4的佈局圖案的幾何形狀比例。金屬化層M1A至M4A分別地包括金屬間介電層551A至554A和561A至564A。金屬間介電層561A至564A形成在相應的金屬間介電層551A至554A之上。金屬化層M1A至M4A包括水平互連(例如，分別在金屬間介電層561A至564A中水平或橫向地延伸的金屬線511A至514A)，以及垂直互連(例如，分別在金屬間介電層551A至554A中垂直地延伸的金屬通孔521A至524A)。積體電路結構500A的金屬化層M1A至M4A的示例材料和 製造與先前關於第3C圖所討論的積體電路結構300A的材料和製造相似，因此，為了簡潔起見不再重複。 The integrated circuit structure 500A also includes an interconnect structure 530A including a plurality of metallization layers M1A to M4A fabricated using a layout pattern of the metallization layers M1 to M4 of the layout 500 shown in FIG. 5A, And thus metallization layers M1A to M4A inherit the geometrical proportions of the layout pattern of metallization layers M1 to M4 in layout 500 . Metallization layers M1A to M4A include intermetal dielectric layers 551A to 554A and 561A to 564A, respectively. The intermetal dielectric layers 561A to 564A are formed over the corresponding intermetal dielectric layers 551A to 554A. Metallization layers M1A to M4A include horizontal interconnects (eg, metal lines 511A to 514A extending horizontally or laterally in IMD layers 561A to 564A, respectively), and vertical interconnects (eg, metal lines 511A to 514A respectively in IMD layers 561A to 564A), vertically extending metal vias 521A-524A in layers 551A-554A). Example materials and Fabrication is similar to the materials and fabrication of the integrated circuit structure 300A previously discussed with respect to FIG. 3C and, therefore, is not repeated for brevity.

金屬線511A至514A和金屬通孔521A至524A具有與佈局500中相應的金屬線511至514和金屬通孔521至524相同的幾何形狀比例。更詳細地，金屬線511A和513A沿著第一方向(例如，如第5A圖的立體圖所示的X方向)延伸，並且沿著第二方向(例如，如第5A圖的立體圖所示的Y方向)彼此間隔開。金屬線512A和514A沿著第二方向(如第5A圖所示的Y方向)延伸，並且沿著第一方向(如第5A圖所示的X方向)彼此間隔開。因此，金屬線511A和513A的長度方向垂直於金屬線512A和514A的長度方向。 Metal lines 511A to 514A and metal vias 521A to 524A have the same geometrical proportions as corresponding metal lines 511 to 514 and metal vias 521 to 524 in layout 500 . In more detail, the metal lines 511A and 513A extend along a first direction (for example, the X direction shown in the perspective view of FIG. 5A ), and extend along a second direction (for example, the Y direction shown in the perspective view of FIG. 5A ). direction) are spaced apart from each other. Metal lines 512A and 514A extend along a second direction (Y direction shown in FIG. 5A ), and are spaced apart from each other along a first direction (X direction shown in FIG. 5A ). Therefore, the length direction of the metal lines 511A and 513A is perpendicular to the length direction of the metal lines 512A and 514A.

金屬線511A、513A的線寬W51、W53小於金屬線512A、514A的線寬W52、W54。金屬線511A、513A的線至線間距S51、S53小於金屬線512A、514A的線至線間距S52、S54。因此，金屬化層M1A的佈線密度大於金屬化層M2A的佈線密度，這將有助於連接在第一金屬化層M1A下面按比例縮小的元件(例如，處於10nm、7nm、5nm或3nm技術節點的電晶體)。此外，因為金屬線512A的線寬W52大於在金屬線512A上方的金屬線513A的線寬W53，所以金屬線512A具有比金屬線513A低的電阻。以此方式，可以在金屬化層M2A上佈線較長的電路網(即，具有較長的金屬線總長度的電路網)以減少較長的電路網的電阻，並且可以在金屬化層 M3A上佈線較短的電路網(即，具有較短的金屬線總長度的電路網)。 The line widths W51 and W53 of the metal lines 511A and 513A are smaller than the line widths W52 and W54 of the metal lines 512A and 514A. The line-to-line spacing S51 , S53 of the metal lines 511A, 513A is smaller than the line-to-line spacing S52 , S54 of the metal lines 512A, 514A. Therefore, the wiring density of metallization layer M1A is greater than the wiring density of metallization layer M2A, which will facilitate the connection of components that are scaled down below the first metallization layer M1A (for example, at 10nm, 7nm, 5nm or 3nm technology nodes). transistors). In addition, because the line width W52 of the metal line 512A is larger than the line width W53 of the metal line 513A above the metal line 512A, the metal line 512A has a lower resistance than the metal line 513A. In this way, a longer net (that is, a net with a longer total length of metal lines) can be routed on the metallization layer M2A to reduce the resistance of the longer net, and the metallization layer A shorter net (ie, a net with a shorter total metal wire length) is routed on the M3A.

在第5A圖至第5C圖中，將兩個相同的模型堆疊在一起。然而，沒有限制相同模型的重複次數。例如，第6A圖至第6C圖繪示在佈局中堆疊在一起之三個相同的模型。第6A圖是在本公開的部分實施例中包括堆疊在一起之三個相同模型的佈局600的立體圖。第6B圖繪示在第6A圖的佈局中，金屬化層之間的金屬線線寬差異的示意圖。佈局600可用於製造如第6C圖所示的積體電路結構600A。 In Figures 5A to 5C, two identical models are stacked together. However, there is no limit to the number of repetitions of the same model. For example, Figures 6A-6C show three identical models stacked together in a layout. Figure 6A is a perspective view of a layout 600 including three identical models stacked together in some embodiments of the present disclosure. FIG. 6B is a schematic diagram illustrating the difference in metal line width between metallization layers in the layout of FIG. 6A. Layout 600 may be used to fabricate integrated circuit structure 600A as shown in FIG. 6C.

佈局600中的模型Group_3和Group_4的細節已在先前關於第5A圖和第5B圖中討論過，因此，為了簡潔起見不再重複。佈局600還包括堆疊在模型Group_4上並且具有與模型Group_3和Group_4相同的尺寸參數的第五組金屬化層模型Group_5。例如，模型Group_5僅包括兩個金屬化層(例如，第五金屬化層M5和在第五金屬化層M5上方的第六金屬化層M6)。金屬化層M5至M6包括水平互連(例如，水平或橫向地延伸的金屬線615至616)，以及相應的垂直互連(例如，分別垂直地延伸的金屬通孔625至626)。金屬線615沿著X方向延伸並且沿著Y方向彼此間隔開，因此，金屬線615沿平行於金屬線513和511並且垂直於金屬線514和512的方向延伸。金屬線616沿著Y方向延伸並且沿著X方向彼此間隔開，因此，金屬線616沿平行於金屬線514和 512並且垂直於金屬線615、513和511的方向延伸。 The details of models Group_3 and Group_4 in layout 600 have been discussed previously with respect to Figures 5A and 5B and, therefore, are not repeated for the sake of brevity. Layout 600 also includes a fifth group of metallization layer models Group_5 stacked on model Group_4 and having the same dimensional parameters as models Group_3 and Group_4. For example, model Group_5 includes only two metallization layers (eg, fifth metallization layer M5 and sixth metallization layer M6 above fifth metallization layer M5 ). Metallization layers M5 - M6 include horizontal interconnects (eg, metal lines 615 - 616 extending horizontally or laterally), and corresponding vertical interconnects (eg, metal vias 625 - 626 extending vertically, respectively). The metal lines 615 extend in the X direction and are spaced apart from each other in the Y direction, thus, the metal lines 615 extend in a direction parallel to the metal lines 513 and 511 and perpendicular to the metal lines 514 and 512 . The metal lines 616 extend along the Y direction and are spaced apart from each other along the X direction, therefore, the metal lines 616 are parallel to the metal lines 514 and 512 and extend perpendicular to the direction of metal lines 615 , 513 and 511 .

金屬線615具有在Y方向上測量的線寬W65和在Y方向上測量的線高H65，並且金屬線615以在Y方向上測量的線至線間距S65配置。金屬線615的線寬W65、線高H65和線至線間距S65分別與金屬線513的線寬W53、線高H53和線至線間距S53相同，並且也分別與金屬線511的線寬W51、線高H51和線至線間距S51相同。金屬線616具有在X方向上量測的線寬W66和在Z方向上量測的線高H66，並且金屬線616以在X方向上測量的線至線間距S66配置。金屬線616的線寬W66、線高H66和線至線間距S66分別與金屬線514的線寬W54、線高H54和線至線間距S54相同，並且也分別與金屬線512的相應線寬W52、線高H52和線至線間距S52相同。因此，第五組金屬化層模型Group_5具有與模型Group_3和Group_4相同的尺寸參數。 The metal line 615 has a line width W65 measured in the Y direction and a line height H65 measured in the Y direction, and the metal line 615 is configured with a line-to-line spacing S65 measured in the Y direction. The line width W65, line height H65, and line-to-line spacing S65 of the metal line 615 are respectively the same as the line width W53, line height H53, and line-to-line spacing S53 of the metal line 513, and are also the same as the line width W51, The line height H51 is the same as the line-to-line spacing S51. The metal lines 616 have a line width W66 measured in the X direction and a line height H66 measured in the Z direction, and the metal lines 616 are arranged with a line-to-line spacing S66 measured in the X direction. The line width W66, line height H66, and line-to-line spacing S66 of the metal line 616 are respectively the same as the line width W54, line height H54, and line-to-line spacing S54 of the metal line 514, and are also respectively the same as the corresponding line width W52 of the metal line 512. , line height H52 and line-to-line spacing S52 are the same. Therefore, the fifth group of metallization layer models Group_5 has the same size parameters as the models Group_3 and Group_4.

更詳細地，金屬線511、513、615的線寬W51、W53、W65小於金屬線512、514、616的線寬W52、W54、W66。金屬線511、513、615的線至線間距S51、S53、S65小於金屬線512、514、616的線至線間距S52、S54、S66。因此，金屬線514的電阻比金屬線615的電阻低。以此方式，可以在金屬化層M4上佈線較長的電路網(即，金屬線總長度較長的電路網)，以減小較長的電路網的電阻，而可以在金屬化層M5上佈線較短的電路網(即，金屬線總長度較短的電路網)。 In more detail, the line widths W51 , W53 , W65 of the metal lines 511 , 513 , 615 are smaller than the line widths W52 , W54 , W66 of the metal lines 512 , 514 , 616 . The line-to-line spacings S51 , S53 , S65 of the metal lines 511 , 513 , 615 are smaller than the line-to-line spacings S52 , S54 , S66 of the metal lines 512 , 514 , 616 . Therefore, the resistance of the metal line 514 is lower than that of the metal line 615 . In this way, a longer circuit net (that is, a circuit net with a longer total length of metal lines) can be wired on the metallization layer M4 to reduce the resistance of the longer circuit net, while the metallization layer M5 can Nets with shorter wiring (i.e., nets with shorter overall wire lengths).

第6C圖是根據本公開的部分實施例使用佈局600製造的積體電路結構600A的剖面圖，因此，積體電路結構600A繼承了佈局600中那些圖案的幾何形狀比例(如下面更詳細的訊息)。如第1圖所示，可以在製造流程100的步驟122在製造廠中製造積體電路結構600A。積體電路結構600A是用於促進本公開說明的非限制性示例。 FIG. 6C is a cross-sectional view of an integrated circuit structure 600A fabricated using layout 600 in accordance with some embodiments of the present disclosure. Thus, integrated circuit structure 600A inherits the geometrical proportions of those patterns in layout 600 (as described in more detail below. ). As shown in FIG. 1 , integrated circuit structure 600A may be fabricated in a fab at step 122 of fabrication process 100 . Integrated circuit structure 600A is a non-limiting example used to facilitate the description of the present disclosure.

積體電路結構600A類似於積體電路結構500A，除了互連結構630A還包括在金屬化層M4A之上的金屬化層M5A和在金屬化層M5A之上的金屬化層M6A之外。如第6A圖所示，使用佈局600的金屬化層M5至M6的佈局圖案來製造金屬化層M5A至M6A，因此，金屬化層M5A至M6A繼承了佈局600中金屬化層M5至M6的佈局圖案的幾何形狀比例。金屬化層M5A至M6A分別地包括金屬間介電層655A至656A和665A至666A。金屬間介電層665A至666A形成在相應的金屬間介電層655A至656A之上。金屬化層M5A至M6A包括水平互連(例如，分別在金屬間介電層665A至666A中水平或橫向地延伸的金屬線615A至616A)，以及垂直互連(例如，分別在金屬間介電層655A至656A中垂直地延伸的金屬通孔625A至626A)。積體電路結構600A的金屬化層M5A至M6A的示例材料和製造與先前關於第3C圖所討論的積體電路結構300A的示例性材料和製造相似，因此，為了簡潔起見不再重複。 Integrated circuit structure 600A is similar to integrated circuit structure 500A, except that interconnect structure 630A also includes metallization layer M5A over metallization layer M4A and metallization layer M6A over metallization layer M5A. As shown in FIG. 6A , metallization layers M5A to M6A are fabricated using the layout pattern of metallization layers M5 to M6 of layout 600 , and thus metallization layers M5A to M6A inherit the layout of metallization layers M5 to M6 in layout 600 The geometric proportions of the pattern. Metallization layers M5A-M6A include intermetal dielectric layers 655A-656A and 665A-666A, respectively. IMD layers 665A-666A are formed over corresponding IMD layers 655A-656A. Metallization layers M5A to M6A include horizontal interconnects (eg, metal lines 615A to 616A extending horizontally or laterally in IMD layers 665A to 666A, respectively), and vertical interconnects (eg, metal lines 615A to 616A respectively in IMD layers 665A to 666A), Vertically extending metal vias 625A-626A in layers 655A-656A). The example materials and fabrication of the metallization layers M5A-M6A of the integrated circuit structure 600A are similar to the example materials and fabrication of the integrated circuit structure 300A previously discussed with respect to FIG. 3C and, therefore, are not repeated for brevity.

金屬線615A至616A和金屬通孔625A至626A具有與佈局500中相應的金屬線615至616和金屬通孔625至626相同的幾何形狀比例，因此，為了簡潔起見，不再重複。金屬化層M1A至M4A與先前關於第5C圖所討論的積體電路結構500A的金屬化層相同，因此，為了簡潔起見不再重複。 Metal lines 615A-616A and metal vias 625A-626A have the same geometrical proportions as corresponding metal lines 615-616 and metal vias 625-626 in layout 500 and, therefore, are not repeated for brevity. The metallization layers M1A-M4A are the same as those of the integrated circuit structure 500A previously discussed with respect to FIG. 5C and, therefore, are not repeated for brevity.

在部分實施例中，不同的模型具有不同數量的金屬化層(如第7A圖至第7C圖所示)。第7A圖是在本公開的部分實施例中包括群組化的金屬層的示例性模型的佈局700的立體圖。第7B圖繪示在第7A圖的佈局中，金屬化層之間的金屬線線寬差異的示意圖。佈局700可用於製造如第7C圖所示的積體電路結構700A。 In some embodiments, different models have different numbers of metallization layers (as shown in FIGS. 7A-7C ). FIG. 7A is a perspective view of a layout 700 of an exemplary model including grouped metal layers in some embodiments of the present disclosure. FIG. 7B is a schematic diagram illustrating the difference in metal line width between metallization layers in the layout of FIG. 7A. Layout 700 may be used to fabricate integrated circuit structure 700A as shown in FIG. 7C.

佈局700包括第六組金屬化層模型Group_6和堆疊在第六組金屬化層模型Group_6上方的第七組金屬化層模型Group_7。模型Group_6和Group_7定義在庫208中，並且至少在金屬化層的數量上不同。例如，模型Group_6僅包括兩個金屬化層(例如，第一金屬化層M1和在第一金屬化層M1上方的第二金屬化層M2)，但是模型Group_7包括三個金屬化層(例如，在第二金屬化層M2上方的第三金屬化層M3、在第三金屬化層M3上方的第四金屬化層M4和在第四金屬化層M4上方的第五金屬化層M5)。 Layout 700 includes a sixth group of metallization layer models Group_6 and a seventh group of metallization layer models Group_7 stacked above the sixth group of metallization layer models Group_6. Models Group_6 and Group_7 are defined in library 208 and differ at least in the number of metallization layers. For example, model Group_6 includes only two metallization layers (e.g., a first metallization layer M1 and a second metallization layer M2 above first metallization layer M1), but model Group_7 includes three metallization layers (e.g., A third metallization layer M3 above the second metallization layer M2, a fourth metallization layer M4 above the third metallization layer M3, and a fifth metallization layer M5 above the fourth metallization layer M4).

金屬化層M1至M5包括水平互連(例如，水平或橫向地延伸的金屬線711至715)，以及相應的垂直互連 (例如，分別垂直地延伸的金屬通孔721至725)。金屬線711、713和715沿著第一方向(例如，如第7A圖的立體圖所示的X方向)延伸，並且沿著第二方向(例如，如第7A圖的立體圖所示的Y方向)彼此間隔開。金屬線712和714沿著第二方向(如第7A圖所示的Y方向)延伸並且沿著第一方向(如第7A圖所示的X方向)彼此間隔開。因此，金屬線711、713和715的長度方向垂直於金屬線712和714的長度方向。 Metallization layers M1 to M5 include horizontal interconnects (eg, metal lines 711 to 715 extending horizontally or laterally), and corresponding vertical interconnects (eg, vertically extending metal vias 721 to 725 , respectively). Metal lines 711, 713, and 715 extend along a first direction (for example, the X direction as shown in the perspective view of FIG. 7A ), and along a second direction (for example, the Y direction as shown in the perspective view of FIG. 7A ). spaced apart from each other. Metal lines 712 and 714 extend along a second direction (Y direction as shown in FIG. 7A ) and are spaced apart from each other along a first direction (X direction as shown in FIG. 7A ). Therefore, the length direction of the metal lines 711 , 713 and 715 is perpendicular to the length direction of the metal lines 712 and 714 .

金屬線711、713、715具有在Y方向上測量之對應的線寬W71、W73、W75，並且以在Y方向上測量之對應的線至線間距S71、S73、S75配置。金屬線712、714具有在X方向上測量之對應的線寬W72、W74，並且以在X方向上測量之對應的線至線間距S72、S74配置。金屬線711、713的線寬W71、W73小於金屬線712、714的線寬W72、W74。金屬線711、713的線至線間距S71、S73小於金屬線712、714的線至線間距S72、S74。因此，金屬化層M1的佈線密度大於金屬化層M2的佈線密度，這將助於連接在第一金屬化層M1下方按比例縮小尺寸的元件(例如，在10nm、7nm、7nm或3nm技術節點處的電晶體)。此外，因為金屬線712的線寬W72大於在金屬線712上方的金屬線713的線寬W73，所以金屬線712的電阻低於金屬線713的電阻。以這種方式，可以在金屬化層M2上佈線較長的電路網(即，金屬線總長度較長的電路網)以減小較長的電路網的電阻，並 且可以在金屬化層M3上佈線較短的電路網(即，金屬線總長度較短的電路網)。在部分實施例中，金屬線715的線寬W75和線至線間距S75分別與金屬線714的線寬W74和線至線間距S74相同。作為示例而非限制，金屬線711至715的線寬可以滿足關係式W71=W73<W72<W74=W75，並且金屬線711至715的線至線間距可以滿足關係式S71=S73<S72<S74=S75。 Metal lines 711 , 713 , 715 have corresponding line widths W71 , W73 , W75 measured in the Y direction, and are arranged with corresponding line-to-line spacings S71 , S73 , S75 measured in the Y direction. The metal lines 712, 714 have corresponding line widths W72, W74 measured in the X direction and are arranged with corresponding line-to-line spacings S72, S74 measured in the X direction. The line widths W71 , W73 of the metal lines 711 , 713 are smaller than the line widths W72 , W74 of the metal lines 712 , 714 . The line-to-line spacing S71 , S73 of the metal lines 711 , 713 is smaller than the line-to-line spacing S72 , S74 of the metal lines 712 , 714 . Therefore, the wiring density of the metallization layer M1 is greater than the wiring density of the metallization layer M2, which will facilitate the connection of components that are scaled down below the first metallization layer M1 (for example, at the 10nm, 7nm, 7nm or 3nm technology node Transistors at the location). In addition, since the metal line 712 has a line width W72 greater than the line width W73 of the metal line 713 above the metal line 712 , the resistance of the metal line 712 is lower than that of the metal line 713 . In this way, a longer net (ie, a net with a longer total length of metal lines) can be routed on the metallization layer M2 to reduce the resistance of the longer net, and And a shorter circuit network (that is, a circuit network with a shorter total length of metal wires) can be routed on the metallization layer M3. In some embodiments, the line width W75 and the line-to-line spacing S75 of the metal line 715 are respectively the same as the line width W74 and the line-to-line spacing S74 of the metal line 714 . As an example and not limitation, the line width of the metal lines 711 to 715 may satisfy the relationship W71=W73<W72<W74=W75, and the line-to-line spacing of the metal lines 711 to 715 may satisfy the relationship S71=S73<S72<S74 =S75.

在部分實施例中，作為示例而非限制，金屬線711、712、713的線高H71、H72、H73(如第7A圖所示，在垂直於X-Y平面的Z方向上測量)小於金屬線714、715的線高H74、H75。在部分實施例中，作為示例而非限制，金屬線711、712、713的線高H71、H72、H73小於通孔721至725的通孔高度，但是金屬線714、715的線高H74、H75大於通孔721至725的通孔高度。作為示例而非限制，金屬線711至715的線高可以滿足關係式H71=H72=H73<H74=H75或H71=H73<H72<H74=H75。 In some embodiments, as an example and not a limitation, the wire heights H71, H72, H73 of the metal lines 711, 712, 713 (as shown in FIG. 7A, measured in the Z direction perpendicular to the X-Y plane) are smaller than the metal line 714 , 715 line height H74, H75. In some embodiments, as an example and not limitation, the line heights H71, H72, H73 of the metal lines 711, 712, 713 are smaller than the via heights of the via holes 721 to 725, but the line heights H74, H75 of the metal lines 714, 715 Greater than the via heights of the vias 721 to 725 . As an example and not a limitation, the line heights of the metal lines 711 to 715 may satisfy the relationship H71=H72=H73<H74=H75 or H71=H73<H72<H74=H75.

第7C圖是根據本公開的部分實施例使用佈局700製造的積體電路結構700A的剖面圖，因此，積體電路結構700A繼承了佈局700中那些圖案的幾何形狀比例(如下面更詳細的訊息)。如第1圖所示，可以在製造流程100的步驟122中在製造商中製造積體電路結構700A。積體電路結構700A是用於促進本公開的說明的非限制性示例。 FIG. 7C is a cross-sectional view of an integrated circuit structure 700A fabricated using layout 700 in accordance with some embodiments of the present disclosure. Thus, integrated circuit structure 700A inherits the geometrical proportions of those patterns in layout 700 (as described in more detail below. ). As shown in FIG. 1 , integrated circuit structure 700A may be fabricated in a fabricator in step 122 of fabrication flow 100 . Integrated circuit structure 700A is a non-limiting example used to facilitate the description of the present disclosure.

積體電路結構700A包括可以是鰭式場效應電晶體的元件702A，其包括從基板701A突出並具有由淺溝槽隔離區域705A橫向地圍繞的其下部的鰭片703A，形成在鰭片703A中的源極/汲極區域704A，橫向地在源極/汲極區域704A之間的高介電常數金屬閘極閘極結構706A以及在閘極結構706A的相對側壁上的閘極間隔物707A。基板701A、鰭片703A、源極/汲極區域704A、淺溝槽隔離區域705A、閘極結構706A和閘極間隔物707A的示例材料和製造與先前在第3C圖中所討論的鰭式場效應電晶體302A相似，因此，為了簡潔起見不再重複。 The integrated circuit structure 700A includes an element 702A, which may be a FinFET, including a fin 703A protruding from a substrate 701A and having its lower portion laterally surrounded by shallow trench isolation regions 705A, in which fins 703A are formed. Source/drain regions 704A, high-k metal gate structure 706A laterally between source/drain regions 704A, and gate spacers 707A on opposing sidewalls of gate structure 706A. Exemplary materials and fabrication of substrate 701A, fins 703A, source/drain regions 704A, shallow trench isolation regions 705A, gate structures 706A, and gate spacers 707A are similar to the finfield effect previously discussed in Figure 3C. Transistor 302A is similar and, therefore, not repeated for brevity.

積體電路結構700A還包括在鰭式場效應電晶體702A上方的層間介電層741A，以及延伸穿過層間介電層741A以到達鰭式場效應電晶體702A的閘極結構706A和/或源極/汲極區域704A的接觸件708A。層間介電層741A和接觸件708A的示例性材料和製造與先前關於第3C圖所討論的層間介電層341A和接觸件308A的示例性材料和製造相似，因此，為了簡潔起見不再重複。 The integrated circuit structure 700A also includes an interlayer dielectric layer 741A over the FinFET 702A, and a gate structure 706A and/or source/ Contact 708A of drain region 704A. The exemplary materials and fabrication of interlayer dielectric layer 741A and contact 708A are similar to the exemplary materials and fabrication of interlayer dielectric layer 341A and contact 308A discussed previously with respect to FIG. .

積體電路結構700A還包括互連結構730A，此互連結構730A包括複數個金屬化層M1A至M5A，其使用如第7A圖所示的佈局700的金屬化層M1至M5的佈局圖案製造，並且因此金屬化層M1A至M5A繼承佈局700中的金屬化層M1至M4的佈局圖案的幾何形狀比例。金屬化層M1A至M5A分別地包括金屬間介電層751A至 755A和761A至765A。金屬間介電層761A至765A形成在相應的金屬間介電層751A至755A之上。金屬化層M1A至M5A包括水平互連(例如，分別在金屬間介電層761A至765A中水平或橫向地延伸的金屬線711A至715A)，以及垂直互連(例如，分別在金屬間介電層751A至755A中垂直地延伸的金屬通孔721A至725A)。積體電路結構700A的金屬化層M1A至M5A的示例材料和製造與先前關於第3C圖所討論的積體電路結構300A的材料和製造相似，因此，為了簡潔起見不再重複。金屬線711A至715A和金屬通孔721A至725A具有與佈局700中相應的金屬線711至715和金屬通孔721至725相同的幾何形狀比例，因此，為了簡潔起見不再重複。 The integrated circuit structure 700A also includes an interconnect structure 730A comprising a plurality of metallization layers M1A to M5A fabricated using a layout pattern of the metallization layers M1 to M5 of the layout 700 shown in FIG. 7A, And thus metallization layers M1A to M5A inherit the geometrical proportions of the layout pattern of metallization layers M1 to M4 in layout 700 . Metallization layers M1A to M5A include intermetal dielectric layers 751A to 755A and 761A to 765A. Intermetal dielectric layers 761A to 765A are formed over corresponding intermetal dielectric layers 751A to 755A. Metallization layers M1A to M5A include horizontal interconnects (eg, metal lines 711A to 715A extending horizontally or laterally in IMD layers 761A to 765A, respectively), and vertical interconnects (eg, metal lines 711A to 715A respectively in IMD layers 761A to 765A), vertically extending metal vias 721A-725A in layers 751A-755A). The example materials and fabrication of metallization layers M1A-M5A of integrated circuit structure 700A are similar to those of integrated circuit structure 300A previously discussed with respect to FIG. 3C and, therefore, are not repeated for brevity. Metal lines 711A-715A and metal vias 721A-725A have the same geometrical proportions as corresponding metal lines 711-715 and metal vias 721-725 in layout 700 and, therefore, are not repeated for brevity.

第8A圖是在本公開的部分實施例中包括群組化的金屬層的示例性模型的佈局800的立體圖。第8B圖繪示在第8A圖的佈局中，金屬化層之間的金屬線線寬差異的示意圖。佈局800可用於製造如第8C圖所示的積體電路結構800A。 FIG. 8A is a perspective view of a layout 800 of an exemplary model including grouped metal layers in some embodiments of the present disclosure. FIG. 8B is a schematic diagram illustrating the difference in metal line width between metallization layers in the layout of FIG. 8A. Layout 800 may be used to fabricate integrated circuit structure 800A as shown in FIG. 8C.

佈局800包括第八組金屬化層模型Group_8和堆疊在第八組金屬化層模型Group_8上的第九組金屬化層模型Group_9。模型Group_8和Group_9定義在庫208中，並且至少在金屬化層的數量上不同。例如，模型Group_8包括三個金屬化層(例如，第一金屬化層M1、在第一金屬化層M1上方的第二金屬化層M2和在第二金屬化層M2上方的第三金屬化層M3)，但是模型Group_9 僅包括兩個金屬化層(例如，在第三金屬化層M3上方的第四金屬化層M4，以及在第四金屬化層M4上方的第五金屬化層M5)。 The layout 800 includes an eighth group of metallization layer models Group_8 and a ninth group of metallization layer models Group_9 stacked on the eighth group of metallization layer models Group_8. Models Group_8 and Group_9 are defined in library 208 and differ at least in the number of metallization layers. For example, model Group_8 includes three metallization layers (e.g., a first metallization layer M1, a second metallization layer M2 above the first metallization layer M1, and a third metallization layer above the second metallization layer M2 M3), but model Group_9 Only two metallization layers are included (eg, a fourth metallization layer M4 above the third metallization layer M3, and a fifth metallization layer M5 above the fourth metallization layer M4).

金屬化層M1至M5包括水平互連(例如，水平或橫向地延伸的金屬線811至815)，以及相應的垂直互連(例如，分別垂直地延伸的金屬通孔821至825)。金屬線811、813和815沿著第一方向(例如，如第8A圖的立體圖所示的X方向)延伸，並且沿著第二方向(例如，如第8A圖的立體圖所示的Y方向)彼此間隔開。金屬線812和814沿著第二方向(如第8A圖所示的Y方向)延伸並且沿著第一方向(如第8A圖所示的X方向)彼此間隔開。因此，金屬線811、813和815的長度方向垂直於金屬線812和814的長度方向。 Metallization layers M1 to M5 include horizontal interconnects (eg, metal lines 811 to 815 extending horizontally or laterally), and corresponding vertical interconnects (eg, metal vias 821 to 825 extending vertically, respectively). The metal lines 811, 813, and 815 extend along a first direction (for example, the X direction as shown in the perspective view of FIG. 8A ), and along a second direction (for example, the Y direction as shown in the perspective view of FIG. 8A ). spaced apart from each other. Metal lines 812 and 814 extend along a second direction (Y direction as shown in FIG. 8A ) and are spaced apart from each other along a first direction (X direction as shown in FIG. 8A ). Therefore, the length direction of the metal lines 811 , 813 and 815 is perpendicular to the length direction of the metal lines 812 and 814 .

金屬線811、813、815具有在Y方向上測量之對應的線寬W81、W83、W85，並且以在Y方向上測量之對應的線至線間距S81、S83、S85配置。金屬線812、814具有在X方向上測量之對應的線寬W82、W84，並且以在X方向上測量之對應的線至線間距S82、S84配置。金屬線811、812、814的線寬W81、W82、W84小於金屬線813、815的線寬W83、W85。金屬線811、812、814的線至線間距S81、S82、S84小於金屬線813、815的線至線間距S83、S85。因此，金屬化層M1的佈線密度大於金屬化層M3的佈線密度，這將有助於連接在第一金屬化層M1下方按比例縮小的元件(例如，處於10nm、 8nm、8nm或3nm技術節點的電晶體)。此外，因為金屬線813的線寬W83大於在金屬線813上方的金屬線814的線寬W84，所以金屬線813的電阻低於金屬線814的電阻。以這種方式，可以在金屬化層M3上佈線較長的電路網(即，具有較長的金屬線總長度的電路網)，以減小較長的電路網的電阻，並且可以在金屬化層M4上佈線較短的電路網(即，具有較短的金屬線總長度的電路網)。作為示例而非限制，金屬線811至815的線寬可以滿足關係式W81<W82=W84<W83=W85，並且金屬線811至815的線至線間距可以滿足關係式S81<S82=S84<S83=S85。 Metal lines 811 , 813 , 815 have corresponding line widths W81 , W83 , W85 measured in the Y direction, and are arranged with corresponding line-to-line spacings S81 , S83 , S85 measured in the Y direction. The metal lines 812, 814 have corresponding line widths W82, W84 measured in the X direction and are arranged with corresponding line-to-line spacings S82, S84 measured in the X direction. The line widths W81 , W82 , W84 of the metal lines 811 , 812 , 814 are smaller than the line widths W83 , W85 of the metal lines 813 , 815 . The line-to-line spacings S81 , S82 , S84 of the metal lines 811 , 812 , 814 are smaller than the line-to-line spacings S83 , S85 of the metal lines 813 , 815 . Therefore, the wiring density of the metallization layer M1 is greater than the wiring density of the metallization layer M3, which will facilitate the connection of components scaled down below the first metallization layer M1 (for example, at 10nm, 8nm, 8nm or 3nm technology node transistors). Furthermore, since the metal line 813 has a line width W83 greater than the line width W84 of the metal line 814 above the metal line 813 , the resistance of the metal line 813 is lower than that of the metal line 814 . In this way, longer nets (i.e., nets with a longer total length of metal lines) can be routed on the metallization layer M3 to reduce the resistance of the longer nets, and can be placed on the metallization layer M3. Shorter nets (ie, nets with shorter overall metal line lengths) are routed on layer M4. As an example and not a limitation, the line width of the metal lines 811 to 815 may satisfy the relationship W81<W82=W84<W83=W85, and the line-to-line spacing of the metal lines 811 to 815 may satisfy the relationship S81<S82=S84<S83 =S85.

在部分實施例中，作為示例而非限制，金屬線811、812、814的線高H81、H82、H84(如第8A圖所示，在垂直於X-Y平面的Z方向上測量)小於金屬線813、815的線高H83、H85。在部分實施例中，作為示例而非限制，金屬線811、812、814的線高H81、H82、H84小於通孔821至825的通孔高度，但是金屬線813、815的線高H83、H85大於通孔821至825的通孔高度。作為示例而非限制，金屬線811至815的線高可以滿足關係式H81=H82=H84<H83=H85或H81<H82=H84<H83=H85。 In some embodiments, as an example and not a limitation, the wire heights H81, H82, H84 of the metal lines 811, 812, 814 (as shown in FIG. 8A, measured in the Z direction perpendicular to the X-Y plane) are smaller than the metal line 813 , 815 line height H83, H85. In some embodiments, as an example but not a limitation, the line heights H81, H82, and H84 of the metal lines 811, 812, and 814 are smaller than the via heights of the via holes 821 to 825, but the line heights H83, H85 of the metal lines 813, 815 Greater than the via heights of the vias 821 to 825 . As an example and not a limitation, the line heights of the metal lines 811 to 815 may satisfy the relationship H81=H82=H84<H83=H85 or H81<H82=H84<H83=H85.

第8C圖是根據本公開的部分實施例使用佈局800製造的積體電路結構800A的剖面圖，因此，積體電路結構800A繼承了佈局800中那些圖案的幾何形狀比例 (如下面更多詳細的訊息)。如第1圖所示，可以在製造流程100的步驟122中在製造廠中製造積體電路結構800A。積體電路結構800A是用於促進本公開說明的非限制性示例。 FIG. 8C is a cross-sectional view of an integrated circuit structure 800A fabricated using layout 800 in accordance with some embodiments of the present disclosure, whereby integrated circuit structure 800A inherits the geometric proportions of those patterns in layout 800 (as more detailed information below). As shown in FIG. 1 , integrated circuit structure 800A may be fabricated in a fab in step 122 of fabrication process 100 . Integrated circuit structure 800A is a non-limiting example used to facilitate the description of the present disclosure.

積體電路結構800A包括可以是鰭式場效應電晶體的元件802A，其包括從基板801A突出並且具有由淺溝槽隔離區域805A橫向地圍繞其下部的鰭片803A，形成在鰭片803A中的源極/汲極區域804A，橫向地在源極/汲極區域804A之間的高介電常數金屬閘極閘極結構，和在閘極結構806A的相對側壁上的閘極間隔物807A。基板801A、鰭片803A、源極/汲極區域804A、淺溝槽隔離區域805A、閘極結構806A和閘極間隔物807A的示例材料和製造與先前關於第3C圖所討論的鰭式場效應電晶體302A相似，因此，為了簡潔起見不再重複。 The integrated circuit structure 800A includes an element 802A, which may be a FinFET, including a fin 803A protruding from a substrate 801A and having a lower portion laterally surrounded by a shallow trench isolation region 805A, in which a source pole/drain regions 804A, a high-k metal gate gate structure laterally between the source/drain regions 804A, and gate spacers 807A on opposing sidewalls of the gate structure 806A. The example materials and fabrication of substrate 801A, fins 803A, source/drain regions 804A, shallow trench isolation regions 805A, gate structures 806A, and gate spacers 807A are similar to the FinFETs previously discussed with respect to FIG. 3C. Crystal 302A is similar and, therefore, not repeated for brevity.

積體電路結構800A還包括在鰭式場效應電晶體802A之上的層間介電層841A，以及延伸穿過層間介電層841A以到達鰭式場效應電晶體802A的閘極結構806A和/或源極/汲極區域804A的接觸件808A。層間介電層841A和接觸件808A的示例性材料和製造與先前關於第3C圖所討論的層間介電層341A和接觸件308A的示例性材料和製造相似，因此，為了簡潔起見不再重複。 The integrated circuit structure 800A also includes an interlayer dielectric layer 841A over the FinFET 802A, and a gate structure 806A and/or source extending through the interlayer dielectric layer 841A to the FinFET 802A. Contact 808A of /drain region 804A. The exemplary materials and fabrication of interlayer dielectric layer 841A and contact 808A are similar to the exemplary materials and fabrication of interlayer dielectric layer 341A and contact 308A discussed previously with respect to FIG. 3C and, therefore, are not repeated for brevity. .

積體電路結構800A還包括互連結構830A，此互連結構830A包括使用如第8A圖所示的佈局800的金屬化層M1至M5的佈局圖案製造的複數個金屬化層M1A 至M5A，並且因此金屬化層M1A至M5A繼承佈局800中的金屬化層M1至M5的佈局圖案的幾何形狀比例。金屬化層M1A至M5A分別地包括金屬間介電層851A至855A和861A至865A。金屬間介電層861A至865A形成在相應的金屬間介電層851A至855A之上。金屬化層M1A至M5A包括水平互連(例如，分別在金屬間介電層861A至865A中水平或橫向地延伸的金屬線811A至815A)，以及垂直互連(例如，分別在金屬間介電層851A至855A中垂直地延伸的金屬通孔821A至825A)。積體電路結構800A的金屬化層M1A至M5A的示例材料和製造與先前關於第3C圖所討論的積體電路結構300A的示例性材料和製造相似，因此，為了簡潔起見不再重複。金屬線811A至815A和金屬通孔821A至825A具有與佈局800中相應的金屬線811至815和金屬通孔821至825相同的幾何形狀比例，因此，為了簡潔起見不再重複。 The integrated circuit structure 800A also includes an interconnect structure 830A including a plurality of metallization layers M1A fabricated using the layout pattern of the metallization layers M1 to M5 of the layout 800 shown in FIG. 8A. to M5A, and thus metallization layers M1A to M5A inherit the geometrical proportions of the layout pattern of metallization layers M1 to M5 in layout 800 . Metallization layers M1A-M5A include intermetal dielectric layers 851A-855A and 861A-865A, respectively. IMD layers 861A to 865A are formed over corresponding IMD layers 851A to 855A. Metallization layers M1A to M5A include horizontal interconnects (eg, metal lines 811A to 815A extending horizontally or laterally in IMD layers 861A to 865A, respectively), and vertical interconnects (eg, metal lines 811A to 815A in IMD layers 861A to 865A, respectively). vertically extending metal vias 821A-825A in layers 851A-855A). The example materials and fabrication of the metallization layers M1A-M5A of the integrated circuit structure 800A are similar to the example materials and fabrication of the integrated circuit structure 300A previously discussed with respect to FIG. 3C and, therefore, are not repeated for brevity. Metal lines 811A-815A and metal vias 821A-825A have the same geometrical proportions as corresponding metal lines 811-815 and metal vias 821-825 in layout 800 and, therefore, are not repeated for brevity.

第9A圖是在本公開的部分實施例中包括群組化的金屬層的示例性模型的佈局900的立體圖。第9B圖繪示在第9A圖的佈局中，金屬化層之間的金屬線線寬差異的示意圖。佈局900可用於製造如第9C圖所示的積體電路結構900A。 FIG. 9A is a perspective view of a layout 900 of an exemplary model including grouped metal layers in some embodiments of the present disclosure. FIG. 9B is a schematic diagram illustrating the difference in metal line width between metallization layers in the layout of FIG. 9A. Layout 900 may be used to fabricate integrated circuit structure 900A as shown in FIG. 9C.

佈局900包括第十組金屬化層模型Group_10，堆疊在第十組金屬化層模型Group_10上的第十一組金屬化層模型Group_11，以及堆疊在第十一組金屬化層模型Group_11上的第十二組金屬化層模型Group_12。模型 Group_10、Group_11和Group_12定義在庫209中，並且至少在金屬化層的數量上不同。例如，模型Group_10包括一個金屬化層M1，模型Group_11包括兩個金屬化層(例如，在第一金屬化層上方的第二金屬化層M2和在第二金屬化層M2上方的第三金屬化層M3)，以及模型Group_12包括三個金屬化層(例如，在第三金屬化層M3上方的第四金屬化層M4，在第四金屬化層M4上方的第五金屬化層M5和在第五金屬化層M5上方的第六金屬化層M6)。 The layout 900 includes the tenth group of metallization layer models Group_10, the eleventh group of metallization layer models Group_11 stacked on the tenth group of metallization layer models Group_10, and the tenth group of metallization layer models stacked on the eleventh group of metallization layer models Group_11 Two groups of metallization layer models Group_12. Model Group_10, Group_11 and Group_12 are defined in library 209 and differ at least in the number of metallization layers. For example, model Group_10 includes one metallization layer M1 and model Group_11 includes two metallization layers (e.g., a second metallization layer M2 above the first metallization layer and a third metallization layer above the second metallization layer M2 layer M3), and the model Group_12 includes three metallization layers (for example, the fourth metallization layer M4 above the third metallization layer M3, the fifth metallization layer M5 above the fourth metallization layer M4 and the second metallization layer The sixth metallization layer M6 above the fifth metallization layer M5).

金屬化層M1至M6包括水平互連(例如，水平或橫向地延伸的金屬線911至916)，以及相應的垂直互連(例如，分別垂直地延伸的金屬通孔921至926)。金屬線911、913和915沿著第一方向(例如，如第9A圖的立體圖所示的X方向)延伸，並且沿著第二方向(例如，如第9A圖的立體圖所示的Y方向)彼此間隔開。金屬線912、914和916沿著第二方向(如第9A圖所示的Y方向)延伸並且沿著第一方向(如第9A圖所示的X方向)彼此間隔開。因此，金屬線911、913和915的長度方向垂直於金屬線912、914和916的長度方向。 Metallization layers M1 to M6 include horizontal interconnects (eg, metal lines 911 to 916 extending horizontally or laterally), and corresponding vertical interconnects (eg, metal vias 921 to 926 extending vertically, respectively). The metal lines 911, 913, and 915 extend along a first direction (for example, the X direction as shown in the perspective view of FIG. 9A ), and along a second direction (for example, the Y direction as shown in the perspective view of FIG. 9A ). spaced apart from each other. Metal lines 912, 914, and 916 extend along a second direction (Y direction as shown in FIG. 9A) and are spaced apart from each other along a first direction (X direction as shown in FIG. 9A). Therefore, the length direction of the metal lines 911 , 913 and 915 is perpendicular to the length direction of the metal lines 912 , 914 and 916 .

金屬線911、913、915具有在Y方向上測量之對應的線寬W91、W93、W95和在Z方向上測量之對應的線高H91、H93、H95，並且以在Y方向上測量之對應的線至線間距S91、S93、S95配置。金屬線912、914、916具有在X方向上測量之對應的線寬W92、W94、W96 和在Z方向上測量之對應的線高H92、H94、H96，並且以在X方向上測量之對應的線至線間距S92、S94、S96配置。作為示例而非限制，金屬線911至916的線寬可以滿足關係式W94=W95=W96<W92<W91=W93，金屬線911至916的線至線間距可以滿足關係式S94=S95=S96<S92<S91=S93，金屬線911至916的線高可以滿足關係式H94=H95=H96=H92<H91=H93或H94=H95=H96<H92<H91=H93。 The metal lines 911, 913, 915 have corresponding line widths W91, W93, W95 measured in the Y direction and corresponding line heights H91, H93, H95 measured in the Z direction, and have corresponding line heights H91, H93, H95 measured in the Y direction. Line-to-line spacing S91, S93, S95 configuration. Metal lines 912, 914, 916 have corresponding line widths W92, W94, W96 measured in the X direction and corresponding line heights H92, H94, H96 measured in the Z direction, and arranged with corresponding line-to-line spacings S92, S94, S96 measured in the X direction. As an example and not a limitation, the line width of the metal lines 911 to 916 can satisfy the relationship W94=W95=W96<W92<W91=W93, and the line-to-line spacing of the metal lines 911 to 916 can satisfy the relationship S94=S95=S96< S92<S91=S93, the wire heights of the metal wires 911 to 916 can satisfy the relationship H94=H95=H96=H92<H91=H93 or H94=H95=H96<H92<H91=H93.

因為金屬線913的線寬W93大於在金屬線913上方的金屬線914的線寬W94，所以金屬線913的電阻小於金屬線914的電阻。以此方式，可以在金屬化層M3上佈線較長的電路網(即，金屬線總長度較長的電路網)，以減小較長的電路網的電阻，並且可以在金屬化層M4上佈線較短的電路網(即，金屬線總長度較短的電路網)。 Since the line width W93 of the metal line 913 is greater than the line width W94 of the metal line 914 above the metal line 913 , the resistance of the metal line 913 is smaller than that of the metal line 914 . In this way, longer circuit nets (that is, circuit nets with a longer total length of metal lines) can be routed on the metallization layer M3 to reduce the resistance of the longer circuit nets, and can be routed on the metallization layer M4 Nets with shorter wiring (i.e., nets with shorter overall wire lengths).

第9C圖是根據本公開的部分實施例使用佈局900製造的積體電路結構900A的剖面圖，因此，積體電路結構900A繼承了佈局900中那些圖案的幾何形狀比例(如下面更多詳細的訊息)。如第1圖所示，可以在製造流程100的步驟122中在製造廠中製造積體電路結構900A。積體電路結構900A是用於促進本公開說明的非限制性示例。 FIG. 9C is a cross-sectional view of an integrated circuit structure 900A fabricated using layout 900 in accordance with some embodiments of the present disclosure. Thus, integrated circuit structure 900A inherits the geometrical proportions of those patterns in layout 900 (as described in more detail below). message). As shown in FIG. 1 , integrated circuit structure 900A may be fabricated in a fab in step 122 of fabrication process 100 . Integrated circuit structure 900A is a non-limiting example used to facilitate the description of the present disclosure.

積體電路結構900A包括可以為鰭式場效應電晶體的元件902A，其包括從基板901A突出並具有被淺溝槽隔離區域905A橫向地圍繞其下部的鰭片903A，形成 在鰭片903A中的源極/汲極區域904A，橫向地在源極/汲極區域904A之間的高介電常數金屬閘極閘極結構，以及在閘極結構906A的相對側壁上的閘極間隔物907A。基板901A、鰭片903A、源極/汲極區域904A、淺溝槽隔離區域905A、閘極結構906A和閘極間隔物907A的示例材料和製造與先前關於第3C圖所討論之鰭式場效應電晶體302A的示例材料和製造相似，因此，為了簡潔起見不再重複。 The integrated circuit structure 900A includes an element 902A, which may be a FinFET, including a fin 903A protruding from a substrate 901A and having a lower portion laterally surrounded by a shallow trench isolation region 905A, forming Source/drain regions 904A in fins 903A, high-k metal gate structures laterally between source/drain regions 904A, and gates on opposing sidewalls of gate structures 906A pole spacer 907A. The example materials and fabrication of substrate 901A, fins 903A, source/drain regions 904A, shallow trench isolation regions 905A, gate structures 906A, and gate spacers 907A are similar to the FinFETs previously discussed with respect to FIG. 3C. Example materials and fabrication for crystal 302A are similar and, therefore, not repeated for brevity.

積體電路結構900A還包括在鰭式場效應電晶體902A上方的層間介電層941A，以及延伸穿過層間介電層941A以到達鰭式場效應電晶體902A的閘極結構906A和/或源極/汲極區域904A的接觸件908A。層間介電層941A和接觸件908A的示例性材料和製造與先前關於第3C圖所討論的層間介電層341A和接觸件308A的示例性材料和製造相似，因此，為了簡潔起見不再重複。 The integrated circuit structure 900A also includes an interlayer dielectric layer 941A over the FinFET 902A, and a gate structure 906A and/or source/ Contact 908A of drain region 904A. Exemplary materials and fabrication of interlayer dielectric layer 941A and contacts 908A are similar to those of interlayer dielectric layer 341A and contacts 308A discussed previously with respect to FIG. .

積體電路結構900A還包括互連結構930A，此互連結構包括使用第9A圖所示的佈局900的金屬化層M1至M6的佈局圖案製造的複數個金屬化層M1A至M6A，並且因此金屬化層M1A至M6A繼承佈局900中的金屬化層M1至M6的佈局圖案的幾何形狀比例。金屬化層M1A至M6A分別地包括金屬間介電層951A至956A和961A至966A。金屬間介電層961A至966A形成在相應的金屬間介電層951A至956A之上。金屬化層M1A至M6A包括水平互連(例如，分別在金屬間介電 層961A至966A中水平或橫向地延伸的金屬線911A至916A)，以及垂直互連(例如，分別地在金屬間介電層951A至956A中垂直地延伸的金屬通孔921A至926A)。積體電路結構900A的金屬化層M1A至M6A的示例材料和製造與先前關於第3C圖所討論的積體電路結構300A的示例性材料和製造相似，因此，為了簡潔起見不再重複。金屬線911A至916A和金屬通孔921A至926A具有與佈局900中相應的金屬線911至916和金屬通孔921至926相同的幾何形狀比例，因此，為了簡潔起見不再重複。 The integrated circuit structure 900A also includes an interconnect structure 930A comprising a plurality of metallization layers M1A to M6A fabricated using the layout pattern of the metallization layers M1 to M6 of the layout 900 shown in FIG. Metallization layers M1A through M6A inherit the geometrical proportions of the layout pattern of metallization layers M1 through M6 in layout 900 . Metallization layers M1A-M6A include intermetal dielectric layers 951A-956A and 961A-966A, respectively. Intermetal dielectric layers 961A to 966A are formed over corresponding intermetal dielectric layers 951A to 956A. Metallization layers M1A to M6A include horizontal interconnects (eg, intermetal dielectric metal lines 911A-916A extending horizontally or laterally in layers 961A-966A), and vertical interconnects (eg, metal vias 921A-926A extending vertically in intermetal dielectric layers 951A-956A, respectively). The example materials and fabrication of the metallization layers M1A-M6A of the integrated circuit structure 900A are similar to the example materials and fabrication of the integrated circuit structure 300A discussed previously with respect to FIG. 3C and, therefore, are not repeated for brevity. Metal lines 911A-916A and metal vias 921A-926A have the same geometrical proportions as corresponding metal lines 911-916 and metal vias 921-926 in layout 900 and, therefore, are not repeated for brevity.

第10A圖是在本公開的部分實施例中包括群組化的金屬層之更多示例性模型的佈局1000的立體圖。第10B圖是繪示第10A圖的佈局中金屬化層之間的金屬線寬度差異的示意圖。佈局1000可用於製造如第10C圖所示的積體電路結構1000A。 FIG. 10A is a perspective view of a layout 1000 of more exemplary models including grouped metal layers in some embodiments of the present disclosure. FIG. 10B is a schematic diagram illustrating the difference in metal line width between metallization layers in the layout of FIG. 10A. Layout 1000 may be used to fabricate integrated circuit structure 1000A as shown in FIG. 10C.

佈局1000包括依序堆疊的第十三組、第十四組、第十五組、第十六組和第十七組金屬化層模型Group_13、Group_14、Group_15、Group_16和Group_17。模型Group_13包括第一金屬化層M1和在第一金屬化層M1上方的第二金屬化層M2。模型Group_14包括在第二金屬化層M2之上的第三金屬化層M3和在第三金屬化層M3之上的第四金屬化層M4。模型Group_15包括在第四金屬化層M4上方的第五金屬化層M5和在第五金屬化層M5上方的第六金屬化層M6。模型Group_16僅包括在第六金屬化層M6上方的第七金屬化層M7，模型 Group_17僅包括在第七金屬化層M7上方的第八金屬化層M8。 The layout 1000 includes a thirteenth group, a fourteenth group, a fifteenth group, a sixteenth group and a seventeenth group of metallization layer models Group_13 , Group_14 , Group_15 , Group_16 and Group_17 stacked in sequence. Model Group_13 includes a first metallization layer M1 and a second metallization layer M2 above the first metallization layer M1 . Model Group_14 includes a third metallization layer M3 on top of the second metallization layer M2 and a fourth metallization layer M4 on top of the third metallization layer M3. Model Group_15 includes a fifth metallization layer M5 above the fourth metallization layer M4 and a sixth metallization layer M6 above the fifth metallization layer M5. Model Group_16 includes only the seventh metallization layer M7 above the sixth metallization layer M6, the model Group_17 includes only the eighth metallization layer M8 above the seventh metallization layer M7.

金屬化層M1至M8包括水平互連(例如，水平或橫向地延伸的金屬線1011至1018)，以及相應的垂直互連(例如，分別垂直地延伸的金屬通孔1021至1028)。金屬線1011、1013、1015、1017沿著第一方向(例如，如第10A圖的立體圖所示的X方向)延伸，並且沿著第二方向(例如，如第10A圖的立體圖所示的Y方向)彼此間隔開。金屬線1012、1014、1016、1018沿著第二方向(如第10A圖所示的Y方向)延伸並且沿著第一方向(如第10A圖所示的X方向)彼此間隔開。因此，金屬線1011、1013、1015、1017的長度方向垂直於金屬線1012、1014、1016、1018的長度方向。 Metallization layers M1 to M8 include horizontal interconnects (eg, metal lines 1011 to 1018 extending horizontally or laterally), and corresponding vertical interconnects (eg, metal vias 1021 to 1028 extending vertically, respectively). The metal lines 1011, 1013, 1015, 1017 extend along a first direction (for example, the X direction as shown in the perspective view of FIG. 10A), and along a second direction (for example, the Y direction as shown in the perspective view of FIG. direction) are spaced apart from each other. Metal lines 1012 , 1014 , 1016 , 1018 extend along a second direction (Y direction as shown in FIG. 10A ) and are spaced apart from each other along a first direction (X direction as shown in FIG. 10A ). Therefore, the length direction of the metal lines 1011 , 1013 , 1015 , 1017 is perpendicular to the length direction of the metal lines 1012 , 1014 , 1016 , 1018 .

金屬線1011、1013、1015、1017具有在Y方向上測量之對應的線寬W101、W103、W105、W107和在Z方向上測量之對應的線高H101、H103、H105、H107，並且以在Y方向測量之對應的線至線間距S101、S103、S105、S107配置。金屬線1012、1014、1016、1018具有在X方向上測量之相應的線寬W102、W104、W106、W108和在Z方向上測量之對應的線高H102、H104、H106、H108，並以在X方向上測量之線至線間距S102、S104、S106、S108配置。作為示例而非限制，金屬線1011至1018的線寬可以滿足以下關係式W103=W105=W108<W104=W107<W101=W102= W106，金屬線1011至1018的線至線間距可以滿足關係S103=S105=S108<S104=S107<S101=S102=S106，金屬線1011至1018的線高可以滿足關係式H103=H105=H108=H104=H107<H101=H102=H106或H103=H105=H108<H104=H107<H101=H102=H106。 The metal lines 1011, 1013, 1015, 1017 have corresponding line widths W101, W103, W105, W107 measured in the Y direction and corresponding line heights H101, H103, H105, H107 measured in the Z direction, and are measured in the Y direction The corresponding line-to-line spacing S101 , S103 , S105 , and S107 are configured for direction measurement. The metal lines 1012, 1014, 1016, 1018 have corresponding line widths W102, W104, W106, W108 measured in the X direction and corresponding line heights H102, H104, H106, H108 measured in the Z direction, and are measured in the X direction. S102, S104, S106, S108 configuration of the line-to-line spacing measured in the direction. As an example and not limitation, the line widths of the metal lines 1011 to 1018 may satisfy the following relationship W103=W105=W108<W104=W107<W101=W102= W106, the line-to-line spacing of the metal lines 1011 to 1018 can satisfy the relationship S103=S105=S108<S104=S107<S101=S102=S106, the line height of the metal lines 1011 to 1018 can satisfy the relationship H103=H105=H108=H104 =H107<H101=H102=H106 or H103=H105=H108<H104=H107<H101=H102=H106.

第10C圖是根據本公開的部分實施例使用佈局1000製造的積體電路結構1000A的剖面圖，因此，積體電路結構1000A繼承了佈局1000中那些圖案的幾何形狀比例(如下面更多詳細的訊息)。如第1圖所示，可以在製造流程100的步驟122在製造廠中製造積體電路結構1000A。積體電路結構1000A是用於促進本公開說明的非限制性示例。 FIG. 10C is a cross-sectional view of an integrated circuit structure 1000A fabricated using layout 1000 in accordance with some embodiments of the present disclosure. Thus, integrated circuit structure 1000A inherits the geometrical proportions of those patterns in layout 1000 (as described in more detail below). message). As shown in FIG. 1 , integrated circuit structure 1000A may be fabricated in a fab at step 122 of fabrication process 100 . Integrated circuit structure 1000A is a non-limiting example used to facilitate the description of the present disclosure.

積體電路結構1000A包括可以是鰭式場效應電晶體的元件1002A，其包括從基板1001A突出並具有由淺溝槽隔離區域1005A橫向地圍繞其下部的鰭片1003A，形成在鰭片1003A中的源極/汲極區域1004A，橫向地在源極/汲極區域1004A之間的高介電常數金屬閘極閘極結構1006A，以及在閘極結構1006A的相對側壁上的閘極間隔物1007A。基板1001A、鰭片1003A、源極/汲極區域1004A、淺溝槽隔離區域1005A、閘極結構1006A和閘極間隔物1007A的示例材料和製造與先前關於第3C圖所討論的鰭式場效應電晶體302A的示例材料和製造相似，因此，為了簡潔起見不再重複。 The integrated circuit structure 1000A includes an element 1002A, which may be a FinFET, including a fin 1003A protruding from a substrate 1001A and having a lower portion laterally surrounded by a shallow trench isolation region 1005A, in which a source electrode/drain regions 1004A, a high-k metal gate gate structure 1006A laterally between the source/drain regions 1004A, and gate spacers 1007A on opposing sidewalls of the gate structure 1006A. The example materials and fabrication of substrate 1001A, fins 1003A, source/drain regions 1004A, shallow trench isolation regions 1005A, gate structures 1006A, and gate spacers 1007A are similar to the FinFETs previously discussed with respect to FIG. 3C. Example materials and fabrication for crystal 302A are similar and, therefore, not repeated for brevity.

積體電路結構1000A還包括在鰭式場效應電晶體1002A上方的層間介電層1041A，以及延伸穿過層間介電層1041A以到達鰭式場效應電晶體1002A的閘極結構1006A和/或源極/汲極區域1004A的接觸件1008A。層間介電層1041A和接觸件1008A的示例性材料和製造與先前關於第3C圖所討論的層間介電層341A和接觸件308A的材料和製造類似，因此，為了簡潔起見不再重複。 The integrated circuit structure 1000A also includes an interlayer dielectric layer 1041A over the FinFET 1002A, and a gate structure 1006A and/or source/ Contact 1008A of drain region 1004A. Exemplary materials and fabrication of interlayer dielectric layer 1041A and contacts 1008A are similar to materials and fabrication of interlayer dielectric layer 341A and contacts 308A discussed previously with respect to FIG. 3C and, therefore, are not repeated for brevity.

積體電路結構1000A還包括互連結構1030A，此互連結構1030A包括複數個金屬化層M1A至M8A，其使用如第10A圖所示的佈局1000的金屬化層M1至M8的佈局圖案製造，因此，金屬化層M1A至M8A繼承佈局1000中的金屬化層M1至M8的佈局圖案的幾何形狀比例。金屬化層M1A至M8A分別地包括金屬間介電層1051A至1058A和1061A至1068A。金屬間介電層1061A至1068A形成在相應的金屬間介電層1051A至1058A之上。金屬化層M1A至M8A包括水平互連(例如，分別在金屬間介電層1061A至1068A中水平或橫向地延伸的金屬線1011A至1018A)，以及垂直互連(例如，分別在金屬間介電層1051A至1058A中垂直地延伸的金屬通孔1021A至1028A)。積體電路結構1000A的金屬化層M1A至M8A的示例材料和製造與先前關於第3C圖所討論的積體電路結構300A的示例材料和製造相似，因此，為了簡潔起見不再重複。金屬線1011A至1018A和金屬通孔1021A至1028A具有與佈局1000 中相應的金屬線1011至1018和金屬通孔1021至1028相同的幾何形狀比例，因此，為了簡潔起見不再重複。 The integrated circuit structure 1000A also includes an interconnect structure 1030A comprising a plurality of metallization layers M1A to M8A fabricated using the layout pattern of the metallization layers M1 to M8 of the layout 1000 shown in FIG. 10A, Accordingly, metallization layers M1A through M8A inherit the geometrical proportions of the layout patterns of metallization layers M1 through M8 in layout 1000 . Metallization layers M1A to M8A include intermetal dielectric layers 1051A to 1058A and 1061A to 1068A, respectively. IMD layers 1061A to 1068A are formed over corresponding IMD layers 1051A to 1058A. Metallization layers M1A to M8A include horizontal interconnects (eg, metal lines 1011A to 1018A extending horizontally or laterally in IMD layers 1061A to 1068A, respectively), and vertical interconnects (eg, metal lines 1011A to 1018A in IMD layers 1061A to 1068A, respectively). Vertically extending metal vias 1021A-1028A in layers 1051A-1058A). The example materials and fabrication of the metallization layers M1A-M8A of the integrated circuit structure 1000A are similar to the example materials and fabrication of the integrated circuit structure 300A previously discussed with respect to FIG. 3C and, therefore, are not repeated for brevity. Metal lines 1011A to 1018A and metal vias 1021A to 1028A have layout 1000 with The geometric proportions of the corresponding metal lines 1011 to 1018 and metal vias 1021 to 1028 are the same, and therefore, are not repeated for the sake of brevity.

第11圖是繪示根據本公開的部分實施例，自動擺置和佈線功能的一部分的流程圖。在程序1101中，首先從庫208(如第2圖所示)中選擇群組化的金屬化層中的一個或複數個模型並將其擺置在佈局中。作為示例而非限制，選擇模型Group_1和Group_2並將其擺置在佈局中以構建如第3A圖所示的佈局300。 FIG. 11 is a flowchart illustrating a portion of an automatic placement and routing function according to some embodiments of the present disclosure. In procedure 1101, one or more patterns in the grouped metallization layers are first selected from the library 208 (shown in FIG. 2) and placed in a layout. By way of example and not limitation, models Group_1 and Group_2 are selected and placed in a layout to build a layout 300 as shown in Figure 3A.

在程序1102中，檢查從程序1101生成的佈局，以決定此佈局是否滿足合格的電路相關特性(例如，寄生電阻和電容)、製造標準和/或設計規範。如果檢查結果不理想，則自動擺置和佈線功能進行到程序1103，以從庫208中選擇一個或複數個其他模型來替換最初選擇的模型。作為示例而非限制，可以將初始選擇的模型Group_1和Group_2替換為模型Group_3、Group_4和Group_5，從而得到如第5A圖所示的佈局500。然後，在程序1102中再次檢查從程序1103產生之重組的佈局。如果檢查結果可接受，則在程序1104中完成自動擺置和佈線功能，並由此生成佈局和佈線。 In procedure 1102, the layout generated from procedure 1101 is checked to determine whether the layout meets acceptable circuit-related characteristics (eg, parasitic resistance and capacitance), manufacturing standards, and/or design specifications. If the check result is unsatisfactory, the automatic placement and routing function proceeds to program 1103 to select one or more other models from the library 208 to replace the initially selected model. As an example and not limitation, the initially selected models Group_1 and Group_2 may be replaced with models Group_3, Group_4 and Group_5, resulting in a layout 500 as shown in FIG. 5A. Then, the reorganized layout generated from procedure 1103 is checked again in procedure 1102 . If the inspection result is acceptable, the automatic placement and routing function is completed in program 1104, and placement and routing are generated accordingly.

第12圖是根據部分實施例的電子設計自動化(electronic design automation,EDA)系統1200的示意圖。根據部分實施例，可使用諸如電子設計自動化系統1200來實現本公開所述之生成設計佈局(例如，佈局300、400、500、600、700、800、900和/或1000) 的方法。在部分實施例中，電子設計自動化系統1200是通用電腦裝置，其包括硬體處理器1202和非暫態電腦可讀取儲存媒體(non-transitory,computer-readable storage medium)1204。除此之外，電腦可讀取儲存媒體1204被編碼(即，儲存)可執行的指令1206集、設計佈局1207、設計規則檢查(design rule check,DRC)平台1209或用於執行指令集的任何中間數據。每個設計佈局1207包括積體晶片的圖形表示(例如，GSII文件)。每個設計規則檢查平台1209包括特定用於製造設計佈局1207而選擇的半導體製程之設計規則的列表。由硬體處理器1202執行的指令1206、設計佈局1207和設計規則檢查平台1209(至少部分地)代表根據一個或複數個實現本公開描述的方法(以下稱為所提到的過程和/或方法)的電子設計自動化工具。 FIG. 12 is a schematic diagram of an electronic design automation (EDA) system 1200 according to some embodiments. According to some embodiments, generating design layouts (e.g., layouts 300, 400, 500, 600, 700, 800, 900, and/or 1000) described in this disclosure may be implemented using, for example, electronic design automation system 1200 Methods. In some embodiments, the electronic design automation system 1200 is a general-purpose computer device, which includes a hardware processor 1202 and a non-transitory, computer-readable storage medium (non-transitory, computer-readable storage medium) 1204 . In addition, the computer-readable storage medium 1204 encodes (i.e., stores) an executable instruction set 1206, a design layout 1207, a design rule check (DRC) platform 1209, or any other means for executing the instruction set. intermediate data. Each design layout 1207 includes a graphical representation (eg, a GSII file) of the bulk wafer. Each design rule checking platform 1209 includes a list of design rules specific to the semiconductor process selected for manufacturing design layout 1207 . The instructions 1206 executed by the hardware processor 1202, the design layout 1207, and the design rule checking platform 1209 represent (at least in part) implementations according to one or more of the methods described in this disclosure (hereinafter referred to as the mentioned processes and/or methods) ) electronic design automation tool.

處理器1202透過匯流排1208電耦合到電腦可讀取儲存媒體1204。處理器1202還透過匯流排1208電耦合到輸入/輸出(I/O)介面1210。網路介面1212也透過匯流排1208電耦合到處理器1202。網路介面1212連接到網路1214，以便處理器1202和電腦可讀取儲存媒體1204能夠透過網路1214連接到外部元素。為了使電子設計自動化系統1200可用於執行如第1圖所示之流程100的部分或全部的程序步驟102至118，處理器1202用以執行編碼在電腦可讀取儲存媒體1204中的指令1206。例如，處理器1202用以執行以下步驟：提供設計規範、生 成電路網表、執行佈局前模擬、生成佈局的設計數據、在庫中定義群組化的金屬化層的模型、進行佈局和佈線程序以生成佈局、執行佈局後模擬並驗證佈局後模擬結果。在一個或複數個實施例中、處理器1202是中央處理器(central processing unit,CPU)、多處理器、分佈式處理系統、特殊應用積體電路(application specific integrated circuit,ASIC)和/或合適的製程元件。 The processor 1202 is electrically coupled to the computer readable storage medium 1204 through the bus bar 1208 . The processor 1202 is also electrically coupled to an input/output (I/O) interface 1210 through a bus bar 1208 . Network interface 1212 is also electrically coupled to processor 1202 through bus 1208 . The network interface 1212 is connected to the network 1214 so that the processor 1202 and the computer-readable storage medium 1204 can be connected to external elements through the network 1214 . In order for the EDA system 1200 to be used to execute part or all of the program steps 102 to 118 of the process 100 shown in FIG. For example, the processor 1202 is configured to perform the following steps: providing design specifications, producing Create a circuit netlist, perform pre-layout simulations, generate design data for placement, define models of grouped metallization layers in libraries, perform place and route procedures to generate placement, perform post-placement simulations, and verify post-placement simulation results. In one or more embodiments, the processor 1202 is a central processing unit (central processing unit, CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (application specific integrated circuit, ASIC) and/or a suitable process components.

在一個或複數個實施例中，電腦可讀取儲存媒體1204是電的、磁的、光的、電磁的、紅外的和/或半導體的系統(或裝置或設備)。例如，電腦可讀取儲存媒體1204包括半導體或固態記憶體、磁帶、可移動電腦磁碟、隨機存取記憶體(random access memory,RAM)、唯讀記憶體(read-only memory,ROM)、剛性磁碟和/或光碟。在使用光碟的一個或多個實施例中，電腦可讀取儲存媒體1204包括唯讀光碟(compact disk-read only memory,CD-ROM)、讀/寫光碟(CD-R/W)和/或數位影音光碟(digital video disc,DVD)。 In one or more embodiments, the computer-readable storage medium 1204 is an electrical, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or device or device). For example, the computer-readable storage medium 1204 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (random access memory, RAM), read-only memory (read-only memory, ROM), Rigid disks and/or optical disks. In one or more embodiments using optical discs, the computer-readable storage medium 1204 includes compact disc-read only memory (CD-ROM), compact disc-read/write (CD-R/W), and/or Digital video disc (digital video disc, DVD).

在一個或複數個實施例中，電腦可讀取儲存媒體1204儲存指令1206、設計佈局1207(例如，之前討論的佈局300、400、500、600、700、800、900和1000)、設計規則檢查平台1209，以用以使電子設計自動化系統1200(其中這樣的執行(至少部分地)表示電子設計自動化工具)可執行所提到的製程和/或方法的一部分或全部。在一個或複數個實施例中，儲存媒體1204還儲存有助於 執行如第1圖所示的流程100之部分或全部的程序步驟102至118的訊息。例如，儲存媒體1204可以儲存在自動擺置和佈線程序中使用之群組化的金屬化層模型(例如，前面討論的模型Group_1至Group_17)。 In one or more embodiments, computer-readable storage medium 1204 stores instructions 1206, design layouts 1207 (e.g., layouts 300, 400, 500, 600, 700, 800, 900, and 1000 previously discussed), design rule checking A platform 1209 for enabling the EDA system 1200 (where such execution (at least in part) denotes an EDA tool) to perform part or all of the mentioned processes and/or methods. In one or more embodiments, storage medium 1204 also stores Execute the message of part or all of the program steps 102 to 118 of the process 100 shown in FIG. 1 . For example, the storage medium 1204 may store grouped metallization layer models (eg, models Group_1 to Group_17 discussed above) used in automatic place and route programs.

電子設計自動化系統1200包括I/O介面1210。I/O介面1210耦合到外部電路。在一個或複數個實施例中，I/O介面1210包括鍵盤、小鍵盤、鼠標、軌跡球、觸控板、觸摸屏和/或光標方向鍵，以用於將訊息和指令傳達給處理器1202。 The EDA system 1200 includes an I/O interface 1210 . The I/O interface 1210 is coupled to external circuitry. In one or more embodiments, the I/O interface 1210 includes a keyboard, keypad, mouse, trackball, touchpad, touch screen, and/or cursor direction keys for communicating information and instructions to the processor 1202 .

電子設計自動化系統1200還包括耦合到處理器1202的網路介面1212。網路介面1212允許電子設計自動化系統1200與一個或複數個其他電腦系統連接到的網路1214通訊。網路介面1212包括無線網路介面(例如，藍牙(BLUETOOTH)、無線網路(WIFI)、全球互通微波存取(WIMAX)、通用封包無線服務(GPRS)或寬頻分碼多重進接(WCDMA))；或有線網路介面(例如，乙太網路(ETHERNET)、通用序列匯流排(USB)或IEEE-131212)。在一個或複數個實施例中，在兩個或更多個電子設計自動化系統1200中執行所述過程和/或方法的一部分或全部。 EDA system 1200 also includes a network interface 1212 coupled to processor 1202 . Network interface 1212 allows EDA system 1200 to communicate with network 1214 to which one or more other computer systems are connected. The network interface 1212 includes a wireless network interface (for example, Bluetooth (BLUETOOTH), wireless network (WIFI), Worldwide Interoperability for Microwave Access (WIMAX), General Packet Radio Service (GPRS) or Wideband Code Division Multiple Access (WCDMA) ); or a wired network interface (eg, Ethernet (ETHERNET), Universal Serial Bus (USB) or IEEE-131212). In one or more embodiments, some or all of the processes and/or methods are performed in two or more electronic design automation systems 1200 .

將電子設計自動化系統1200配置為透過I/O介面1210接收訊息。透過I/O介面1210接收的訊息包括指令、數據、設計規則、標準元件庫和/或其他參數中的一個或複數個，以供處理器1202處理。訊息經匯流排1208 傳輸到處理器1202。將電子設計自動化系統1200配置為透過I/O介面1210接收與使用者界面(userinterface,UI)1216有關的訊息。此訊息儲存在電腦可讀取媒體1204中作為使用者介面1216。 The EDA system 1200 is configured to receive messages through the I/O interface 1210 . The information received through the I/O interface 1210 includes one or more of commands, data, design rules, standard component libraries, and/or other parameters for processing by the processor 1202 . Message via bus 1208 Transfer to processor 1202. The EDA system 1200 is configured to receive information related to a user interface (UI) 1216 through an I/O interface 1210 . This information is stored on computer readable medium 1204 as user interface 1216 .

在部分實施例中，可以使用諸如從CADENCE DESIGN SYSTEMS公司獲得的VIRTUOSO®工具或另一種合適的佈局生成工具來產生包括標準元件的佈局圖。 In some embodiments, a layout diagram including standard components may be generated using a tool such as the VIRTUOSO® tool available from CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool.

在部分實施例中，這些過程被實現為儲存在非暫態電腦可讀取記錄媒體中的程式的功能。非暫態電腦可讀取記錄媒體的示例包括但不限於外部/可移除和/或內部/內置儲存或記憶體元件(例如，光碟(例如，數位影音光碟)、磁碟(例如，硬碟)、半導體記憶體(例如，唯讀記憶體、隨機存取記憶體、記憶卡等)中的一個或多個)。 In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external/removable and/or internal/built-in storage or memory elements (e.g., optical discs (e.g., DVD), magnetic disks (e.g., hard disk ), semiconductor memory (for example, read-only memory, random access memory, memory card, etc.) in one or more).

在第12圖中還繪示遮罩室1230，其透過諸如網路1214從電子設計自動化系統1200接收經驗證的佈局。遮罩室1230具有遮罩製造工具1232(例如，遮罩寫入器)，以基於由電子設計自動化系統1200產生之經驗證的佈局製造一個或複數個光罩(例如，用於製造諸如積體電路300A、400A、500A、600A、700A、800A、900A和/或1000A的光罩)。積體電路製造商1220可以透過諸如網路1214連接到遮罩室1230和電子設計自動化系統1200。積體電路製造商1220包括積體電路製造工具1222，以使用由遮罩室1230製造的光罩製造積體電路晶 片(例如，積體電路300A、400A、500A、600A、700A、800A、900A和/或1000A)。作為示例而非限制，積體電路製造工具1222可以是用於製造積體電路晶片的集結式加工機台(cluster tool)。集結式加工機台可以是多反應室型複合裝置，包括：在其中心處插入有晶片處理機器人的多面體傳輸室；位在多面體傳輸室的每個壁面上的多個處理室(例如，化學氣相沉積室、物理氣相沉積室、蝕刻室、退火室等)；以及安裝在傳輸室的另一壁面上的樣品傳送室(loadlock chamber)。 Also shown in FIG. 12 is a mask room 1230 that receives a verified layout from the EDA system 1200 over, for example, the network 1214 . The mask chamber 1230 has a mask fabrication tool 1232 (e.g., a mask writer) to fabricate one or more reticles based on a verified layout generated by the EDA system 1200 (e.g., for fabricating reticle for circuits 300A, 400A, 500A, 600A, 700A, 800A, 900A, and/or 1000A). IC manufacturer 1220 may be connected to mask house 1230 and EDA system 1200 via, for example, network 1214 . The IC manufacturer 1220 includes an IC fabrication tool 1222 to fabricate IC wafers using reticles fabricated by the mask house 1230. chip (eg, integrated circuit 300A, 400A, 500A, 600A, 700A, 800A, 900A, and/or 1000A). By way of example and not limitation, the integrated circuit fabrication tool 1222 may be a cluster tool for fabricating integrated circuit wafers. The hub may be a multi-chamber compound device comprising: a polyhedral transfer chamber with a wafer processing robot inserted at its center; a plurality of processing chambers (e.g., chemical gas phase deposition chamber, physical vapor deposition chamber, etching chamber, annealing chamber, etc.); and a sample transfer chamber (loadlock chamber) installed on the other wall of the transfer chamber.

在部分實施例中，電子設計自動化系統1200、遮罩室1230和積體電路製造商1220中的兩個或更多個由單個公司擁有。例如，電子設計自動化系統1200、遮罩室1230和積體電路製造商1220中的兩個或更多個在公共設施中共存並使用公共資源。在部份其他實施例中，電子設計自動化系統1200由設計室擁有，此設計室是與遮罩室1230和積體電路製造商1220不同的企業。在這樣的實施例中，遮罩室1230、積體電路製造商1220和設計室各自擁有與一個或多個其他企業進行交互的電子設計自動化系統1200，並向一個或多個其他企業提供服務和/或從其接收服務。 In some embodiments, two or more of electronic design automation system 1200, mask house 1230, and integrated circuit manufacturer 1220 are owned by a single company. For example, two or more of electronic design automation system 1200, mask house 1230, and integrated circuit manufacturer 1220 coexist in a common facility and use common resources. In some other embodiments, EDA system 1200 is owned by a design house that is a different enterprise than mask house 1230 and IC manufacturer 1220 . In such an embodiment, mask house 1230, integrated circuit manufacturer 1220, and design house each own electronic design automation system 1200 that interacts with and provides services and services to one or more other businesses. / or receive services from it.

基於以上討論，可以看出本公開提供了益處。然而，應當理解，其他實施例可以提供附加的益處，並且在本文中不必公開所有益處，並且對於所有實施例都不需要特定的益處。其中一個益處是，對於群組化的金屬化層，佈線 器可以在較低的金屬化層上使用較粗的金屬線來降低淨電阻，從而減少信號延遲。另一個益處是，因為減少了信號延遲，時脈樹合成可以在積體電路佈局中擺置較少的緩衝器，從而在最終積體電路晶片中減少了緩衝器，因而可以進一步等比例縮小晶片面積。 Based on the above discussion, it can be seen that the present disclosure provides benefits. It should be understood, however, that other embodiments may provide additional benefits, and not all of them are necessarily disclosed herein, and no particular benefit is required for all embodiments. One of the benefits is that, for grouped metallization layers, routing Devices can use thicker metal lines on lower metallization layers to lower net resistance and thus reduce signal delay. Another benefit is that due to the reduced signal delay, clock tree synthesis allows for fewer buffers to be placed in the IC layout, thereby reducing the number of buffers in the final IC die, thus enabling further die scaling area.

在部分實施例中，積體電路結構包括第一電晶體、第二電晶體、第三電晶體、第四電晶體、第一金屬化層和第二金屬化層。第一電晶體、第二電晶體、第三電晶體和第四電晶體形成在基板上。第一金屬化層在第一電晶體、第二電晶體、第三電晶體和第四電晶體上方。第一金屬化層具有沿第一方向橫向地延伸並且具有在垂直於第一方向的第二方向上測量的第一線寬的複數個第一金屬線。複數個第一金屬線中的一個或複數個是電連接第一電晶體和第二電晶體的第一電路網的一部分。第二金屬化層在第一金屬化層上方。第二金屬化層具有沿著第二方向橫向地延伸並具有在第一方向上測量的第二線寬的複數個第二金屬線。第二金屬線的第二線寬小於第一金屬線的第一線寬。複數個第二金屬線中的一個或複數個是電連接第三電晶體和第四電晶體的第二電路網的一部分，並且第二電路網的總長度小於第一電路網的總長度。 In some embodiments, the integrated circuit structure includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first metallization layer, and a second metallization layer. The first transistor, the second transistor, the third transistor and the fourth transistor are formed on the substrate. The first metallization layer is over the first transistor, the second transistor, the third transistor and the fourth transistor. The first metallization layer has a plurality of first metal lines extending laterally in a first direction and having a first line width measured in a second direction perpendicular to the first direction. One or more of the plurality of first metal lines is a part of the first circuit network electrically connecting the first transistor and the second transistor. The second metallization layer is over the first metallization layer. The second metallization layer has a plurality of second metal lines extending laterally along a second direction and having a second line width measured in the first direction. The second line width of the second metal line is smaller than the first line width of the first metal line. One or more of the plurality of second metal lines is a part of a second circuit network electrically connecting the third transistor and the fourth transistor, and the total length of the second circuit network is smaller than that of the first circuit network.

於部分實施例中，積體電路結構還包含一第三金屬化層，在該第一金屬化層下，該第三金屬化層具有複數個第三金屬線，該些第三金屬線沿該第二方向延伸並具有在該第一方向上測量的一第三線寬，其中該些第三金屬線的 該第三線寬小於該些第一金屬線的該第一線寬。 In some embodiments, the integrated circuit structure further includes a third metallization layer, under the first metallization layer, the third metallization layer has a plurality of third metal lines, and the third metal lines are along the The second direction extends and has a third line width measured in the first direction, wherein the third metal lines The third line width is smaller than the first line width of the first metal lines.

於部分實施例中，該些第三金屬線的該第三線寬大於該些第二金屬線的該第二線寬。 In some embodiments, the third line width of the third metal lines is greater than the second line width of the second metal lines.

於部分實施例中，積體電路結構還包含一第四金屬化層，在該第二金屬化層上，該第四金屬化層包含複數個第四金屬線，該些第四金屬線沿該第一方向延伸並具有沿該第二方向測量的一第四線寬，其中該些第四金屬線的該第四線寬小於該些第一金屬線的該第一線寬。 In some embodiments, the integrated circuit structure further includes a fourth metallization layer, on the second metallization layer, the fourth metallization layer includes a plurality of fourth metal lines, and the fourth metal lines are along the The first direction extends and has a fourth line width measured along the second direction, wherein the fourth line width of the fourth metal lines is smaller than the first line width of the first metal lines.

於部分實施例中，該些第四金屬線的該第四線寬大於該些第二金屬線的該第二線寬。 In some embodiments, the fourth line width of the fourth metal lines is larger than the second line width of the second metal lines.

於部分實施例中，該些第四金屬線的該第四線寬與該些第三金屬線的該第三線寬相同。 In some embodiments, the fourth line width of the fourth metal lines is the same as the third line width of the third metal lines.

於部分實施例中，積體電路結構還包含一第四金屬化層，在該第三金屬化層下，該第四金屬化層包含複數個第四金屬線，該些第四金屬線沿該第一方向延伸並具有沿該第二方向測量的一第四線寬，其中該些第四金屬線的該第四線寬小於該些第三金屬線的該第三線寬。 In some embodiments, the integrated circuit structure further includes a fourth metallization layer, under the third metallization layer, the fourth metallization layer includes a plurality of fourth metal lines along the The first direction extends and has a fourth line width measured along the second direction, wherein the fourth line width of the fourth metal lines is smaller than the third line width of the third metal lines.

於部分實施例中，該些第四金屬線的該第四線寬與該些第二金屬線的該第二線寬相同。 In some embodiments, the fourth line width of the fourth metal lines is the same as the second line width of the second metal lines.

於部分實施例中，積體電路結構還包含一第三金屬化層，在該第二金屬化層上，該第三金屬化層具有複數個第三金屬線，該些第三金屬線沿該第二方向延伸並具有沿該第一方向測量的一第三線寬，其中該些第三金屬線的該第三線寬大於該些第二金屬線的該第二線寬。 In some embodiments, the integrated circuit structure further includes a third metallization layer, on the second metallization layer, the third metallization layer has a plurality of third metal lines, and the third metal lines are along the The second direction extends and has a third line width measured along the first direction, wherein the third line width of the third metal lines is larger than the second line width of the second metal lines.

於部分實施例中，該些第三金屬線的該第三線寬與該些第一金屬線的該第一線寬相同。 In some embodiments, the third line width of the third metal lines is the same as the first line width of the first metal lines.

於部分實施例中，該第一電晶體、該第二電晶體、該第三電晶體和該第四電晶體是複數個鰭式場效應電晶體。 In some embodiments, the first transistor, the second transistor, the third transistor and the fourth transistor are a plurality of FinFETs.

在部分實施例中，積體電路結構包括第一電晶體、第二電晶體、第三電晶體、第四電晶體、第一金屬化層和第二金屬化層。第一金屬化層在第一電晶體、第二電晶體、第三電晶體和第四電晶體上方。第一金屬化層包括複數個第一金屬線，這些第一金屬線沿著第一方向橫向地延伸並且以第一線至線間距配置。複數個第一金屬線中的一個或多個是電連接第一電晶體和第二電晶體的第一電路網的一部分。第二金屬化層在第一金屬化層上方。第二金屬化層包括複數個第二金屬線，這些第二金屬線沿著垂直於第一方向的第二方向橫向地延伸並且以第二線至線間距配置。第一線至線間距大於第二線至線間距。複數個第二金屬線中的一個或多個是連接第三電晶體和第四電晶體的第二電路網的一部分，並且第二電路網的總長度小於第一電路網的總長度。 In some embodiments, the integrated circuit structure includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first metallization layer, and a second metallization layer. The first metallization layer is over the first transistor, the second transistor, the third transistor and the fourth transistor. The first metallization layer includes a plurality of first metal lines extending laterally along a first direction and arranged at a first line-to-line pitch. One or more of the plurality of first metal lines is a part of a first circuit network electrically connecting the first transistor and the second transistor. The second metallization layer is over the first metallization layer. The second metallization layer includes a plurality of second metal lines extending laterally along a second direction perpendicular to the first direction and arranged at a second line-to-line pitch. The first line-to-line spacing is greater than the second line-to-line spacing. One or more of the plurality of second metal lines is a part of a second circuit network connecting the third transistor and the fourth transistor, and the total length of the second circuit network is smaller than the total length of the first circuit network.

於部分實施例中，積體電路結構還包含一第三金屬化層，在該第二金屬化層上，該第三金屬化層包含複數個第三金屬線，該些第三金屬線沿該第一方向延伸並以一第三線至線間距配置，其中該第三線至線間距大於該第二線至線間距。 In some embodiments, the integrated circuit structure further includes a third metallization layer, on the second metallization layer, the third metallization layer includes a plurality of third metal lines, and the third metal lines are along the The first direction extends and is configured with a third line-to-line spacing, wherein the third line-to-line spacing is greater than the second line-to-line spacing.

於部分實施例中，該第三線至線間距與該第一線至線間距相同。 In some embodiments, the third line-to-line spacing is the same as the first line-to-line spacing.

於部分實施例中，積體電路結構還包含一第三金屬化層，在該第一金屬化層下，該第三金屬化層沿該第二方向延伸並以一第三線至線間距配置，其中該第三線至線間距小於該第一線至線間距。 In some embodiments, the integrated circuit structure further includes a third metallization layer, under the first metallization layer, the third metallization layer extends along the second direction and is arranged with a third line-to-line spacing, Wherein the third line-to-line spacing is smaller than the first line-to-line spacing.

於部分實施例中，該第三線至線間距與該第二線至線間距相同。 In some embodiments, the third line-to-line spacing is the same as the second line-to-line spacing.

在部分實施例中，一種形成積體電路結構的方法方法包括：在儲存媒體中儲存群組化的金屬化層的複數個模型；在佈局中，將複數個群組化的金屬化層模型中的第一個擺置在元件上；在佈局中，將複數個群組化的金屬化層模型中的第二個擺置在複數個群組化的金屬化層模型中的第一個之上，其中，複數個群組化的金屬化層模型中的第二個的最底部的金屬化層的線寬小於複數個群組化的金屬化層模型中的第一個的最頂部的金屬化層的線寬；在複數個群組化的金屬化層的複數個模型中的第一個的最頂部的金屬化層上至少部分地佈線第一電路網；在複數個群組化的金屬化層的複數個模型中的第二個的最底部的金屬化層上至少部分地佈線第二電路網；並基於佈局製造積體電路。第二電路網的總長度小於第一電路網的總長度。 In some embodiments, a method for forming an integrated circuit structure includes: storing a plurality of models of grouped metallization layers in a storage medium; Place the first of the grouped metallization layer models on the component; place the second of the grouped metallization layer models on top of the first of the grouped metallization layer models in the layout , wherein the line width of the bottommost metallization layer of the second of the plurality of grouped metallization layer models is smaller than the topmost metallization of the first of the plurality of grouped metallization layer models the line width of the layer; at least partially wiring the first circuit net on the topmost metallization layer of the first one of the plurality of patterns of the plurality of grouped metallization layers; in the plurality of grouped metallization layers wiring a second circuit net at least partially on a bottommost metallization layer of a second one of the plurality of patterns of layers; and fabricating an integrated circuit based on the layout. The total length of the second circuit network is smaller than the total length of the first circuit network.

於部分實施例中，該些群組化的金屬化層的該些模型中的該第一個和該第二個具有相同數量之金屬化層。 In some embodiments, the first and the second of the models of the grouped metallization layers have the same number of metallization layers.

於部分實施例中，該些群組化的金屬化層的該些模 型中的該第一個具有比該些群組化的金屬化層的該些模型中的該第二個更多的金屬化層。 In some embodiments, the modes of the grouped metallization layers The first of the models has more metallization layers than the second of the models of the grouped metallization layers.

於部分實施例中，該些群組化的金屬化層的該些模型中的該第一個具有比該些群組化的金屬化層的該些模型中的該第二個更少的金屬化層。 In some embodiments, the first of the patterns of the grouped metallization layers has less metal than the second of the patterns of the grouped metallization layers layers.

前述內容概述了幾個實施例的特徵，使得本領域中具有通常知識者可以更好地理解本公開的各方面。本領域中具有通常知識者應該理解，他們可以容易地將本公開作為設計或修改其他過程和結構的基礎，以實現與本文介紹的實施例相同的目的和/或實現相同的益處。本領域中具有通常知識者還應該理解，這樣的等同構造並不脫離本公開的精神和範圍，並且在不脫離本公開的精神和範圍的情況下，可以進行各種改變、替換和變更。 The foregoing summary outlines features of several embodiments so that those of ordinary skill in the art may better understand aspects of the disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and/or achieve the same benefits as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they could make various changes, substitutions and alterations without departing from the spirit and scope of the present disclosure.

300:佈局 300: Layout

311:金屬線 311: metal wire

312:金屬線 312: metal wire

313:金屬線 313: metal wire

314:金屬線 314: metal wire

315:金屬線 315: metal wire

316:金屬線 316: metal wire

Group_1:模型 Group_1: Model

Group_2:模型 Group_2: Model

M1:金屬化層 M1: metallization layer

M2:金屬化層 M2: metallization layer

M3:金屬化層 M3: metallization layer

M4:金屬化層 M4: metallization layer

M5:金屬化層 M5: metallization layer

M6:金屬化層 M6: metallization layer

S31:線至線間距 S31: Line-to-Line Spacing

S32:線至線間距 S32: Line-to-Line Spacing

S33:線至線間距 S33: Line-to-Line Spacing

S34:線至線間距 S34: Line-to-Line Spacing

S35:線至線間距 S35: Line-to-Line Spacing

S36:線至線間距 S36: Line-to-Line Spacing

W31:線寬 W31: Line width

W32:線寬 W32: Line width

W33:線寬 W33: Line width

W34:線寬 W34: Line width

W35:線寬 W35: Line width

W36:線寬 W36: Line width

X:方向 X: direction

Y:方向 Y: Direction

Z:方向 Z: Direction

Claims (10)

一種積體電路結構，包含：一第一電晶體、一第二電晶體、一第三電晶體和一第四電晶體，形成在一基板上；一第一金屬化層，在該第一電晶體、該第二電晶體、該第三電晶體和該第四電晶體上，該第一金屬化層具有複數個第一金屬線，該些第一金屬線沿一第一方向橫向地延伸並具有在垂直於該第一方向的一第二方向上測量的一第一線寬，其中該些第一金屬線中的一個或複數個是電連接該第一電晶體和該第二電晶體的一第一電路網的一部分；以及一第二金屬化層，在該第一金屬化層上，該第二金屬化層具有複數個第二金屬線，該些第二金屬線沿該第二方向橫向地延伸並具有在該第一方向測量的一第二線寬，其中該些第二金屬線的該第二線寬小於該些第一金屬線的該第一線寬，該些第二金屬線中的一個或複數個是電連接該第三電晶體和該第四電晶體的一第二電路網的一部分，並且該第二電路網的沿該第二方向的一總長度小於該第一電路網的沿該第一方向的一總長度。 An integrated circuit structure, comprising: a first transistor, a second transistor, a third transistor and a fourth transistor formed on a substrate; a first metallization layer formed on the first transistor On the crystal, the second transistor, the third transistor and the fourth transistor, the first metallization layer has a plurality of first metal lines, and the first metal lines extend laterally along a first direction and having a first line width measured in a second direction perpendicular to the first direction, wherein one or a plurality of the first metal lines are electrically connected to the first transistor and the second transistor A part of a first circuit network; and a second metallization layer, on the first metallization layer, the second metallization layer has a plurality of second metal lines, and the second metal lines are along the second direction Extending laterally and having a second line width measured in the first direction, wherein the second line width of the second metal lines is smaller than the first line width of the first metal lines, the second metal lines One or more of the lines is part of a second circuit network electrically connecting the third transistor and the fourth transistor, and a total length of the second circuit network along the second direction is smaller than the first A total length of the circuit network along the first direction. 根據請求項1所述的積體電路結構，更包含：一第三金屬化層，在該第一金屬化層下，該第三金屬化層具有複數個第三金屬線，該些第三金屬線沿該第二方向延伸並具有在該第一方向上測量的一第三線寬，其中該些 第三金屬線的該第三線寬小於該些第一金屬線的該第一線寬。 According to the integrated circuit structure described in claim 1, further comprising: a third metallization layer, under the first metallization layer, the third metallization layer has a plurality of third metal lines, and the third metallization layers lines extending along the second direction and having a third linewidth measured in the first direction, wherein the The third line width of the third metal lines is smaller than the first line width of the first metal lines. 根據請求項1所述的積體電路結構，更包含：一第三金屬化層，在該第二金屬化層上，該第三金屬化層具有複數個第三金屬線，該些第三金屬線沿該第二方向延伸並具有沿該第一方向測量的一第三線寬，其中該些第三金屬線的該第三線寬大於該些第二金屬線的該第二線寬。 According to the integrated circuit structure described in Claim 1, further comprising: a third metallization layer, on the second metallization layer, the third metallization layer has a plurality of third metal lines, and the third metallization layers The lines extend along the second direction and have a third linewidth measured along the first direction, wherein the third linewidth of the third metal lines is larger than the second linewidth of the second metal lines. 一種積體電路結構，包含：一第一電晶體、一第二電晶體、一第三電晶體和一第四電晶體，形成在一基板上；一第一金屬化層，在該第一電晶體、該第二電晶體、該第三電晶體和該第四電晶體上，該第一金屬化層包含複數個第一金屬線，該些第一金屬線沿一第一方向橫向地延伸並以一第一線至線間距配置，其中該些第一金屬線中的一個或複數個是電連接該第一電晶體和該第二電晶體的一第一電路網的一部分；以及一第二金屬化層，在該第一金屬化層上，該第二金屬化層包含複數個第二金屬線，該些第二金屬線沿垂直於該第一方向的一第二方向橫向地延伸並以一第二線至線間距配置，其中該第一線至線間距大於該第二線至線間距，該些第二金屬線中的一個或複數個是連接該第三電晶體和該第 四電晶體的一第二電路網的一部分，並且該第二電路網的沿該第二方向的一總長度小於該第一電路網的沿該第一方向的一總長度。 An integrated circuit structure, comprising: a first transistor, a second transistor, a third transistor and a fourth transistor formed on a substrate; a first metallization layer formed on the first transistor On the crystal, the second transistor, the third transistor and the fourth transistor, the first metallization layer includes a plurality of first metal lines, and the first metal lines extend laterally along a first direction and configured with a first line-to-line pitch, wherein one or more of the first metal lines is part of a first circuit network electrically connecting the first transistor and the second transistor; and a second a metallization layer, on the first metallization layer, the second metallization layer includes a plurality of second metal lines extending laterally along a second direction perpendicular to the first direction and A second line-to-line spacing configuration, wherein the first line-to-line spacing is greater than the second line-to-line spacing, one or a plurality of the second metal lines are connected to the third transistor and the first A part of a second circuit network of four transistors, and a total length of the second circuit network along the second direction is smaller than a total length of the first circuit network along the first direction. 根據請求項4所述的積體電路結構，更包含：一第三金屬化層，在該第二金屬化層上，該第三金屬化層包含複數個第三金屬線，該些第三金屬線沿該第一方向延伸並以一第三線至線間距配置，其中該第三線至線間距大於該第二線至線間距。 According to the integrated circuit structure described in claim 4, further comprising: a third metallization layer, on the second metallization layer, the third metallization layer includes a plurality of third metal lines, and the third metallization layers The lines extend along the first direction and are arranged at a third line-to-line spacing, wherein the third line-to-line spacing is greater than the second line-to-line spacing. 根據請求項4所述的積體電路結構，更包含：一第三金屬化層，在該第一金屬化層下，該第三金屬化層沿該第二方向延伸並以一第三線至線間距配置，其中該第三線至線間距小於該第一線至線間距。 The integrated circuit structure according to claim 4, further comprising: a third metallization layer, under the first metallization layer, the third metallization layer extends along the second direction and connects a third line to line A pitch configuration, wherein the third line-to-line pitch is smaller than the first line-to-line pitch. 一種形成積體電路結構的方法，包含：儲存複數個群組化的金屬化層的複數個模型於一儲存媒體中；在一佈局中，將該些群組化的金屬化層的該些模型中的一第一個擺置在複數個半導體元件上；在該佈局中，將該些群組化的金屬化層的該些模型中的一第二個擺置在該些群組化的金屬化層的該些模型中的該第一個上，其中，該些群組化的金屬化層的該些模型中的該第二個的一最底部的金屬化層的一金屬線寬小於該些群 組化的金屬化層的該些模型中的該第一個的一最頂部的金屬化層的一金屬線寬；佈線一第一電路網，使該第一電路網至少部分地在該些群組化的金屬化層的該些模型中的該第一個的該最頂部的金屬化層上，該第一個的該最頂部的金屬化層沿一第一方向延伸；佈線一第二電路網，使該第二電路網至少部分地在該些群組化的金屬化層的該些模型中的該第二個的該最底部的金屬化層上，該第二個的該最底部的金屬化層沿一第二方向延伸，其中該第二電路網的沿該第二方向的一總長度小於該第一電路網的沿該第一方向的一總長度；以及根據該佈局製造一積體電路。 A method of forming an integrated circuit structure, comprising: storing a plurality of models of a plurality of grouped metallization layers in a storage medium; in a layout, the models of the grouped metallization layers a first one of which is placed on a plurality of semiconductor elements; in the layout, a second one of the models of the grouped metallization layers is placed on the grouped metallization layers on the first of the models of the grouped metallization layers, wherein a metal line width of a bottommost metallization layer of the second of the models of the grouped metallization layers is smaller than the some groups A metal line width of a topmost metallization layer of the first one of the models of grouped metallization layers; routing a first circuit net such that the first circuit net is at least partially in the groups On the topmost metallization layer of the first one of the models of organized metallization layers, the topmost metallization layer of the first one extends along a first direction; wiring a second circuit mesh such that the second circuit mesh is at least partially on the bottommost metallization layer of the second of the patterns of the grouped metallization layers, the bottommost of the second the metallization layer extends along a second direction, wherein an overall length of the second circuit net along the second direction is less than an overall length of the first circuit net along the first direction; and fabricating a product according to the layout body circuit. 根據請求項7所述的方法，其中該些群組化的金屬化層的該些模型中的該第一個和該第二個具有相同數量之金屬化層。 The method of claim 7, wherein the first and the second of the models of the grouped metallization layers have the same number of metallization layers. 根據請求項7所述的方法，其中該些群組化的金屬化層的該些模型中的該第一個具有比該些群組化的金屬化層的該些模型中的該第二個更多的金屬化層。 The method according to claim 7, wherein the first of the models of the grouped metallization layers has a higher value than the second of the models of the grouped metallization layers More layers of metallization. 根據請求項7所述的方法，其中該些群組化的金屬化層的該些模型中的該第一個具有比該些群組化的金屬化層的該些模型中的該第二個更少的金屬化層。 The method according to claim 7, wherein the first of the models of the grouped metallization layers has a higher value than the second of the models of the grouped metallization layers Fewer metallization layers.
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11264486B2 (en) * 2020-01-16 2022-03-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of fabricating the semiconductor structure
US11113443B1 (en) * 2020-06-12 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit with thicker metal lines on lower metallization layer
US12272043B2 (en) * 2022-06-04 2025-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor topography simulation of non-removal type processes
US12423499B1 (en) * 2022-06-21 2025-09-23 Cadence Design Systems, Inc. Resistance and capacitance aware preferred layer trimming
US20240055494A1 (en) * 2022-08-12 2024-02-15 Qualcomm Incorporated Via alternate net spacing

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9620510B2 (en) * 2014-12-19 2017-04-11 Taiwan Semiconductor Manufacturing Company Ltd. Stacked metal layers with different thicknesses
CN107273623A (en) * 2012-10-01 2017-10-20 株式会社索思未来 The design method of semiconductor device
TW201917852A (en) * 2017-10-20 2019-05-01 智原科技股份有限公司 Power distribution network of integrated circuit
TW201926555A (en) * 2017-11-22 2019-07-01 台灣積體電路製造股份有限公司 Method of forming conductive grid of integrated circuit

Family Cites Families (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3603229B2 (en) * 1994-02-09 2004-12-22 富士通株式会社 Semiconductor storage device
JPH09321242A (en) * 1996-05-30 1997-12-12 Hitachi Ltd Semiconductor integrated circuit device and manufacturing method thereof
JPH1197525A (en) * 1997-09-19 1999-04-09 Hitachi Ltd Semiconductor device and manufacturing method thereof
TW396524B (en) * 1998-06-26 2000-07-01 United Microelectronics Corp A method for fabricating dual damascene
US7076750B1 (en) * 2001-02-06 2006-07-11 Advanced Micro Devices, Inc. Method and apparatus for generating trenches for vias
JP4497791B2 (en) * 2002-05-09 2010-07-07 株式会社ルネサステクノロジ Semiconductor integrated circuit
JP3808866B2 (en) * 2003-12-05 2006-08-16 株式会社東芝 Semiconductor device
US7023739B2 (en) * 2003-12-05 2006-04-04 Matrix Semiconductor, Inc. NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same
DE102004021261B4 (en) * 2004-04-30 2007-03-22 Advanced Micro Devices, Inc., Sunnyvale Semiconductor device having a hybrid metallization layer stack for improved mechanical strength during and after insertion into a package
JP4602004B2 (en) * 2004-06-22 2010-12-22 株式会社東芝 Test pattern creation device, test pattern creation method, and test pattern creation program
DE102005057076A1 (en) * 2005-11-30 2007-05-31 Advanced Micro Devices, Inc., Sunnyvale Increasing adhesion of metal layers comprises determination of regions of reduced contact hole density and formation of position-holding contacts with metal
DE102006004428B4 (en) * 2006-01-31 2017-12-21 Globalfoundries Inc. Non-destructive Metal Detachment Monitoring Technology in Semiconductor Devices
DE102006025405B4 (en) * 2006-05-31 2018-03-29 Globalfoundries Inc. Method for producing a metallization layer of a semiconductor device with different thickness metal lines
US7565638B2 (en) * 2006-11-21 2009-07-21 Sun Microsystems, Inc. Density-based layer filler for integrated circuit design
JP5104403B2 (en) * 2008-02-29 2012-12-19 富士通株式会社 Capacitors
US9711407B2 (en) * 2009-04-14 2017-07-18 Monolithic 3D Inc. Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer
US8618826B2 (en) * 2009-07-02 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for de-embedding
US8461035B1 (en) * 2010-09-30 2013-06-11 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9293366B2 (en) * 2010-04-28 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias with improved connections
US9484973B1 (en) * 2010-08-09 2016-11-01 Qorvo Us, Inc. Voltage equalization for stacked FETs in RF switches
US10388568B2 (en) * 2011-06-28 2019-08-20 Monolithic 3D Inc. 3D semiconductor device and system
US9406738B2 (en) * 2011-07-20 2016-08-02 Xilinx, Inc. Inductive structure formed using through silicon vias
US20140061915A1 (en) * 2012-08-30 2014-03-06 International Business Machines Corporation Prevention of thru-substrate via pistoning using highly doped copper alloy seed layer
US8891280B2 (en) * 2012-10-12 2014-11-18 Micron Technology, Inc. Interconnection for memory electrodes
US8946884B2 (en) * 2013-03-08 2015-02-03 Xilinx, Inc. Substrate-less interposer technology for a stacked silicon interconnect technology (SSIT) product
US9287257B2 (en) * 2014-05-30 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Power gating for three dimensional integrated circuits (3DIC)
JP6332680B2 (en) * 2014-06-13 2018-05-30 新光電気工業株式会社 Wiring board and manufacturing method thereof
TWI542077B (en) * 2014-10-27 2016-07-11 國立臺灣大學 A three dimensional structure frequency reflecting unit
US9659882B2 (en) * 2015-01-20 2017-05-23 Sandisk Technologies Llc System, method and apparatus to relieve stresses in a semiconductor die caused by uneven internal metallization layers
US11256846B2 (en) * 2015-03-27 2022-02-22 Samsung Electronics Co., Ltd. System and method of analyzing integrated circuit in consideration of a process variation and a shift
JP2016192443A (en) * 2015-03-30 2016-11-10 株式会社東芝 Storage device
US9547742B2 (en) * 2015-04-27 2017-01-17 Nxp Usa, Inc. Systems and methods for via placement
US9634243B1 (en) * 2015-11-27 2017-04-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of forming the same
US10460070B2 (en) * 2016-01-28 2019-10-29 Taiwan Semiconductor Manufacturing Co., Ltd. Optimized electromigration analysis
US9898571B2 (en) * 2016-02-05 2018-02-20 International Business Machines Corporation Layout of interconnect lines in integrated circuits
US9911697B2 (en) * 2016-05-02 2018-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Power strap structure for high performance and low current density
US10157258B2 (en) * 2016-11-18 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method for evaluating failure-in-time
JP6971597B2 (en) 2017-03-10 2021-11-24 キヤノン株式会社 Information processing device, display control method, and program
US10763304B2 (en) * 2017-06-27 2020-09-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of forming the same
US10685157B2 (en) * 2017-09-28 2020-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Power-aware scan partitioning
US10671788B2 (en) * 2017-11-21 2020-06-02 Taiwan Semiconductor Manufacturing Company Ltd. Method, system, and storage medium of resource planning for designing semiconductor device
US10727272B2 (en) * 2017-11-24 2020-07-28 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method of the same
KR20230006054A (en) * 2017-11-30 2023-01-10 인텔 코포레이션 Fin patterning for advanced integrated circuit structure fabrication
US10756114B2 (en) * 2017-12-28 2020-08-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor circuit with metal structure and manufacturing method
US10622306B2 (en) * 2018-03-26 2020-04-14 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure in semiconductor devices
US10586012B2 (en) * 2018-04-25 2020-03-10 International Business Machines Corporation Semiconductor process modeling to enable skip via in place and route flow
US11367749B2 (en) * 2018-06-28 2022-06-21 Intel Corporation Spin orbit torque (SOT) memory devices and their methods of fabrication
US10949597B2 (en) * 2018-07-16 2021-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Through-silicon vias in integrated circuit packaging
CN110323247B (en) * 2019-07-04 2021-08-31 中国科学院微电子研究所 MRAM device, method of manufacturing same, and electronic device including MRAM
US10963609B2 (en) * 2019-08-08 2021-03-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method for analyzing electromigration (EM) in integrated circuit
US11113443B1 (en) * 2020-06-12 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit with thicker metal lines on lower metallization layer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107273623A (en) * 2012-10-01 2017-10-20 株式会社索思未来 The design method of semiconductor device
US9620510B2 (en) * 2014-12-19 2017-04-11 Taiwan Semiconductor Manufacturing Company Ltd. Stacked metal layers with different thicknesses
TW201917852A (en) * 2017-10-20 2019-05-01 智原科技股份有限公司 Power distribution network of integrated circuit
TW201926555A (en) * 2017-11-22 2019-07-01 台灣積體電路製造股份有限公司 Method of forming conductive grid of integrated circuit

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