TWI785674B - Display - Google Patents

Abstract

A display includes multiple groups of pixel circuits, multiple groups of scanning circuits and emission controlling circuits. A first group of pixel circuits includes K pixel circuits. K is an integer larger than one. A first group of scanning circuits is configured to generate and transmit each scanning signal of a first group of scanning signals to a corresponding pixel circuit in the first group of pixel circuits. A first emission controlling circuit is configured to generate and transmit a first group of emission controlling signals to each pixel circuit in the first group of pixel circuits. The first group of pixel circuits is configured to write a data signal into the first group of pixel circuits according to K scanning signals the first group of scanning signals in order, respectively. After the data signal is written into the first group of pixel circuits, the K pixel circuits is configured to emit light simultaneously according to the first group of emission controlling signals and the data signal.

Description

monitor

The present invention relates to a display technology, in particular to a display.

When driving the LED panel, the display device operates according to a pulse-width modulation (PWM) signal. Operation by means of PWM signals may cause a large amount of current to be accumulated in the display device, and the circuit of the driving device requires complex design, which may easily lead to risks such as screen flicker. Therefore, how to develop related technologies that can overcome the above problems is an important issue in this field.

Embodiments of the invention include a display. The display includes multiple groups of pixel circuits, multiple groups of scanning circuits and multiple lighting control circuits. The multiple groups of pixel circuits include a first group of pixel circuits, and the first group of pixel circuits includes K pixel circuits, wherein K is an integer greater than one. The multiple sets of scanning circuits include a first set of scanning circuits, the first set of scanning circuits are used to generate a first set of scanning signals, and are used to transmit each scanning signal of the first set of scanning signals to one of the first set of pixel circuits Corresponding pixel circuit. The multiple light emission control circuits include a first light emission control circuit, the first light emission control circuit is used to generate a first light emission control signal, and is used to transmit the first light emission control signal to each pixel circuit in the first group of pixel circuits . The first group of pixel circuits is used for respectively sequentially writing a data signal into the K pixel circuits in the first group of pixel circuits according to the K scanning signals in the first group of scanning signals. After the data signal is written into the first group of pixel circuits, the K pixel circuits in the first group of pixel circuits emit light simultaneously according to the first lighting control signal and the data signal.

Herein, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although terms such as “first”, “second”, . Unless clearly indicated by the context, the terms do not imply any particular order or sequence, nor are they intended to be limiting of the invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include plural forms including "at least one" unless the content clearly dictates otherwise. "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprising" and/or "comprising" designate the stated features, regions, integers, steps, operations, the presence of elements and/or parts, but do not exclude one or more Existence or addition of other features, regions as a whole, steps, operations, elements, parts and/or combinations thereof.

The following will disclose multiple implementation modes of this case with diagrams. For the sake of clarity, many practical details will be described together in the following description. It should be understood, however, that these practical details should not be used to limit the present case. That is, in some embodiments of the present disclosure, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some well-known structures and components will be shown in a simple and schematic manner in the drawings.

FIG. 1 is a schematic diagram of a display 100 according to an embodiment of the present application. Please refer to FIG. 1 , the display 100 includes a display device 110 , a scanning device 120 , a data input device 130 and a light emission control device 140 . In some embodiments, the display 100 may be made of a glass substrate or a plastic substrate, but is not limited thereto.

In some embodiments, the scanning device 120 provides scanning signals through the scanning lines SL(0)~SL(n), such as the scanning signals G1(n)~G4(n) shown in FIG. 6A and FIG. 8A, to display device 110 . The data input device 130 provides data signals, such as the data signals DTW(m) and DTA(m) shown in FIG. 5 and FIG. 7 , to the display device 110 through the data lines DL( 1 )˜DL(m). Where n and m are both positive integers. The light emission control device 140 provides light emission control signals through the light emission lines EL(1)~EL(Q), such as the light emission control signals GST(Q), EM1(Q), EM2(Q), VST(Q) and SW(Q), to the display device 110 . where Q is a positive integer.

In some embodiments, the scanning device 120, the data input device 130 and the lighting control device 140 are further used to provide other signals as shown in FIG. 7, such as a voltage signal RES and a pinch off signal PPO, to the display device 110, but the embodiment of the present invention is not limited thereto. In various embodiments, various configurations for providing the voltage signal RES and the pinch-off signal PPO to the display device 110 are also within the scope of the embodiments of the present invention.

In some embodiments, the scanning device 120 is implemented as a scanning shift register, and is used for signal reset, data writing and threshold voltage compensation functions. In some embodiments, the lighting control device 140 is implemented as a pulse width modulation (Pulse Width Modulation, PWM) shift register, and is used to generate a ramp signal and a square wave signal for PWM lighting operation, such as FIG. 6A And the light emission control signals EM1(n) and SW(n) shown in FIG. 8A.

FIG. 2 is a block diagram of a display 200 according to an embodiment of the present application. Display 200 is an embodiment of display 100 shown in FIG. 1 .

As shown in FIG. 2 , the display 200 includes a display device 210 , a scanning device 220 and a light emission control device 240 . The display device 210 , the scanning device 220 and the light emission control device 240 are respectively an embodiment of the display device 110 , the scanning device 120 and the light emission control device 140 shown in FIG. 1 .

As shown in FIG. 2, the scanning device 220 is used to generate scanning signals SS(1)~SS(8) according to the scanning clock signals SCLK1, SCLK2, and SCLK3 and the scanning start signal SSTV, and transmit the scanning signals SS(1)~ SS(8) is transmitted to the display device 210 . The light emission control device 240 is used to generate light emission control signals ES(1) and ES(2) according to the light emission clock signals ECLK1, ECLK2, selection signals INA1, INA2, INB1, INB2 and light emission start signal ESTV, and transmit the light emission control signals ES (1) and ES(2) are transmitted to the display device 210 . The display device 210 is used for performing a data writing operation and a light emitting operation according to the scan signals SS( 1 )˜SS( 8 ) and the light emitting control signals ES( 1 ) and ES( 2 ). In some embodiments, the selection signals INA1 , INA2 , INB1 , INB2 are selection imitation signals.

As shown in Figure 2, the display device 210 includes multi-level pixel circuits PX(1)~PX(8), the scanning device 220 includes multi-level scanning circuits SG(1)~SG(8), and the light emission control device 240 includes multi-stage light emission control circuits EG(1) and EG(2).

In the embodiment shown in Figure 2, the scanning start signal SSTV is sequentially transmitted in the scanning circuits SG(1)~SG(8), and the light emission start signal ESTV is transmitted in the light emission control circuits EG(1) and EG(2) ) are delivered sequentially. The scanning circuits SG(1), SG(4) and SG(7) are used to receive the scanning clock signal SCLK1, and the scanning circuits SG(2), SG(5) and SG(8) are used to receive the scanning clock signal SCLK2, And the scan circuits SG( 3 ) and SG( 6 ) are used for receiving the scan clock signal SCLK3. The light emission control circuit EG(1) is used for receiving light emission clock signals ECLK1, ECLK2 and selection signals INA1, INB1. The light emission control circuit EG(2) is used for receiving light emission clock signals ECLK1, ECLK2 and selection signals INA2, INB2. In different embodiments, the scanning circuit and the lighting control circuit may have different signal configuration relationships.

As shown in FIG. 2 , the scanning circuits SG( 1 )˜SG( 8 ) are used to generate scanning signals SS( 1 )˜SS( 8 ), respectively. The light emission control circuits EG(1) and EG(2) are used for generating light emission control signals ES(1) and ES(2) respectively. The pixel circuits PX(1)-PX(8) are respectively used for receiving scan signals SS(1)-SS(8). The pixel circuits PX(1)-PX(4) are used for receiving the light-emitting control signal ES(1), and the pixel circuits PX(5)-PX(8) are used for receiving the light-emitting control signal ES(2).

In some embodiments, each of the pixel circuits PX(1)-PX(8) corresponds to a row of pixel circuits in the display device 210, and the operation of other pixel circuits on the row of pixel circuits is similar to that of a pixel The operation of one of the circuits PX( 1 )˜PX( 8 ) is not repeated here.

In some embodiments, the pixel circuits PX(1)~PX(4) corresponding to the light emission control signal ES(1) are referred to as the first group of pixel circuits, and the scanning circuit SG(1) corresponding to the first group of pixel circuits )~SG(4) are called the first group of scanning circuits, and the scanning signals SS(1)~SS(4) generated by the scanning circuits SG(1)~SG(4) are called the first group of scanning signals. Similarly, the pixel circuits PX(5)~PX(8) corresponding to the lighting control signal ES(2) are called the second group of pixel circuits, and the scanning circuits SG(5)~SG corresponding to the second group of pixel circuits (8) is called the second group of scanning circuits, and the scanning signals SS(5)-SS(8) generated by the scanning circuits SG(5)-SG(8) are called the first group of scanning signals.

In the embodiment corresponding to Fig. 2, the display 200 includes two sets of pixel circuits and two sets of scanning circuits, each set of pixel circuits includes four pixel circuits, and each set of scanning circuits includes four scanning circuits, but the present invention Embodiments are not limited thereto. In different embodiments, the display 200 may include multiple groups of pixel circuits and multiple groups of scanning circuits and corresponding lighting control circuits in different numbers, a group of pixel circuits may include different numbers of pixel circuits, and a group of pixel circuits may include different numbers of pixel circuits, and a group of pixel circuits Circuits may contain varying numbers of scanning circuits.

For example, the pixel circuit 200 includes L light-emitting control circuits, L groups of pixel circuits and L groups of scanning circuits, wherein each group of pixel circuits includes K pixel circuits, and each group of scanning circuits includes K scanning circuits. Each of the L lighting control circuits corresponds to K pixel circuits and K scanning circuits. Wherein L is a positive integer, and K is an integer greater than one.

In some prior approaches, a column of pixel circuits in a display corresponds to a scanning circuit and a light emitting control circuit. The pixel circuit performs data writing operation and lighting operation according to the scanning signal generated by the scanning circuit and the lighting control signal generated by the lighting control circuit. In the above approach, the timing requirements of the scanning signal and the light-emitting control signal may conflict.

Compared with the above method, in the embodiment of the present invention, K pixel circuits PX(1)~PX(K) are used to generate multiple scanning signals SS according to multiple scanning circuits SG(1)~SG(K) (1)~SS(K) and a light emission control signal ES(1) generated by a light emission control circuit EG(1) operate. The scan signal and the light-emitting control signal can meet the timing requirements by adjusting the ratio of the number of the scanning circuit and the light-emitting control circuit. Further details are described below.

FIG. 3 is a timing diagram 300 of the pixel circuit 200 performing a data writing operation and a light emitting operation according to an embodiment of the present invention. As shown in FIG. 3 , the horizontal axis of the timing diagram 300 corresponds to time. The timing diagram 300 includes periods P31 - P316 arranged sequentially and continuously. In some embodiments, the timing diagram 300 corresponds to the operation of the pixel circuits PX(1)-PX(12) during periods P31-P316. In some embodiments, the time lengths of periods P31 to P315 are the same.

Please refer to FIG. 3 and FIG. 2. In the embodiment shown in FIG. 3, during the period P31, the pixel circuit PX(1) is used to reset the corresponding PWM data writing according to the scanning signal SS(1). operate. During the period P32, the pixel circuit PX(1) is used for writing PWM data according to the scan signal SS(1). During the period P34 , the pixel circuit PX( 1 ) is used for performing a reset operation corresponding to writing in Pulse Amplitude Modulation (PAM) data according to the scan signal SS( 1 ). During the period P34, the pixel circuit PX(1) is used for writing PAM data according to the scan signal SS(1). As mentioned above, at the end of the period P34, the pixel circuit PX(1) has written the PWM data signal and the PAM data signal, and is ready to start emitting light.

Similarly, during the period P32, the pixel circuit PX(2) is used to perform a reset operation corresponding to writing PWM data according to the scan signal SS(2). During the period P33, the pixel circuit PX(2) is used for writing PWM data according to the scan signal SS(2). During the period P34, the pixel circuit PX(2) is used for performing a reset operation corresponding to PAM data writing according to the scan signal SS(2). During the period P35, the pixel circuit PX(2) is used for writing PAM data according to the scan signal SS(2). As mentioned above, when the period P35 ends, the pixel circuit PX( 2 ) has written the PWM data signal and the PAM data signal, and is ready to start emitting light.

By analogy, for a positive integer i, during the period P3i, the pixel circuit PX(i) performs a reset operation corresponding to writing PWM data according to the scan signal SS(i). During the period P3(i+1), the pixel circuit PX(i) is used for writing PWM data according to the scan signal SS(i). During the period P3(i+2), the pixel circuit PX(i) is used for performing a reset operation corresponding to PAM data writing according to the scan signal SS(i). During the period P3(i+3), the pixel circuit PX(i) is used for writing PAM data according to the scan signal SS(i). At the end of the period P3(i+3), the pixel circuit PX(i) has written the PWM data signal and the PAM data signal, and is ready to start emitting light.

In other words, as shown in FIG. 3, during the period P31~P315, the pixel circuits PX(1)~PX(12) perform data writing operations sequentially, wherein the i-th pixel circuit PX(i) is based on the i-th The time when the scanning signal SS(i) starts to perform the data writing operation and the time when the i+1th pixel circuit PX(i+1) starts to perform the data writing operation according to the i+1th scanning signal SS(i+1) There is a time interval T31 between the instants. In some embodiments, the length of the time interval T31 is the time length of the period P1.

Please refer to FIG. 3 and FIG. 2. In the embodiment shown in FIG. 3, during the period P38, the pixel circuits PX(1)~PX(4) are simultaneously used for the light generated by the light emitting control circuit EG(1). The light emission control signal ES(1) performs a light emission operation. In other words, after the pixel circuits PX( 1 )˜PX( 4 ) sequentially write data signals during the period P31 ˜P37 , they simultaneously perform light emitting operation during the period P38 .

In some embodiments, the lighting time lengths of the pixel circuits PX(1)~PX(4) are determined by the corresponding PWM data signals, and the pixel circuits PX(1)~PX(4) may have different lighting time lengths . For example, in the embodiment shown in Figure 3, the pixel circuit PX(1) emits light during the period P38~P313, the pixel circuit PX(2) emits light during the period P38~P311, and the pixel circuit PX(3) Light is emitted during the period P38-P314, and the pixel circuit PX(4) emits light during the period P38-P39.

Similarly, in the embodiment shown in FIG. 3, during the period P312, the pixel circuits PX(5)~PX(8) are simultaneously used for the light emission control signal ES(2) generated by the light emission control circuit EG(2) Perform a glow operation. In other words, after the pixel circuits PX( 5 )-PX( 8 ) sequentially write data signals during the period P35-P311 , they simultaneously perform light-emitting operation during the period P312 .

Similarly, in the embodiment shown in FIG. 3, during the period P316, the pixel circuits PX(9)~PX(12) are simultaneously used for the light emission control signal ES(3) generated by the light emission control circuit EG(3) Perform a glow operation. In other words, after the pixel circuits PX( 9 )-PX( 12 ) sequentially write data signals during the period P39-P315 , they simultaneously perform light-emitting operation during the period P316 .

In the embodiment shown in Figure 3, the first group of pixel circuits including pixel circuits PX(1)~PX(4), the second group of pixel circuits including pixel circuits PX(5)~PX(8) The pixel circuit and the third group of pixel circuits including pixel circuits PX(9)-PX(12) emit light sequentially.

T31。舉例來說，第一組畫素電路從期間P38開始發光，且第二組畫素電路從期間P312開始發光，其中期間P38及期間P312之間具有時間間距4

T31。 In the embodiment shown in FIG. 3, each set of pixel circuits includes four pixel circuits. Correspondingly, there is a time interval of 4 between the moment when the i-th group of pixel circuits starts to emit light and the moment when the i+1th group of pixel circuits starts to emit light.

T31. For example, the first group of pixel circuits starts to emit light from the period P38, and the second group of pixel circuits starts to emit light from the period P312, wherein there is a time interval of 4 between the period P38 and the period P312.

T31.

T31。 In some other embodiments, each set of pixel circuits includes K pixel circuits. Correspondingly, there is a time interval K between the moment when the i-th group of pixel circuits start to emit light and the moment when the i+1th group of pixel circuits start to emit light

T31.

As shown in FIG. 3 , the maximum possible light-emitting time of each light-emitting circuit in the first group of pixel circuits is marked by a time interval T32. Time interval T32 is not drawn to scale. Various lengths of the time interval T32 are within the disclosed range of the embodiments of the present invention.

FIG. 4 is a block diagram of a display 400 according to an embodiment of the present application. Display 400 is an embodiment of display 100 shown in FIG. 1 . The display 400 is a variation of the display 200 shown in FIG. 2 .

As shown in FIG. 4 , the display 400 includes a display device 410 , a scanning device 420 and a light emission control device 440 . The display device 410 , the scanning device 420 and the light emission control device 440 are respectively an embodiment of the display device 110 , the scanning device 120 and the light emission control device 140 shown in FIG. 1 .

As shown in FIG. 4, the display device 410 includes multi-level pixel circuits PX(1)~PX(52), the scanning device 420 includes multi-level scanning circuits SG(1)~SG(52), and the light emission control device 440 includes multi-stage lighting control circuits EG( 1 )˜EG( 13 ). The operation and configuration of the display device 410, scanning device 420, and light emission control device 440 are similar to those of the display device 210, scanning device 220, and light emission control device 240 shown in FIG. For example, the pixel circuits PX(49)~PX(52) and the scanning circuits SG(49)~SG(52) correspond to the light emitting control circuit EG(13) and the operation is similar to the pixel circuit PX shown in Figure 2 (1)-PX(4) and scanning circuits SG(1)-SG(4) correspond to the operation of the light-emitting control circuit EG(1).

As shown in FIG. 4 , the light emission control circuits EG( 1 )˜EG( 12 ) are respectively used to receive the driving signals DV1 ˜DV12 . In some embodiments, the light emission control circuits EG( 1 )˜EG( 12 ) are used for generating corresponding light emission control signals ES( 1 )˜ES( 12 ) according to the driving signals DV1 ˜DV12 .

As shown in FIG. 4 , the light emission control circuit EG ( 13 ) is used to receive the driving signal DV1 to generate the light emission control signal ES ( 13 ). In some embodiments, the light emission control circuits EG ( 14 ) - EG ( 24 ) are respectively used to receive the driving signals DV2 - DV12 to generate corresponding light emission control signals.

In the embodiment corresponding to FIG. 4 , the light emission control device 440 is used to receive twelve driving signals DV1 - DV12 , but the embodiment of the present invention is not limited thereto. In various embodiments, the lighting control device 440 is configured to receive various numbers of driving signals.

P+j個發光控制電路用以接收P個驅動信號中的第j個驅動信號以產生對應的發光控制信號，其中k為非負的整數，且j為大於零且小於或等於P的整數。 In some embodiments, the multi-level light emission control circuit in the light emission control device 440 is used to receive P driving signals, and the kth

The P+j lighting control circuits are used to receive the jth driving signal among the P driving signals to generate a corresponding lighting control signal, wherein k is a non-negative integer, and j is an integer greater than zero and less than or equal to P.

T31。在具有P個驅動信號的實施例中，最大可能發光時間具有時間間距T32=P

T31。 Please refer to FIG. 4 and FIG. 3 , in some embodiments, the display 400 operates with the timing shown in FIG. 3 . For example, the pixel circuits PX(1)~PX(52) sequentially perform data writing operations, and correspond to the first group to the thirteenth group of pixel circuits of the lighting control circuits EG(1)~EG(13). The pixel circuits perform light emitting operations sequentially. In the above embodiment, the maximum possible lighting time of the first group of pixel circuits has a time interval T32=12

T31. In an embodiment with P drive signals, the maximum possible luminescence time has a time interval T32=P

T31.

FIG. 5 is a circuit diagram of a pixel circuit 500 according to an embodiment of the present application. The pixel circuit 500 is an embodiment of the pixel circuit PX(n) shown in FIG. 2, wherein n is a positive integer. In some embodiments, the pixel circuit 500 is a progressive PWM driving circuit.

As shown in FIG. 5 , the pixel circuit 500 includes switches T51 - T517 , capacitors C51 - C53 and a light emitting element L5 . In some embodiments, the pixel circuit 500 is used to receive scan signals G1(n) and G2(n), data signals DTW(m), DTA(m) and light emission control signals GST(Q), EM1(Q), EM2(Q), VST(Q) and SW(Q) are used for light emitting operation, wherein m and Q are positive integers. Please refer to Figure 2, the scanning signals G1(n) and G2(n) are examples of the scanning signal SS(n), and the light emission control signals GST(Q), EM1(Q), EM2(Q), VST(Q ), SW(Q) are examples of the light emission control signal ES(Q). In some embodiments, the light emitting control signal EM1(Q) corresponds to a square wave signal of the PWM light emitting operation, and the light emitting control signal SW(Q) corresponds to a ramp wave signal of the PWM light emitting operation.

In some embodiments, the pixel circuit 500 corresponds to the nth pixel circuit PX(n), and is used for scanning signals G1(n), G2(n) and the Qth scanning signal generated by the nth scanning circuit SG(n). The light-emitting control signals GST(Q), EM1(Q), EM2(Q), VST(Q) and SW(Q) generated by each light-emitting control circuit EG(Q) perform data writing operation and light-emitting operation. Wherein the Q th light emission control circuit EG(Q) corresponds to the Q th group of pixel circuits including the pixel circuit 500 .

As shown in FIG. 5 , one end of the switch T51 is coupled to the node N51 , the other end of the switch T51 is used to receive the voltage signal HDC, and the control end of the switch T51 is used to receive the light emission control signal EM2 (Q). One end of the switch T52 is coupled to the node N51, the other end of the switch T52 is used for receiving the data signal DTW(m), and the control end of the switch T52 is used for receiving the scan signal G2(n). One terminal of the switch T53 is coupled to the node N51, the other terminal of the switch T53 is coupled to the node N52, and the control terminal of the switch T53 is coupled to the node N53. One terminal of the switch T54 is coupled to the node N53, the other terminal of the switch T54 is coupled to the node N52, and the control terminal of the switch T54 is used for receiving the scanning signal G2(n). One end of the switch T55 is coupled to the node N53, and the other end and the control end of the switch T55 are used for receiving the scan signal G1(n). One end of the switch T56 is coupled to the node N54, and the other end and the control end of the switch T56 are used for receiving the scan signal G1(n). One terminal of the switch T57 is coupled to the node N55, the other terminal of the switch T57 is used for receiving the voltage signal VDD, and the control terminal of the switch T57 is used for receiving the light emission control signal EM2(Q). One end of the switch T58 is coupled to the node N55, the other end of the switch T58 is used for receiving the data signal DTA(m), and the control end of the switch T58 is used for receiving the scanning signal G2(n). One terminal of the switch T59 is coupled to the node N55, the other terminal of the switch T59 is coupled to the node N56, and the control terminal of the switch T59 is coupled to the node N54. One terminal of the switch T510 is coupled to the node N54, the other terminal of the switch T510 is coupled to the node N56, and the control terminal of the switch T510 is used for receiving the scan signal G2(n). One terminal of the switch T511 is coupled to the node N57, the other terminal of the switch T511 is coupled to the node N56, and the control terminal of the switch T511 is coupled to the node N58. One end of the switch T512 is coupled to the node N57 , the other end of the switch T512 is coupled to the light-emitting element L5 , and the control end of the switch T512 is used for receiving the light-emitting control signal EM1 (Q). One end of the switch T513 is coupled to the node N52, the other end of the switch T513 is coupled to the node N58, and the control end of the switch T513 is used to receive the light emission control signal EM2(Q). One terminal of the switch T514 is coupled to the node N52, the other terminal of the switch T514 is used for receiving the voltage signal LDC, and the control terminal of the switch T514 is used for receiving the light emission control signal GST(Q). One end of the switch T515 is used to receive the voltage signal HDC, the other end of the switch T515 is used to receive the light emission control signal SW(Q), and the control end of the switch T515 is used to receive the light emission control signal VST(Q). One terminal of the switch T516 is coupled to the node N59, the other terminal of the switch T516 is used for receiving the voltage signal HDC, and the control terminal of the switch T515 is used for receiving the light emission control signal VST(Q). One end of the switch T517 is coupled to the node N59, the other end of the switch T517 is used to receive the voltage signal VDD, and the control end of the switch T517 is used to receive the light emission control signal EM2(Q). One end of the capacitor C51 is used to receive the lighting control signal SW(Q), and the other end of the capacitor C51 is coupled to the node N53. One end of the capacitor C52 is coupled to the node N59, and the other end of the capacitor C52 is coupled to the node N54. One end of the capacitor C53 is used to receive the voltage signal LDC, and the other end of the capacitor C53 is coupled to the node N58. One end of the light emitting element L5 is coupled to the switch T512, and the other end of the light emitting element L5 is used for receiving the voltage signal VSS.

FIG. 6A is a timing diagram 601 of the pixel circuit 500 performing a data writing operation and a light emitting operation according to an embodiment of the present invention. As shown in FIG. 6A, the horizontal axis of the timing diagram 601 corresponds to time. The timing diagram 601 includes periods P61 - P66 arranged in sequence.

As shown in the timing diagram 601 , during the period P61 , the scan signal G1(n) and the light emission control signal VST(Q) have the enable voltage level VEN, so that the switches T55 , T56 , T515 and T516 are turned on. At this time, the switches T55 and T56 respectively reset the voltages of the nodes N53 and N54 through the scanning signal G1(n), and the switch T516 resets the voltage of the node N59 through the voltage signal HDC. The switches T53 and T59 are turned on according to the voltages of the nodes N53 and N54 respectively. In some embodiments, the pixel circuit 500 resets the node voltage during the period P61 corresponding to the subsequent data writing operation, so the period P61 is called a data reset period.

As shown in the timing diagram 601 , during the period P62 , the scan signal G2(n) and the light emission control signal VST(Q) have the enable voltage level VEN, so that the switches T52 , T54 , T58 , T510 , T515 and T516 are turned on. At this moment, the data signal DTW(m) is written into the node N53 through the switches T52 , T53 and T54 in sequence, and the data signal DTA(m) is written into the node N54 through the switches T58 , T59 and T510 in sequence. Capacitors C51 and C52 are used to store data signals DTW(m) and DTA(m) respectively. In some embodiments, the pixel circuit 500 writes the data signals DTW(m) and DTA(m) during the period P62, so the period P62 is called a data writing period.

As shown in the timing diagram 601 , during the period P63 , the lighting control signals GST(Q) and VST(Q) have the enable voltage level VEN, so that the switches T514 , T515 and T516 are turned on. At this moment, the voltage signal LDC is written into the node N52 through the switch T514, so that the voltage of the node N52 is reset according to the voltage signal LDC. In some embodiments, the pixel circuit 500 resets the node voltage during the period P63 corresponding to the subsequent light-emitting operation, so the period P63 is called a light-emitting reset period.

As shown in the timing diagram 601 , during the period P64 , the light emission control signals EM1 (Q) and EM2 (Q) have the enable voltage level VEN, so that the switches T51 , T57 , T517 , T513 and T512 are turned on. At this time, the voltage signal VDD is written into the nodes N59 and N55 through the switches T517 and T57 respectively, and the voltage signal HDC is written into the node N51 through the switch T51 .

During the period P64 , the light emission control signal SW(Q) is a ramp wave signal gradually decreasing from the voltage level VDA to the voltage level VEN. The lighting control signal SW(Q) is used to adjust the voltage of the node N53 via the capacitor C51 to further adjust the voltage of the node N52. The switch T513 adjusts the voltage of the node N58 according to the voltage of the node N52, so that the switch T511 is turned on according to the voltage of the node N58. The light emitting element L5 is used for emitting light according to the current passing through the switch T511. In some embodiments, the pixel circuit 500 performs a light-emitting operation during the period P64, so the period P64 is called a light-emitting period.

As shown in the timing diagram 601 , during the period P65 , the lighting control signals GST(Q) and VST(Q) have the enable voltage level VEN, so that the switches T514 , T515 and T516 are turned on. During the period P66 , the light emission control signals EM1 (Q) and EM2 (Q) have the enable voltage level VEN, so that the switches T51 , T57 , T517 , T513 and T512 are turned on.

During the period P65, the pixel circuit 500 performs the lighting reset operation again. During the period P66, the pixel circuit 500 performs the light emitting operation again. In some embodiments, the operations during the periods P65 and P66 are similar to the operations during the periods P63 and P64, so some details will not be described again. In some embodiments, the pixel circuit 500 can repeatedly perform the lighting reset operation and the lighting operation multiple times within a frame time. In some other embodiments, the pixel circuit 500 can perform one lighting reset operation and multiple lighting operations within one frame time.

FIG. 6B is a timing diagram 602 of a group of pixel circuits performing data writing operation and light emitting operation according to an embodiment of the present invention. As shown in FIG. 6B, the horizontal axis of the timing diagram 602 corresponds to time. The timing diagram 602 includes periods R61 - R66 arranged in sequence.

Please refer to FIG. 2, FIG. 5, FIG. 6A and FIG. 6B, in some embodiments, the configuration of each of the pixel circuits PX(1)-PX(8) is similar to the configuration of the pixel circuit 500 . The pixel circuit PX(n) is used for receiving the scanning signals G1(n) and G2(n). Correspondingly, the pixel circuit PX(n+1) is used to receive the scan signals G1(n+1) and G2(n+1) in a similar configuration, and the pixel circuit PX(n+2) is used to similarly configured to receive scanning signals G1(n+2) and G2(n+2), and the pixel circuit PX(n+3) is configured to receive scanning signals G1(n+3) and G2(n+ 3).

Please refer to FIG. 2, FIG. 6A and FIG. 6B, the operation of the pixel circuit PX(n) during the period R61 and R62 is similar to the operation during the period P61 and P62, and the pixel circuit PX(n) during the period R66 The operation of is similar to the operation during P63~P64. Therefore, some details will not be repeated.

In some embodiments, the pixel circuit PX(n) is used to perform data writing operation according to the scanning signals G1(n) and G2(n) during the period R61 and R62, and according to the light emission control signal GST(Q) during the period R66 , EM1(Q), EM2(Q), VST(Q), SW(Q) perform light emitting operation.

In some embodiments, the pixel circuit PX(n+1) is used to perform data writing operation according to the scanning signals G1(n+1) and G2(n+1) during the period R62 and R63, and according to the light emission during the period R66 Control signals GST(Q), EM1(Q), EM2(Q), VST(Q), SW(Q) perform light emitting operations.

In some embodiments, the pixel circuit PX(n+2) is used to perform data writing operation according to the scanning signals G1(n+2) and G2(n+2) during periods R63 and R64, and according to light emission during period R66 Control signals GST(Q), EM1(Q), EM2(Q), VST(Q), SW(Q) perform light emitting operations.

In some embodiments, the pixel circuit PX(n+3) is used to perform data writing operation according to the scanning signals G1(n+3) and G2(n+3) during the period R64 and R65, and according to the light emission during the period R66 Control signals GST(Q), EM1(Q), EM2(Q), VST(Q), SW(Q) perform light emitting operations.

As mentioned above, the pixel circuits PX(n)-PX(n+3) sequentially perform the data writing operation during the period R61-R65, and simultaneously perform the light-emitting operation during the period R66. Please refer to FIG. 3 and FIG. 6B, in some embodiments, the period R61-R65 corresponds to the period P31-P37, and the period R66 corresponds to the period P38-P315.

FIG. 7 is a circuit diagram of a pixel circuit 700 according to an embodiment of the present invention. The pixel circuit 700 is an embodiment of the pixel circuit PX(n) shown in FIG. 2 . In some embodiments, the pixel circuit 700 is a progressive PWM driving circuit.

As shown in FIG. 7 , the pixel circuit 700 includes switches T71 - T714 , capacitors C71 , C72 and a light emitting element L7 . In some embodiments, the pixel circuit 700 is used to receive scan signals G1(n)~G4(n), data signals DTW(m), DTA(m), and light emission control signals EM1(Q), EM2(Q), VST(Q) and SW(Q) are used for light emitting operation, wherein m and Q are positive integers. Please refer to Fig. 2, the scan signal G1(n) ~ G4(n) is an embodiment of the scan signal SS(n), and the light emission control signals EM1(Q), EM2(Q), VST(Q), SW(Q ) is an embodiment of the light emission control signal ES(Q). In some embodiments, the light emitting control signal EM1(Q) corresponds to a square wave signal of the PWM light emitting operation, and the light emitting control signal SW(Q) corresponds to a ramp wave signal of the PWM light emitting operation.

In some embodiments, the pixel circuit 700 corresponds to the nth pixel circuit PX(n), and is used for scanning signals G1(n)~G4(n) generated by the nth scanning circuit SG(n) and the Qth pixel circuit SG(n). The light emission control signals EM1 (Q), EM2 (Q), VST (Q), and SW (Q) generated by each light emission control circuit EG (Q) perform data writing operation and light emission operation. Wherein the Q th light emission control circuit EG(Q) corresponds to the Q th group of pixel circuits including the pixel circuit 700 .

As shown in FIG. 7, one end of the switch T71 is coupled to the node N71, the other end of the switch T71 is used to receive the voltage signal RES, and the control end of the switch T71 is used to receive the scan signal G1(n). One terminal of the switch T72 is coupled to the node N71, the other terminal of the switch T72 is coupled to the node N72, and the control terminal of the switch T72 is used for receiving the scanning signal G2(n). One terminal of the switch T73 is coupled to the node N73, the other terminal of the switch T73 is coupled to the node N72, and the control terminal of the switch T73 is coupled to the node N71. One end of the switch T74 is coupled to the node N74, the other end of the switch T74 is used to receive the data signal DTA(m), and the control end of the switch T74 is used to receive the scan signal G4(n). One terminal of the switch T75 is coupled to the node N72, the other terminal of the switch T75 is coupled to the node N75, and the control terminal of the switch T75 is used for receiving the scan signal G4(n). One terminal of the switch T76 is coupled to the node N74, the other terminal of the switch T76 is used for receiving the voltage signal VDD, and the control terminal of the switch T76 is used for receiving the light emission control signal EM1(Q). One terminal of the switch T77 is coupled to the node N74, the other terminal of the switch T77 is coupled to the node N75, and the control terminal of the switch T77 is coupled to the node N72. One end of the switch T78 is coupled to the node N75, the other end of the switch T78 is coupled to the light-emitting element L7, and the control end of the switch T78 is used for receiving the light-emitting control signal EM2(Q). One end of the switch T79 is coupled to the node N73, the other end of the switch T79 is used to receive the pinch signal PPO, and the control end of the switch T79 is used to receive the light emission control signal EM2(Q). One terminal of the switch T710 is coupled to the node N73, the other terminal of the switch T710 is used for receiving the data signal DTW(m), and the control terminal of the switch T710 is used for receiving the scan signal G2(n). One end of the switch T711 is used to receive the pinch signal PPO, the other end of the switch T711 is used to receive the lighting control signal SW(Q), and the control terminal of the switch T711 is used to receive the lighting control signal VST(Q). One end of the switch T712 is coupled to the node N72, the other end of the switch T712 is used for receiving the voltage signal RES, and the control end of the switch T712 is used for receiving the scan signal G3(n). One end of the switch T713 is coupled to the node N76, the other end of the switch T713 is used to receive the pinch-off signal PPO, and the control end of the switch T713 is used to receive the light emission control signal VST(Q). One end of the switch T714 is coupled to the node N76, the other end of the switch T714 is used to receive the voltage signal VDD, and the control end of the switch T714 is used to receive the light emission control signal EM2(Q). One end of the capacitor C71 is used to receive the lighting control signal SW(Q), and the other end of the capacitor C71 is coupled to the node N71. One end of the capacitor C72 is coupled to the node N72, and the other end of the capacitor C72 is coupled to the node N76. One end of the light emitting element L7 is coupled to the switch T78, and the other end of the light emitting element L7 is used for receiving the voltage signal VSS.

FIG. 8A is a timing diagram 801 of the pixel circuit 700 performing a data writing operation and a light emitting operation according to an embodiment of the present invention. As shown in FIG. 8A, the horizontal axis of the timing diagram 801 corresponds to time. The timing diagram 801 includes periods P81 - P88 arranged in sequence.

As shown in the timing diagram 801 , during the period P81 , the scan signal G1(n) and the light emission control signal VST(Q) have the enable voltage level VEN, so that the switches T71 , T711 and T713 are turned on. At this time, the switch T71 resets the voltage of the node N71 through the voltage signal RES, and the pinch-off signal PPO is written into the nodes N77 and N76 through the switches T711 and T713 respectively. In some embodiments, the pixel circuit 700 resets the node voltage during the period P81 corresponding to the subsequent PWM data writing operation, so the period P81 is called a PWM data reset period.

As shown in the timing diagram 801 , during the period P82 , the scan signal G2(n) and the light emission control signal VST(Q) have the enable voltage level VEN, so that the switches T72 , T710 , T711 and T713 are turned on. At this moment, the data signal DTW(m) is sequentially written into the node N71 through the switches T710 , T73 and T72 . The capacitor C71 is used for storing the data signal DTW(m). In some embodiments, the data signal DTW(m) is a PWM data signal. In some embodiments, the pixel circuit 700 writes the data signal DTW(m) during the period P82, so the period P82 is called a PWM data writing period.

As shown in the timing diagram 801 , during the period P83 , the scan signal G3(n) and the light emission control signal VST(Q) have the enable voltage level VEN, so that the switches T712 , T711 and T713 are turned on. At this time, the switch T712 resets the voltage of the node N72 through the voltage signal RES, and the pinch signal PPO is written into the nodes N77 and N76 through the switches T711 and T713 respectively. In some embodiments, the pixel circuit 700 resets the node voltage during the period P83 corresponding to the subsequent PAM data writing operation, so the period P83 is called a PAM data reset period.

As shown in the timing diagram 801 , during the period P84 , the scan signal G4(n) and the light emission control signal VST(Q) have the enable voltage level VEN, so that the switches T74 , T75 , T711 and T713 are turned on. At this time, the data signal DTA(m) is sequentially written into the node N72 through the switches T74, T77 and T75. The capacitor C72 is used for storing the data signal DTA(m). In some embodiments, the data signal DTA(m) is a PAM data signal. In some embodiments, the pixel circuit 700 writes the data signal DTA(m) during the period P84, so the period P84 is called a PAM data writing period.

As shown in the timing diagram 801 , during the period P85 , the light emission control signals EM1 (Q) and EM2 (Q) have the enable voltage level VEN, so that the switches T79 , T78 , T76 and T714 are turned on. At this time, the voltage signal VDD is written into the nodes N74 and N76 through the switches T76 and T714 respectively, and the pinch signal PPO is written into the node N73 through the switch T79 .

During the period P85 , the light-emitting control signal SW(Q) is a ramp signal gradually decreasing from the voltage level VDA to the voltage level VEN. The lighting control signal SW(Q) is used to adjust the voltage of the node N71 via the capacitor C71 to further adjust the voltage of the node N72. The switch T73 adjusts the voltage of the node N72 according to the voltage of the node N71 , so that the switch T77 is turned on according to the voltage of the node N72 . The light emitting element L7 is used to emit light according to the current passing through the switch T77. In some embodiments, the pixel circuit 700 performs a light-emitting operation during the period P85, so the period P85 is called a light-emitting period.

As shown in the timing diagram 801 , during the period P86 , the scan signal G3(n) and the light emission control signal VST(Q) have the enable voltage level VEN, so that the switches T712 , T711 and T713 are turned on. During the period P87, the scan signal G4(n) and the light emission control signal VST(Q) have the enable voltage level VEN, so that the switches T74, T75, T711 and T713 are turned on. During the period P85, the light emission control signals EM1(Q) and EM2(Q) have the enabling voltage level VEN, so that the switches T79, T78, T76 and T714 are turned on.

During the period P86˜P87, the pixel circuit 700 writes the PAM data signal again. During the period P88, the pixel circuit 700 performs the light emitting operation again. In some embodiments, operations during periods P86 , P87 and P88 are similar to operations during periods P83 , P84 and P85 , so some details will not be described again. In some embodiments, the pixel circuit 700 can repeatedly perform the PAM data writing operation and the lighting operation multiple times within one frame time. In some other embodiments, the pixel circuit 700 can perform one PAM data writing operation and multiple lighting operations within one frame time.

FIG. 8B is a timing diagram 802 of a group of pixel circuits performing data writing operation and light emitting operation according to an embodiment of the present invention. As shown in FIG. 8B, the horizontal axis of the timing diagram 802 corresponds to time. The timing diagram 802 includes periods R81 - R88 arranged in sequence.

Please refer to FIG. 2, FIG. 7, FIG. 8A and FIG. 8B, in some embodiments, the configuration of each of the pixel circuits PX(1)-PX(8) is similar to the configuration of the pixel circuit 700 . The pixel circuit PX(n) is used for receiving the scanning signals G1(n)˜G4(n). Correspondingly, the pixel circuit PX(n+1) is used to receive the scan signals G1(n+1)~G4(n+1) in a similar configuration, and the pixel circuit PX(n+2) is used to similarly The configuration mode receives scanning signals G1(n+2)~G4(n+2), and the pixel circuit PX(n+3) is used to receive scanning signals G1(n+3)~G4(n+ 3).

Please refer to FIG. 2, FIG. 8A and FIG. 8B, the operation of the pixel circuit PX(n) during the period R81~R84 is similar to the operation during the period P81~P84, and the operation of the pixel circuit PX(n) during the period R88 The operation is similar to the operation during P85. Therefore, some details will not be repeated.

In some embodiments, the pixel circuit PX(n) is used to perform data writing operation according to the scanning signals G1(n)~G4(n) during the period R81~R84, and according to the light emission control signal EM1(Q) during the period R88 , EM2(Q), VST(Q), and SW(Q) perform light-emitting operations.

In some embodiments, the pixel circuit PX(n+1) is used to perform data writing operation according to the scan signal G1(n+1)~G4(n+1) during the period R82~R85, and according to the light emission during the period R88 Control signals EM1(Q), EM2(Q), VST(Q), SW(Q) perform light emitting operation.

In some embodiments, the pixel circuit PX(n+2) is used to perform data writing operation according to the scan signal G1(n+2)~G4(n+2) during the period R83~R86, and according to the light emission during the period R88 Control signals EM1(Q), EM2(Q), VST(Q), SW(Q) perform light emitting operation.

In some embodiments, the pixel circuit PX(n+3) is used to perform data writing operation according to the scan signal G1(n+3)~G4(n+3) during the period R84~R87, and according to the light emission during the period R88 Control signals EM1(Q), EM2(Q), VST(Q), SW(Q) perform light emitting operation.

As mentioned above, the pixel circuits PX(n)-PX(n+3) sequentially perform the data writing operation during the period R81-R87, and simultaneously perform the light-emitting operation during the period R88. Please refer to FIG. 3 and FIG. 8B, in some embodiments, the period R81-R87 corresponds to the period P31-P37, and the period R88 corresponds to the period P38-P315.

The above-mentioned various data writing methods and light-emitting operation methods in this case are used for illustration, and other various data writing methods and light-emitting operation methods are within the scope of this case.

To sum up, in the embodiment of the present invention, the display 200 controls the pixel circuit PX (1 )~PX(K) a group of pixel circuits, so that the pixel circuits PX(1)~PX(K) sequentially write data signals according to the scanning signals SS(1)~SS(K), and according to the light control signal ES(1) emits light at the same time. In this way, the display 200 can meet the timing requirements of various signals.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

100, 200, 400: display

110, 210, 410: display device

120, 220, 420: scanning device

130: data input device

140, 240, 440: lighting control device

SL(0)~SL(n): scan line

SS(1)~SS(52), G1(n)~G4(n), G1(n+1)~G4(n+1), G1(n+2)~G4(n+2), G1( n+3)~G4(n+3): scan signal

DL(1)~DL(m): data line

DTW(m), DTA(m): data signal

EL(1)~EL(Q): luminescent line

SCLK1, SCLK2, SCLK3: scan clock signal

SSTV: scan start signal

ECLK1, ECLK2: Luminous clock signal

INA1, INA2, INB1, INB2: select signal

ESTV: Luminescent start signal

ES(1)~ES(13), GST(Q), EM1(Q), EM2(Q), VST(Q), SW(Q): lighting control signal

DV1~DV12: drive signal

PPO: pinch off signal

SG(1)~SG(52): scanning circuit

PX(1)~PX(52), 500, 700: pixel circuit

EG(1)~EG(13): light control circuit

L5, L7: light emitting elements

VSS, VDD, RES, HDC, LDC: voltage signal

300, 601, 602, 801, 802: timing diagram

P31~P316, P61~P66, R61~R66, P81~P88, R81~R88: period

T32: time interval

C51~C53, C71, C72: capacitance

T51~T517, T71~T714: switch

N51~N59, N71~N76: nodes

VEN, VDA: voltage level

Fig. 1 is a schematic diagram of a display according to an embodiment of the present application. FIG. 2 is a block diagram of a display according to an embodiment of the present invention. FIG. 3 is a timing diagram of a pixel circuit performing a data writing operation and a light emitting operation according to an embodiment of the present invention. FIG. 4 is a block diagram of a display according to an embodiment of the present application. FIG. 5 is a circuit diagram of a pixel circuit according to an embodiment of the present invention. FIG. 6A is a timing diagram of a pixel circuit performing a data writing operation and a light emitting operation according to an embodiment of the present invention. FIG. 6B is a timing diagram of a group of pixel circuits performing data writing operation and light emitting operation according to an embodiment of the present invention. FIG. 7 is a circuit diagram of a pixel circuit according to an embodiment of the present invention. FIG. 8A is a timing diagram of a pixel circuit performing a data writing operation and a light emitting operation according to an embodiment of the present invention. FIG. 8B is a timing diagram of a group of pixel circuits performing data writing operation and light emitting operation according to an embodiment of the present invention.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

300: Timing diagram

P31~P316: period

PX(1)~PX(12): pixel circuit

EG(1)~EG(3): light control circuit

T32: time interval

Claims (10)

A display, comprising: multiple groups of pixel circuits, including a first group of pixel circuits, the first group of pixel circuits including K pixel circuits, wherein K is an integer greater than one; multiple groups of scanning circuits, including a first A group of scanning circuits, the first group of scanning circuits is used to generate a first group of scanning signals, and is used to transmit each scanning signal of the first group of scanning signals to a corresponding pixel circuit in the first group of pixel circuits ; A plurality of light emission control circuits, including a first light emission control circuit, the first light emission control circuit is used to generate a first light emission control signal, and is used to transmit the first light emission control signal to the pixel circuits in the first group Each pixel circuit, wherein the first group of pixel circuits is used to respectively sequentially write a data signal into the K of the first group of pixel circuits according to the K scanning signals of the first group of scanning signals pixel circuits, and after the data signal is written into the first group of pixel circuits, the K pixel circuits in the first group of pixel circuits are used to start simultaneously according to the first light-emitting control signal and the data signal glow. The display as described in claim 1, wherein the multiple sets of pixel circuits further include a second set of pixel circuits, the second set of pixel circuits includes K pixel circuits, and a second set of the multiple sets of scanning circuits The scanning circuit is used to generate a second group of scanning signals and to transmit each scanning signal of the second group of scanning signals To a corresponding pixel circuit in the second group of pixel circuits, a second light emission control circuit of the light emission control circuits is used to generate a second light emission control signal, and is used to transmit the second light emission control signal to the first light emission control circuit For each pixel circuit in the two groups of pixel circuits, the second group of pixel circuits is used for K scanning signals in a second group of scanning signals after the data signal is written into the first group of pixel circuits respectively write the data signal into the K pixel circuits in the second group of pixel circuits in sequence, and after the data signal is written into the second group of pixel circuits, the K pixel circuits in the second group of pixel circuits The K pixel circuits are used for simultaneously emitting light according to the second light emitting control signal and the data signal. The display as described in claim 2, wherein a moment when a first pixel circuit in the first group of pixel circuits starts to write the data signal is the same as a second pixel circuit in the first group of pixel circuits There is a first time interval between a moment when the data signal starts to be written, the moment when the first group of pixel circuits start to emit light according to the first light emission control signal and the second group of pixel circuits according to the second light emission There is a second time interval between a moment when the control signal starts to emit light, and a length of the second time interval is K times a length of the first time interval. The display according to claim 3, wherein the light emission control circuits include the first light emission control circuit that emits light sequentially To a Pth light emitting control circuit and a P+1th light emitting control circuit, the first light emitting control circuit to the Pth light emitting control circuit are respectively used to receive a first driving signal to a P first driving signal, and the Pth light emitting control circuit The +1 light emitting control circuit is used for receiving the first driving signal, wherein P is a positive integer, and the first light emitting control circuit is used for generating the first light emitting control signal according to the first driving signal. The display according to claim 4, wherein a maximum possible light-emitting time of the first group of pixel circuits is P times the second time interval. The display as described in claim 2, wherein when the second group of pixel circuits writes the data signal into the second group of pixel circuits according to the second group of scanning signals, the first group of pixel circuits is used to The first light-emitting control signal and the data signal emit light. The display device according to claim 1, wherein the first light emission control signal includes a square wave signal and a ramp wave signal for pulse width modulation light emission operation. The display as described in claim 1, wherein each group of pixel circuits of the multiple groups of pixel circuits includes K pixel circuits, and the K pixel circuits of each group of pixel circuits perform data writing operations in sequence , there is a first time interval between each writing operation, the plurality of groups of pixel circuits sequentially perform light-emitting operations, and each group of pixel circuits There is a second time interval between light emitting operations, and a length of the second time interval is K times a length of the first time interval. The display as described in claim item 8, wherein the plurality of light-emitting control circuits are divided into P groups of light-emitting control circuits, and the P groups of light-emitting control circuits are used to generate corresponding light-emitting control signals according to P driving signals, and the multiple groups of light-emitting control circuits A maximum possible lighting time of each group of pixel circuits of the pixel circuits is P times of the second time interval. The display according to claim 1, wherein after the data signal is written into the first group of pixel circuits, the first group of pixel circuits alternately resets the first group of pixel circuits according to the first light emission control signal At least one reset operation and at least one light emitting operation of at least one node voltage.

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