CN119068815B

CN119068815B - Display device and driving method thereof

Info

Publication number: CN119068815B
Application number: CN202411346680.2A
Authority: CN
Inventors: 王超; 张洲; 查国伟
Original assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Priority date: 2024-09-25
Filing date: 2024-09-25
Publication date: 2025-10-31
Anticipated expiration: 2044-09-25
Also published as: CN119068815A

Abstract

The application provides a display device and a driving method thereof. The display device comprises a display panel and a control circuit, wherein the display panel comprises N areas divided along a scanning direction, each area comprises a plurality of pixel units, N is an integer larger than 1, the control circuit is used for generating a ramp wave signal, inputting the ramp wave signal to the pixel units, and sequentially controlling the pixel units in each of the N areas to perform data writing and light emitting in a driving period of one frame of picture, the ramp wave signal comprises N pulse periods in the driving period of one frame of picture, the driving period of the pixel unit in each area comprises a data writing sub-period and a light emitting sub-period, the data writing sub-period precedes the light emitting sub-period, the data writing sub-period comprises one pulse period of the ramp wave signal, and the light emitting sub-period comprises N-1 pulse periods of the ramp wave signal. The display device and the driving method thereof can solve the technical problem that the brightness adjusting range of the existing display device is limited.

Description

Display device and driving method thereof

Technical Field

The application relates to the technical field of display, in particular to a display device and a driving method thereof.

Background

Micro light emitting diode (Micro LED) display technology mainly has two modes of Pulse Width Modulation (PWM) and Pulse Amplitude Modulation (PAM) on a circuit architecture, and each mode has advantages and disadvantages. The corresponding lighting modes include global lighting and progressive lighting.

In the global lighting scheme, since the entire display panel emits light at the same time after data writing, a high instantaneous current is generated. This is particularly true in PWM circuit architectures, where higher instantaneous currents are generated at different gray levels. This has an adverse effect on power consumption and internal voltage drop (IR drop) of the display panel.

On the other hand, the micro led display technology is also required to be compatible with both extreme requirements of ultra-high brightness and ultra-low brightness, which requires that the light emission time can be adjusted in a larger range.

The conventional PWM driving method is difficult to simultaneously satisfy the requirements of low power consumption and wide brightness range. While simple progressive lighting can reduce instantaneous current, ramp signals need to be fed row by row and shifted row by row, thus increasing circuit complexity and cost.

Therefore, how to realize a wider brightness adjustment range in the micro light emitting diode display technology, simultaneously reduce power consumption, improve gray scale accuracy, and improve the effect of flicker (flicker) is a technical problem to be solved currently.

Disclosure of Invention

The embodiment of the application provides a display device and a driving method thereof, which aim to solve the technical problem of limited brightness adjusting range in the existing display device.

The embodiment of the application provides a display device, which comprises a display panel, a control circuit and a display control circuit, wherein the display panel comprises N areas divided along a scanning direction, each area comprises a plurality of pixel units, N is an integer larger than 1, the control circuit is electrically connected with the pixel units and used for generating a ramp signal, inputting the ramp signal to the pixel units and sequentially controlling the pixel units in each of the N areas to write data and emit light in a driving period of one frame picture, the ramp signal comprises N pulse periods in the driving period of one frame picture, the driving period of each pixel unit in each area comprises a data writing sub-period and a light emitting sub-period, the data writing sub-period precedes the light emitting sub-period, the data writing sub-period comprises one pulse period of the ramp signal, and the light emitting sub-period comprises N-1 pulse periods of the ramp signal.

The embodiment of the application also provides a driving method of the display device, wherein the display panel of the display device comprises N areas divided along the scanning direction, each area comprises a plurality of pixel units, N is an integer larger than 1, the driving method comprises the steps of generating a ramp signal, inputting the ramp signal into the pixel units, sequentially controlling the pixel units in each of the N areas to write data and emit light in the driving period of one frame, wherein the driving period of the pixel units in each area comprises a data writing sub-period and a light emitting sub-period, the data writing sub-period precedes the light emitting sub-period, the data writing sub-period comprises one pulse period of the ramp signal, and the light emitting sub-period comprises N-1 pulse periods of the ramp signal.

The embodiment of the application adopts a pulse width modulation driving mode combining global oblique wave signals and multiple pulses, realizes progressive luminescence, and effectively solves the technical problems of limited brightness adjusting range, higher power consumption, insufficient gray scale accuracy, obvious flickering phenomenon and the like in the prior art. Specifically, the embodiment of the application adopts global ramp wave signals, ensures that all pixel units receive the same ramp wave signals, improves the display consistency, introduces a multi-pulse light emitting technology, ensures that the pixel units in each area can emit light for a plurality of times in the driving period of a frame of picture, enlarges the brightness adjustment range, particularly can effectively improve the flicker phenomenon during low gray level display, can flexibly control the light emitting duty ratio by adjusting the pulse quantity and the light emitting time of each pulse, and meets the wide display requirement from ultra-low brightness to ultra-high brightness.

Drawings

Fig. 1 is a schematic diagram of a display device according to an embodiment of the present application.

Fig. 2 is a schematic diagram of area division of a display device according to an embodiment of the present application.

Fig. 3 is a circuit diagram of a pixel unit of a display device according to an embodiment of the present application.

Fig. 4 is a waveform diagram of each signal in the display device shown in fig. 3.

Detailed Description

The following describes specific embodiments of the present application in detail with reference to the drawings.

The terms "first," "second," and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The term "plurality" and similar words mean two or more, unless specifically defined otherwise.

Embodiments of the present application may be combined with each other.

As shown in fig. 1, the display device provided in the embodiment of the present application may be, for example, a Micro-LED display device, and of course, the display device may also be a Mini-LED display device or an OLED display device.

The display device comprises a source electrode driving circuit, a gate electrode driving circuit, a time sequence controller, a light-emitting controller, a power management chip, a substrate, a DATA line DATA, a scanning line SCAN, power lines (VDD and VSS), a light-emitting control signal line EM, a pixel array, a packaging layer, a polaroid, a color filter and the like.

The substrate may be, for example, a glass substrate, a flexible substrate (e.g., a polyimide substrate), or the like. The pixel array is formed by arranging a plurality of pixel units PX in rows and columns, and each pixel unit PX includes a light emitting device and a driving circuit. The driving circuit includes a TFT device for controlling brightness of each light emitting device of the display apparatus, the TFT device including Low Temperature Polysilicon (LTPS) and a metal oxide TFT, the light emitting device being electrically connected to the driving circuit, the light emitting device including a light emitting layer, an electron transporting layer, a hole transporting layer, a cathode, an anode, and the like. Each stage of gate driving units in the gate driving circuit correspondingly controls one row of pixel units PX, for realizing the gating of the pixel units PX. Each stage of gate driving unit is composed of a Thin Film Transistor (TFT) and a capacitor. The source driving circuit is used for providing a data signal to the pixel unit PX. The timing controller is used for receiving externally input image data and synchronous signals and generating signals required by the grid driving circuit and the source driving circuit. The power management chip is used for providing required working voltages for various parts of the display device.

In addition, the display device can be integrated with an embedded touch control circuit, is electrically connected with a display driving circuit, and realizes a touch control function and a display function in a time division multiplexing mode.

Embodiments of the present application provide a display device and a driving method thereof. The display device includes a display panel and a control circuit. As shown in fig. 2, the display panel includes N regions (R1 to RN) divided along the scanning direction SD, each region including a plurality of pixel units PX, N being an integer greater than 1. The control circuit is electrically connected to the plurality of pixel units PX, and is configured to generate a ramp signal sleep, input the ramp signal sleep to the plurality of pixel units PX, and sequentially control the pixel units PX of each of the N regions (R1 to RN) to perform data writing and light emission in a driving period of one frame of picture.

The ramp signal Sweep in the display device and the driving method thereof provided by the embodiment of the application is a global multi-pulse signal. The global means that one ramp signal Sweep is supplied to all the pixel units PX of the entire display panel, i.e., one ramp signal output terminal is electrically connected to all the pixel units PX of the entire display panel. The multi-pulse signal Sweep has a plurality of pulse periods within a driving period of one frame of picture, and in the embodiment of the present application, the number of pulse periods is the same as the number of regions of the display panel.

In the display device and the driving method thereof provided by the embodiment of the application, the ramp signal Sweep includes N pulse periods in the driving period of one frame of picture, the driving period of the pixel unit PX of each region includes a data writing sub-period and a light emitting sub-period, the data writing sub-period precedes the light emitting sub-period, the data writing sub-period includes one pulse period of the ramp signal Sweep, and the light emitting sub-period includes N-1 pulse periods of the ramp signal Sweep.

The display panel is divided into N regions (R1-RN) from top to bottom (along the scanning direction SD), and after the pixel unit PX of each region finishes writing data, the light-emitting stage is entered. Since the pixel unit PX needs to be continuously restarted due to the combination of the multi-pulse ramp signal Sweep, the pixel unit PX is reset once in the pulse period of each light-emitting stage, so as to ensure that the pixel unit PX compares the ramp signal Sweep with the data signal and emits light during the pulse period.

As shown in fig. 3 and 4, a pixel unit PX in a display device provided in an embodiment of the present application includes a light emitting device 204 and a driving circuit. The driving circuit comprises a pulse width modulation module 201, a pulse amplitude modulation module 203 and a reset module 202. The pulse width modulation module 201 is electrically connected with the reset module 202, the reset module 202 is electrically connected with the pulse amplitude modulation module 203, and the pulse amplitude modulation module 203 is electrically connected with the light emitting device 204.

The control circuit is used for generating a ramp signal Sweep, a first reset control signal and a light-emitting control signal. The first reset control signal is used for controlling the reset module 202 in the pixel unit PX to reset, and the light-emitting control signal is used for controlling the pixel unit PX to emit light.

In the embodiment of the present application, each of the N regions (R1 to RN) includes M rows of pixel units PX, where M is an integer greater than 1. The control circuit supplies M scan signals to M rows of pixel cells PX of each region in a data writing stage of the data writing sub-period.

Specifically, a scanning signal of the kth region (K is greater than or equal to 1 and less than or equal to N) is denoted as S (K). The first area has M scanning signals, which are S1-SM respectively, the 2 nd area has M scanning signals, which are SM+1-S2M respectively, and the N th area has M scanning signals, which are S (N-1) M+1-SN M respectively.

In an embodiment of the application, the data writing sub-period comprises a pulse period, the data writing sub-period comprising a first reset phase and a data writing phase, each first reset phase being followed by a data writing phase.

In the first reset phase, the control circuit inputs a first reset control signal RST to the reset module 202 of the pixel unit PX. The light emission control signal EM (K) is a high level signal, so that the first transistor T1, the sixth transistor T6, the fourteenth transistor T14 in the pulse width modulation module 201 and the pulse width modulation module 203 are turned off, while the second reset control signal EMi (K) is a low level signal, so that the fifth transistor T5, the thirteenth transistor T13 are turned on, the low level signal Vss is written to the first node a and the fifth node E, and the potentials of these nodes are reset.

In the Data writing stage, the scan signal S (K) sequentially becomes a low level signal such that the second transistor T2, the third transistor T3, the tenth transistor T10, the eleventh transistor T11 are turned on, and the Data signal (including the first Data signal data_pwm (K) and the second Data signal data_pam (K)) is written into the pixel unit PX.

In an embodiment of the application, the light emitting sub-period comprises a plurality of pulse periods, in particular, the light emitting sub-period comprises N-1 second reset phases and N-1 light emitting phases, each second reset phase being followed by one light emitting phase.

In the second reset phase, the control circuit inputs a first reset control signal RST to the reset module 202 of the pixel unit PX. Specifically, the first reset control signal RST is a low level signal, so that the eighth transistor T8, the ninth transistor T9 in the reset block 202 are turned on, and the reset voltage is written to the third node C and the fourth node D. Meanwhile, the light emission control signal EM (K) is a low level signal, so that the first transistor T1, the sixth transistor T6, the fourteenth transistor T14 in the pulse width modulation module 201 and the pulse width modulation module 203 are turned on, the ramp signal Sweep is a high level signal, and a high potential is coupled to the first node a.

In the light emitting stage, the control circuit inputs the ramp signal Sweep and the Data signal (including the first Data signal data_pwm (K) and the second Data signal data_pam (K)) to the pulse width modulation module 201 and the pulse amplitude modulation module 203 of the pixel unit PX, so that the pixel unit PX controls the light emitting device 204 to emit light according to the ramp signal Sweep and the Data signal. Specifically, as the potential of the ramp signal Sweep decreases, the potential of the first node a gradually decreases until the fourth transistor T4 is turned on, the fourth node D is pulled down to Vdd potential, and simultaneously the third node C is coupled to the seventh transistor T7 to be turned on, and the seventh transistor T7, the twelfth transistor T12, and the fourteenth transistor T14 on the light emitting channel are all turned on, and the light emitting device 204 starts to emit light.

Through the multi-pulse light-emitting mode, the display device of the embodiment of the application can emit light for a plurality of times in the driving period of one frame of picture, thereby improving the display effect, particularly effectively improving the flicker phenomenon during low-gray-scale display, and realizing the large-scale controllability of the light-emitting duty ratio.

As shown in fig. 4, the driving period of the pixel unit PX of the kth region includes a phase 1, a phase 2, a phase 3, a phase 4, a phase 5, a phase 6, and the like.

In the driving period of the pixel unit PX of the K-th region, a data writing operation including a first reset phase (phase 1) and a data writing phase (phase 2) and then a light emitting operation including a second reset phase (phase 3, phase 5, phase 7) and a light emitting phase (phase 4, phase 6, phase 8) are performed first.

In the stage 1, a first reset stage in the data writing sub-period is entered, a plurality of scanning signals S (K) input to a Kth area are all high-level signals, a global ramp signal is a high-level signal, a first reset control signal RST is a low-level signal, a light emitting control signal EM (K) is a high-level signal, and a second reset control signal EMi (K) is a low-level signal. In the first reset phase, for the pulse width modulation module 201 and the pulse amplitude modulation module 203, the light emission control signal EM (K) of the area is a high level signal, the first transistor T1, the sixth transistor T6, and the fourteenth transistor T14 are turned off, the second reset control signal EMi (K) is a low level signal, the fifth transistor T5, and the thirteenth transistor T13 are turned on, the low level signal Vss is written into the first node a and the fifth node E, the potentials of the first node a and the fifth node E are reset, the fourth transistor T4 and the twelfth transistor T12 are turned on to ensure the compensation of the threshold voltage Vth when the pixel cells PX of all rows in the area are written with the Data signal, the fourth transistor T4 is compensated for the threshold voltage Vth by Vdd, and the twelfth transistor T12 is compensated for the threshold voltage Vth by the Data signal (the second Data signal data_pam (K)). The second reset control signal EMi (K) is a reset control signal of one frame picture.

In the reset module 202, the global first reset control signal RST is a low level signal (the first reset control signal RST is a reset control signal corresponding to one pulse period, the global first reset control signal RST is that the first reset control signal input end is electrically connected to all pixel units PX of the entire display panel, one first reset control signal RST is provided to all pixel units PX of the entire display panel), the eighth transistor T8 and the ninth transistor T9 are turned on, the third node C and the fourth node D write the first reset signal Vref and the second reset signal VH respectively (the first reset signal Vref may be a high potential voltage, the second reset signal VH may be a high potential voltage, or a low potential voltage). The first reset signal Vref is used to turn off the seventh transistor T7.

In the stage 2, a data writing stage is entered, the ramp signal Sweep is a signal with a level linearly reduced, the first reset control signal RST is a high level signal, the second reset control signal EMi (K) is a high level signal, and the light emission control signal EM (K) is a high level signal. The plurality of scan signals S (K) sequentially inputted to the plurality of rows of pixel units PX of the K-th area are low level signals, the second transistor T2, the third transistor T3, the tenth transistor T10, and the eleventh transistor T11 are turned on, the second reset control signal EMi (K) is a high level signal, the fifth transistor T5, and the thirteenth transistor T13 are turned off, the fourth transistor T4, and the twelfth transistor T12 are turned on, and the first node a and the fifth node E sequentially write data for compensating the threshold voltages Vth of the fourth transistor T4 and the twelfth transistor T12 until the pixel units PX of all rows of the area are written. In both stage 1 and stage 2, the emission control signal EM (K) is a high level signal, and since the first transistor T1 is turned off by the emission control signal EM (K), the ramp signal Sweep is not used to compare with the Data signal (the first Data signal data_pwm (K)) during the period of the pulse (stage 1 and stage 2).

In the stage 3, a second reset stage in the light emitting sub-period is entered, a plurality of scanning signals S (K) sequentially input to a plurality of rows of pixel units PX in a Kth area are all high-level signals, a second reset control signal EMi (K) is a high-level signal, a first reset control signal RST is a low-level signal, a ramp signal is a high-level signal, a light emitting control signal EM (K) is a low-level signal, all of the first transistor T1, the sixth transistor T6 and the fourteenth transistor T14 are turned on, a global ramp signal is a high-level signal, a first node A is coupled to a high potential, and a fourth transistor T4 is turned off. The global first reset control signal RST is a low level signal, the eighth transistor T8 and the ninth transistor T9 are turned on, the fourth node D writes the potential of the second reset signal VH, and the seventh transistor T7 is turned off. The fourth transistor T4 is turned off and the sixth transistor T6 is turned on. The seventh transistor T7 is turned off in the light emission path, and the twelfth transistor T12 and the fourteenth transistor T14 are turned on.

In the light emitting stage of the light emitting sub-period, the plurality of scanning signals S (K) input to the Kth area are all high-level signals, the second reset control signal EMi (K) is a high-level signal, the first reset control signal RST is a high-level signal, the ramp signal Sweep is a ramp signal with linearly reduced level, and the light emitting control signal EM (K) is a low-level signal. As the potential of the ramp signal Sweep decreases, the potential of the coupled first node a gradually decreases until the fourth transistor T4 is turned on, the fourth node D is pulled down to Vdd potential, and the third node C is coupled to the seventh transistor T7 to be turned on, all of the seventh transistor T7, the twelfth transistor T12, and the fourteenth transistor T14 on the light emitting channel are turned on, and the light emitting device 204 starts to emit light.

Stage 5. Entering the second reset stage of the next light emitting sub-period, the global first reset control signal RST is a low level signal and the seventh transistor T7 is turned off. The light emitting device 204 emits light and terminates, while the potentials of the third node C and the fourth node D are reset, and the ramp signal Sweep jumps to a high potential, the first node a is coupled to the high potential, and the fourth transistor T4 is turned off. In stage 5, the level (potential) of each signal is the same as that of stage 3.

And 6, entering a light-emitting stage of the next light-emitting subcycle. As the potential of the ramp signal Sweep decreases, the fourth transistor T4 is turned on again, and in turn the seventh transistor T7 is turned on, the light emitting device 204 emits light again. In stage 6, the level (potential) of each signal is the same as that of stage 4.

Repeating the steps to finish the multi-pulse light emission.

The display device and the driving method thereof provided by the embodiment of the application realize the combined effect of pulse width modulation and multi-pulse and progressive luminescence by adopting the global multi-pulse ramp signal Sweep. Specifically, by dividing the display panel into a plurality of regions, the pixel unit PX of each region completes data writing and light emission a plurality of times in the driving period of one frame of picture, not only the display effect is improved, but also the instantaneous current is reduced. In addition, the embodiment of the application promotes the low gray scale flicker expression and realizes the large-range controllability of the luminous duty ratio. By adopting the multi-pulse light-emitting mode, the light can be emitted for a short time for multiple times during low gray scale display, and the flicker phenomenon is effectively improved.

TABLE 1

As shown in table 1 above, the operating states of the plurality of transistors (T1-T14) and the plurality of nodes (A, B, C, D, E) in the driving circuit at different stages are as follows:

Stage 1 (first reset stage before data writing) is that T1/T6/T14, T2/T3/T10/T11 are turned off, T4, T5/T13, T8/T9, T12 are turned on, node A is at VSS, node B is at sweep_H, node C is at Vref, node D is at VH, and node E is at Vss.

Stage 2 (Data writing stage) T1/T6/T14 off, T2/T3/T10/T11, T4, T12 on, T5/T13, T7, T8/T9 off, node A voltage of Vdd+Vt1, node B voltage of Data_PWM, node C voltage of Vref, node D voltage of VH, node E voltage of Data_PAM+Vt2.

Stage 3 (second reset stage) in which T1/T6/T14, T8/T9, T12 are turned on and the other transistors are turned off, node A is at Vdd+Vt1+Sweep_H-Data_PWM, node B is at Sweep_H, node C is at Vref, node D is at VH, and node E is at Data_PAM+Vt2.

Stage 4 (light emitting stage) where T1/T6/T14, T12 remain on, T4 and T7 change from off to on, the other transistors are off, the voltage at node A changes from Vdd+Vt1+Sweep_H-Data_PWM to Vdd+Vt1+Sweep (T) -Data_PWM, the voltage at node B is Sweep (T), the voltage at node C changes from Vref to Vref+vdd-VH, the voltage at node D changes from VH to Vdd, and the voltage at node E remains data_PAM+Vt2.

Phase 5 (next reset phase) is similar to phase 3.

Stage 6 (next lighting stage) is similar to stage 4.

In the driving period of a frame of picture, the six stages are sequentially carried out, so that the processes of resetting, data writing and multiple light emitting are realized. After the data writing is completed, the pixel units PX in each region emit light for a plurality of times, thereby improving the display effect.

By adopting the global multipulse ramp signal Sweep, the pixel units PX of each area of the display panel complete data writing and multiple light emission in the driving period of one frame of picture, so that the display device of the embodiment of the application can emit light for multiple times in the driving period of one frame of picture, thereby improving the display effect, reducing the instantaneous current, effectively improving the flicker phenomenon particularly in low gray scale display and realizing the large-scale controllability of the light emission duty ratio.

Embodiments of the present application provide a display device including a display panel and a control circuit. The display panel is electrically connected with the control circuit. The control circuit may include a source driving circuit, a gate driving circuit, a timing controller, a light emitting controller, and a power management chip.

As shown in fig. 2, the display panel includes N regions (R1 to RN) divided along the scanning direction SD, each region including a plurality of pixel units PX, N being an integer greater than 1.

The control circuit is electrically connected to the plurality of pixel units PX, and is configured to generate a ramp signal Sweep, input the ramp signal Sweep to the plurality of pixel units PX, and sequentially control the pixel units PX of each of the N regions (R1 to RN) to perform data writing and light emission in a driving period of one frame of picture.

The ramp signal Sweep includes N pulse periods in a driving period of one frame, the driving period of the pixel unit PX of each region includes a data writing sub-period and a light emitting sub-period, the data writing sub-period precedes the light emitting sub-period, the data writing sub-period includes one pulse period of the ramp signal Sweep, and the light emitting sub-period includes N-1 pulse periods of the ramp signal Sweep.

As an improvement, the control circuit is further configured to dynamically adjust the number of partitions according to the complexity of the display content. The control circuit first analyzes the image complexity of the current frame, for example, by calculating the frequency component or dynamic range of the image, and then dynamically adjusts the number of partitions N according to the analysis result. For example, for complex scenes of high dynamic range, the number of partitions is increased to improve control accuracy, and for simple scenes of low dynamic range, the number of partitions is reduced to reduce power consumption.

As shown in fig. 3 and 4, the pixel unit PX includes a light emitting device 204 and a driving circuit. The driving circuit is electrically connected to the light emitting device 204 for controlling the light emission of the light emitting device 204.

The driving circuit includes a pulse width modulation module 201, a pulse amplitude modulation module 203 and a reset module 202, wherein the pulse width modulation module 201 is electrically connected with the reset module 202, the reset module 202 is electrically connected with the pulse amplitude modulation module 203, and the pulse amplitude modulation module 203 is electrically connected with the light emitting device 204.

The pwm module 201 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a first capacitor C1.

The gate of the first transistor T1 is electrically connected to the emission control signal input EM (K), one of the source and the drain of the first transistor T1 is electrically connected to the ramp signal input Sweep, and the other of the source and the drain of the first transistor T1 is electrically connected to the first node a.

The gate of the second transistor T2 is electrically connected to the scan signal input terminal S (K), one of the source and the drain of the second transistor T2 is electrically connected to the first Data signal input terminal data_pwm (K), and the other of the source and the drain of the second transistor T2 is electrically connected to the first node a.

One end of the first capacitor C1 is electrically connected to the first node a, and the other end of the first capacitor C1 is electrically connected to the second node B.

The gate of the third transistor T3 is electrically connected to the scan signal input terminal S (K), and one of the source and the drain of the third transistor T3 is electrically connected to the second node B.

The gate of the fourth transistor T4 is electrically connected to the second node B, one of the source and the drain of the fourth transistor T4 is electrically connected to the first power signal input terminal Vdd, and the other of the source and the drain of the fourth transistor T4 is electrically connected to the other of the source and the drain of the third transistor T3.

The gate of the fifth transistor T5 is electrically connected to the second reset control signal input terminal EMi (K), one of the source and the drain of the fifth transistor T5 is electrically connected to the second power signal input terminal Vss, and the other of the source and the drain of the fifth transistor T5 is electrically connected to the second node B.

The gate of the sixth transistor T6 is electrically connected to the emission control signal input terminal EM (K), one of the source and the drain of the sixth transistor T6 is electrically connected to the drain of the fourth transistor T4, and the other of the source and the drain of the sixth transistor T6 is electrically connected to the third node C of the reset module 202.

The reset module 202 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a second capacitor C2.

The gate of the seventh transistor T7 is electrically connected to the third node C, and one of the source and the drain of the seventh transistor T7 is electrically connected to the first power signal input terminal Vdd.

The gate of the eighth transistor T8 is electrically connected to the first reset control signal input terminal RST, one of the source and the drain of the eighth transistor T8 is electrically connected to the second reset signal input terminal VH, and the other of the source and the drain of the eighth transistor T8 is electrically connected to the fourth node D.

The gate of the ninth transistor T9 is electrically connected to the first reset control signal input terminal RST, one of the source and the drain of the ninth transistor T9 is electrically connected to the first reset signal input terminal Vref, and the other of the source and the drain of the ninth transistor T9 is electrically connected to the third node C.

One end of the second capacitor C2 is electrically connected to the third node C, and the other end of the second capacitor C2 is electrically connected to the fourth node D.

The pulse amplitude modulation module 203 includes a third capacitor C3, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14.

One end of the third capacitor C3 is electrically connected to the first power signal input terminal Vdd, and the other end of the third capacitor C3 is electrically connected to the fifth node E.

The gate of the tenth transistor T10 is electrically connected to the scan signal input terminal S (K), and one of the source and the drain of the tenth transistor T10 is electrically connected to the fifth node E.

The gate of the eleventh transistor T11 is electrically connected to the scan signal input terminal S (K), one of the source and the drain of the eleventh transistor T11 is electrically connected to the second Data signal input terminal data_pam (K), and the other of the source and the drain of the eleventh transistor T11 of the pulse amplitude modulation module 203 is electrically connected to the other of the source and the drain of the seventh transistor T7.

The gate of the twelfth transistor T12 is electrically connected to the fifth node E, one of the source and the drain of the twelfth transistor T12 is electrically connected to the other of the source and the drain of the eleventh transistor T11, and the other of the source and the drain of the twelfth transistor T12 is electrically connected to the other of the source and the drain of the tenth transistor T10.

The gate of the thirteenth transistor T13 is electrically connected to the second reset control signal input terminal EMi (K), one of the source and the drain of the thirteenth transistor T13 is electrically connected to the second power signal input terminal Vss, and the other of the source and the drain of the thirteenth transistor T13 is electrically connected to the fifth node E.

The gate of the fourteenth transistor T14 is electrically connected to the emission control signal input terminal EM (K), one of the source and the drain of the fourteenth transistor T14 is electrically connected to the drain of the twelfth transistor T12, and the other of the source and the drain of the fourteenth transistor T14 is electrically connected to the anode of the light emitting device 204.

As shown in fig. 4, the Data writing sub-period includes a first reset phase and a Data writing phase, and the control circuit is configured to input a first reset control signal RST to the reset module 202 of the pixel unit PX in the first reset phase, and write Data signals (including a first Data signal data_pwm (K) and a second Data signal data_pam (K)) to the pulse width modulation module 201 and the pulse amplitude modulation module 203 of the pixel unit PX in the Data writing phase after the first reset phase.

The light emitting sub-period includes N-1 second reset phases and N-1 light emitting phases, and the control circuit is configured to input a first reset control signal RST to the reset module 202 of the pixel unit PX in the second reset phase, and input a ramp signal Sweep and a data signal to the pulse width modulation module 201 and the pulse amplitude modulation module 203 of the pixel unit PX in the light emitting phase after the second reset phase, so that the pixel unit PX controls the light emitting device 204 to emit light according to the ramp signal Sweep and the data signal.

The control circuit is further configured to generate a first reset control signal RST for controlling the reset module 202 in the pixel unit PX to perform reset, and a light emission control signal EM (K) for controlling the pixel unit PX to emit light.

As an improvement, the control circuit is further adapted to dynamically adjust the duration of each lighting phase in dependence on the image content of the current frame. For example, the control circuit extends the light emission time for a high luminance region and shortens the light emission time for a low luminance region. The control circuit is used for analyzing input image data in real time, calculating average brightness or brightness distribution of each area, and then generating a light emission control parameter. These emission control parameters are used to adjust the pulse width of the emission control signal EM (K) to dynamically adjust the emission time.

As an improvement, the control circuit is further configured to dynamically adjust the slopes of the rising edge and the falling edge of the first reset control signal RST according to the current display content. For example, for a high contrast image region, a first reset control signal RST with a steep slope is generated to increase the response speed, and for a low contrast region, a first reset control signal RST with a gentle slope is generated to reduce the overcharge. The control circuit may comprise a digital-to-analog converter (DAC) and a variable current source. The DAC sets the output of the current source according to an instruction of the control circuit, thereby controlling the slope of the first reset control signal RST.

The first reset control signal RST is a low level signal in the first reset stage of the data writing sub-period, a high level signal in the data writing stage of the data writing sub-period, the light emission control signal EM (K) is a high level signal in the data writing sub-period and a low level signal in the light emission sub-period, or

The first reset control signal RST is a high level signal in the first reset phase, a low level signal in the data writing phase, and the emission control signal EM (K) is a low level signal in the data writing sub-period and a high level signal in the emission sub-period.

The first reset control signal RST is a low level signal in the second reset stage of the light emitting sub-period, a high level signal in the light emitting stage of the light emitting sub-period, and a low level signal in the light emitting sub-period, or

The first reset control signal RST is a high level signal in the second reset phase of the light emitting sub-period, is a low level signal in the light emitting phase of the light emitting sub-period, and the light emitting control signal EM (K) is a high level signal in the light emitting sub-period.

The control circuit includes a ramp signal generating unit having an output terminal electrically connected to the plurality of pixel units PX of the display panel, the ramp signal generating unit being configured to generate a ramp signal Sweep and to supply the ramp signal Sweep to the plurality of pixel units PX.

As an improvement, the control circuit is further configured to adjust the distribution and duration of the respective pulses of the ramp signal Sweep during the driving period of one frame of the picture. Specifically, the control circuit may configure more light-emitting pulses in the middle portion of the frame, and reduce the number of pulses in the beginning and ending portions of the frame.

As an improvement, the ramp signal generating unit of the control circuit comprises a programmable current source. The programmable current source is used for dynamically adjusting the slope of the ramp signal Sweep according to the brightness distribution of the current display content. Specifically, the programmable current source changes its output current according to the control signal provided by the control circuit, thereby changing the charge rate of the ramp signal Sweep. For example, for high brightness regions, a larger current is used to generate a steeper slope to increase contrast, and for low brightness regions, a smaller current is used to generate a softer slope to increase gray scale performance. This dynamic adjustment may be made multiple times during each frame to accommodate the brightness requirements of different regions.

Each of the N regions (R1 to RN) includes M rows of pixel units PX, M being an integer greater than 1, and the control circuit is further configured to provide M scan signals S (K) to the M rows of pixel units PX of each region during a data writing phase of the data writing sub-period.

As an improvement, the control circuit is further configured to generate the interlaced scanning signal such that the same rows of different partitions are scanned sequentially. For example, row 1 of the first region, row 1 of the second region, row 1 of the third region, row 1 of the fourth region are scanned sequentially, followed by row 2 of the first region, row 2 of the second region, and so on. Thus, the instant power consumption can be further reduced, and the power consumption distribution of the large-size display panel can be improved.

As an improvement, the control circuit is further configured to dynamically adjust the pulse width of the scan signal S (K) according to the data complexity of the current row. Specifically, the control circuit first analyzes the degree of data change for each row. For the lines with large data variation, the control circuit lengthens the pulse width of the scan signal S (K) to give more time for data writing, and for the lines with small data variation, shortens the pulse width of the scan signal S (K).

As an improvement, the control circuit is also configured to precharge the first capacitor C1 of the pixel unit PX with a level close to the target voltage in the data writing phase. Specifically, before actually writing the data signal, the control circuit first applies a preset voltage to the first capacitor C1, which is close to the target voltage to be finally written. The precharge mode can remarkably shorten the data writing time and improve the writing efficiency.

All the transistors in the display device provided by the embodiment of the application are P-type transistors, and of course, may be N-type transistors.

The embodiment of the application also provides a driving method of the display device, which comprises the following steps:

the ramp signal Sweep is generated, and includes N pulse periods within a driving period of one frame of picture.

The ramp signal Sweep is input to the plurality of pixel units PX.

In the driving period of one frame of picture, the pixel units PX of each of the N regions (R1 to RN) are sequentially controlled to perform data writing and light emission.

The driving period of the pixel unit PX of each region includes a data writing sub-period and a light emitting sub-period, the data writing sub-period precedes the light emitting sub-period, the data writing sub-period includes one pulse period of the ramp signal Sweep, and the light emitting sub-period includes N-1 pulse periods of the ramp signal Sweep.

The data writing sub-period includes a first reset phase and a data writing phase, and the driving method further includes:

in the first reset phase, a first reset control signal RST is input to the reset module 202 of the pixel unit PX;

In the data writing stage after the first reset stage, a data signal is written to the pulse width modulation module 201 and the pulse width modulation module 203 of the pixel unit PX of the current area.

The light emitting sub-period includes N-1 second reset phases and N-1 light emitting phases, and the driving method further includes:

In the second reset phase, a first reset control signal RST is input to the reset module 202 of the pixel unit PX of the current area to reset the pixel unit PX;

In the light emitting stage after the second reset stage, the ramp signal Sweep and the data signal are input to the pulse width modulation module 201 and the pulse amplitude modulation module 203 of the pixel unit PX, so that the pixel unit PX controls the light emitting device 204 to emit light according to the ramp signal Sweep and the data signal.

The driving method further includes:

a first reset control signal RST for controlling the reset module 202 in the pixel unit PX to perform reset and a light emission control signal EM (K) for controlling the pixel unit PX to emit light are generated.

In the first reset phase of the data writing sub-period, the first reset control signal RST is a low level signal.

In the data writing stage of the data writing sub-period, the first reset control signal RST is a high level signal.

In the data writing sub-period, the emission control signal EM (K) is a high level signal.

In the light emitting sub-period, the light emission control signal EM (K) is a low level signal.

In a second reset phase of the light emitting subcycle, the first reset control signal RST is a low level signal;

in the light emitting stage of the light emitting sub-period, the first reset control signal RST is a high level signal;

Each of the N regions (R1 to RN) includes M rows of pixel units PX, M being an integer greater than 1, and the driving method further includes:

in the data writing stage of the data writing sub-period, M scan signals S (K) are supplied to M rows of pixel units PX of each region.

The driving method further includes the steps of:

under the control of the emission control signal EM (K), the ramp signal Sweep is written to the first node a through the first transistor T1;

under control of the scan signal S (K), writing a data signal to the first node a through the second transistor T2;

storing a voltage between a first node a and a second node B through a first capacitor C1;

Under control of the scan signal S (K), the threshold voltage of the first transistor T1 is compensated by the third transistor T3 and the fourth transistor T4;

Under control of a second reset control signal EMi (K), the second node B is initialized through a fifth transistor T5;

the first power supply signal Vdd output from the fourth transistor T4 is output to the reset block 202 through the sixth transistor T6 under the control of the light emission control signal EM (K).

The driving method further includes the steps of:

under the control of the voltage of the third node C, selectively providing the first power signal Vdd to the pulse amplitude modulation module 203 through the seventh transistor T7;

Under control of the first reset control signal RST, writing the second reset signal VH to the fourth node D through the eighth transistor T8;

under control of the first reset control signal RST, writing the first reset signal Vref to the third node C through the ninth transistor T9;

The coupling changes the voltage of the third node C through the second capacitor C2 when the voltage of the fourth node D changes.

The driving method further includes the steps of:

Under the control of the scan signal S (K), the tenth transistor T10 and the eleventh transistor T11 are simultaneously turned on. Wherein, the turn-on of T10 causes the voltage of the fifth node E to be transmitted, and the turn-on of T11 transmits the second Data signal Data_PAM (K) to the source of T12.

The twelfth transistor T12 is selectively turned on under the control of the fifth node E voltage. Specifically, the gate of T12 is connected to node E, and its on state depends on the voltage level of node E.

Under the control of the second reset control signal EMi (K), the thirteenth transistor T13 is turned on, and the level of the second power supply signal Vss is transmitted to the fifth node E, thereby initializing the fifth node E.

In the light emitting stage, the light emission control signal EM (K) controls the fourteenth transistor T14 to be turned on, connecting the drain of T12 with the anode of the light emitting device 204.

The third capacitor C3 is connected between the first power signal input terminal Vdd and the fifth node E for storing a control voltage.

The embodiment of the application adopts a pulse width modulation driving mode of combining a global ramp signal Sweep and multiple pulses, realizes progressive luminescence, and effectively solves the technical problems of limited brightness adjustment range, higher power consumption, insufficient gray scale accuracy, obvious flickering phenomenon and the like in the prior art. Specifically, the embodiment of the application adopts the global ramp signal Sweep, ensures that all pixel units receive the same ramp signal Sweep, improves the display consistency, introduces a multi-pulse light emitting technology, sequentially completes data writing and multi-light emission in the driving period of one frame of picture by the pixel units of each region in the driving period of one frame of picture, enlarges the brightness adjusting range, particularly can effectively improve the flicker phenomenon when in low gray scale display, can flexibly control the light emitting duty ratio by adjusting the pulse number and the light emitting time of each pulse, meets the wide display requirement from ultra-low brightness to ultra-high brightness, and further adopts a progressive light emitting mode to divide the display panel into a plurality of regions, sequentially completes data writing and multi-light emission by the pixel units of each region in the driving period of one frame of picture, thereby not only improving the display effect, but also remarkably reducing the instantaneous current and effectively solving the problem of high power consumption.

The foregoing describes in detail embodiments of the present application, and the description should not be construed as limiting the scope of the application.

Claims

1. A display device, comprising:

A display panel including N regions divided along a scanning direction, each region including a plurality of pixel units, N being an integer greater than 1, and

The control circuit is electrically connected with the pixel units, is used for generating oblique wave signals, inputting the oblique wave signals to the pixel units and sequentially controlling the pixel units of each of the N areas to write data and emit light in a driving period of one frame of picture;

The driving period of the pixel unit of each area comprises a data writing sub-period and a light emitting sub-period, the data writing sub-period precedes the light emitting sub-period, the data writing sub-period comprises one pulse period of the ramp signal, and the light emitting sub-period comprises N-1 pulse periods of the ramp signal;

The pixel unit includes:

Light emitting device, and

The driving circuit is electrically connected with the light-emitting device and used for controlling the light-emitting of the light-emitting device;

the driving circuit comprises a pulse width modulation module, a pulse amplitude modulation module and a reset module, wherein the pulse width modulation module is electrically connected with the reset module, the reset module is electrically connected with the pulse amplitude modulation module, and the pulse amplitude modulation module is electrically connected with the light emitting device;

The pulse width modulation module comprises:

a first transistor, a gate of which is electrically connected to a light emission control signal input terminal, one of a source and a drain of which is electrically connected to the ramp signal input terminal, and the other of the source and the drain of which is electrically connected to a first node;

A second transistor, a gate of which is electrically connected to the scan signal input terminal, one of a source and a drain of which is electrically connected to the first data signal input terminal, and the other of the source and the drain of which is electrically connected to the first node;

a first capacitor, one end of which is electrically connected with the first node, and the other end of which is electrically connected with the second node;

A third transistor having a gate electrically connected to the scan signal input terminal, one of a source and a drain electrically connected to the second node;

A fourth transistor having a gate electrically connected to the second node, one of a source and a drain electrically connected to the first power signal input terminal, and the other of the source and the drain electrically connected to the other of the source and the drain of the third transistor;

a fifth transistor, a gate of which is electrically connected to the second reset control signal input terminal, one of a source and a drain of which is electrically connected to the second power signal input terminal, and the other of the source and the drain of which is electrically connected to the second node;

And a sixth transistor, wherein the grid electrode of the sixth transistor is electrically connected with the light-emitting control signal input end, one of the source electrode and the drain electrode of the sixth transistor is electrically connected with the drain electrode of the fourth transistor, and the other of the source electrode and the drain electrode of the sixth transistor is electrically connected with the third node of the reset module.

2. The display device of claim 1, wherein the reset module comprises:

A seventh transistor having a gate electrically connected to the third node, one of a source and a drain electrically connected to the first power signal input terminal;

an eighth transistor, a gate of which is electrically connected to the first reset control signal input terminal, one of a source and a drain of which is electrically connected to the second reset signal input terminal, and the other of the source and the drain of which is electrically connected to the fourth node;

A ninth transistor having a gate electrically connected to the first reset control signal input terminal, one of a source and a drain electrically connected to the first reset signal input terminal, and the other of the source and the drain electrically connected to the third node;

and one end of the second capacitor is electrically connected with the third node, and the other end of the second capacitor is electrically connected with the fourth node.

3. The display device of claim 1, wherein the pulse amplitude modulation module comprises:

One end of the third capacitor is electrically connected with the first power supply signal input end, and the other end of the third capacitor is electrically connected with a fifth node;

A tenth transistor having a gate electrically connected to the scan signal input terminal, one of a source and a drain electrically connected to the fifth node;

An eleventh transistor, a gate of the eleventh transistor is electrically connected to the scan signal input terminal, one of a source and a drain of the eleventh transistor is electrically connected to the second data signal input terminal, and the other of the source and the drain of the eleventh transistor of the pulse amplitude modulation module is electrically connected to the other of the source and the drain of the seventh transistor of the reset module;

a twelfth transistor having a gate electrically connected to the fifth node, one of a source and a drain electrically connected to the other of the source and the drain of the eleventh transistor, and the other of the source and the drain electrically connected to the other of the source and the drain of the tenth transistor;

a thirteenth transistor having a gate electrically connected to the second reset control signal input terminal, one of a source and a drain electrically connected to the second power signal input terminal, and the other of the source and the drain electrically connected to the fifth node;

A fourteenth transistor having a gate electrically connected to the emission control signal input terminal, one of a source and a drain electrically connected to the drain of the twelfth transistor, and the other of the source and the drain electrically connected to the anode of the light emitting device.

4. The display device according to claim 1, wherein the data writing sub-period includes a first reset phase and a data writing phase, the control circuit is configured to input a first reset control signal to a reset module of the pixel unit in the first reset phase, and write a data signal to a pulse width modulation module and a pulse amplitude modulation module of the pixel unit in the data writing phase after the first reset phase;

The light emitting subcycle comprises N-1 second reset phases and N-1 light emitting phases, the control circuit is used for inputting a first reset control signal to a reset module of the pixel unit in the second reset phases, and inputting the ramp signal and the data signal to a pulse width modulation module and a pulse amplitude modulation module of the pixel unit in the light emitting phases after the second reset phases, so that the pixel unit controls a light emitting device to emit light according to the ramp signal and the data signal.

5. The display device according to claim 4, wherein the control circuit is further configured to generate a first reset control signal for controlling the reset module in the pixel unit to perform reset and a light emission control signal for controlling the pixel unit to emit light.

6. The display device according to claim 5, wherein the first reset control signal is a low level signal in a first reset phase of the data writing sub-period, a high level signal in a data writing phase of the data writing sub-period, the light emission control signal is a high level signal in the data writing sub-period, and a low level signal in the light emitting sub-period, or

The first reset control signal is a high-level signal in the first reset phase, a low-level signal in the data writing phase, and a light-emitting control signal is a low-level signal in the data writing sub-period and a high-level signal in the light-emitting sub-period.

7. The display device of claim 6, wherein the first reset control signal is a low level signal during a second reset phase of the light emitting sub-period, a high level signal during a light emitting phase of the light emitting sub-period, and a low level signal during the light emitting sub-period, or

The first reset control signal is a high-level signal in a second reset stage of the light emitting sub-period, is a low-level signal in a light emitting stage of the light emitting sub-period, and is a high-level signal in the light emitting sub-period.

8. The display device according to claim 1, wherein the control circuit includes a ramp signal generating unit, an output terminal of the ramp signal generating unit being electrically connected to the plurality of pixel units of the display panel, the ramp signal generating unit being configured to generate the ramp signal and to supply the ramp signal to the plurality of pixel units.

9. The display device according to claim 1, wherein each of the N regions includes M rows of pixel cells, M being an integer greater than 1, the control circuit further configured to provide M scan signals to the M rows of pixel cells of each of the regions during a data writing phase of the data writing sub-period.

10. A driving method of a display device according to any one of claims 1 to 9, wherein a display panel of the display device includes N regions divided in a scanning direction, each region including a plurality of pixel units, N being an integer greater than 1, the driving method comprising:

Generating a ramp signal, wherein the ramp signal comprises N pulse periods in a driving period of a frame of picture;

Inputting the ramp signal to a plurality of the pixel units;

In a driving period of a frame of picture, sequentially controlling the pixel units of each of N areas to write data and emit light;

The driving period of the pixel unit of each region comprises a data writing sub-period and a light emitting sub-period, the data writing sub-period precedes the light emitting sub-period, the data writing sub-period comprises one pulse period of the ramp signal, and the light emitting sub-period comprises N-1 pulse periods of the ramp signal.

11. The driving method according to claim 10, wherein the data writing sub-period includes a first reset phase and a data writing phase, the driving method further comprising:

In the first reset stage, a first reset control signal is input to a reset module of the pixel unit;

And in the data writing stage after the first resetting stage, writing data signals into a pulse width modulation module and a pulse amplitude modulation module of the pixel unit.

12. The driving method according to claim 10, wherein the light emitting sub-period includes N-1 second reset phases and N-1 light emitting phases, the driving method further comprising:

In the second reset stage, a first reset control signal is input to a reset module of the pixel unit;

And in a light-emitting stage after the second reset stage, inputting the ramp signal and the data signal to a pulse width modulation module and a pulse amplitude modulation module of the pixel unit, so that the pixel unit controls a light-emitting device to emit light according to the ramp signal and the data signal.

13. The driving method according to claim 10, characterized in that the driving method further comprises:

And generating a first reset control signal and a light-emitting control signal, wherein the first reset control signal is used for controlling a reset module in the pixel unit to reset, and the light-emitting control signal is used for controlling the pixel unit to emit light.

14. The driving method according to claim 13, wherein in a first reset phase of the data writing sub-period, the first reset control signal is a low level signal;

In a data writing stage of the data writing sub-period, the first reset control signal is a high level signal;

in the data writing sub-period, the light-emitting control signal is a high-level signal;

In the light emitting sub-period, the light emission control signal is a low level signal.

15. The driving method according to claim 14, wherein in a second reset phase of the light emitting sub-period, the first reset control signal is a low level signal;

in the light emitting stage of the light emitting subcycle, the first reset control signal is a high level signal;

16. The driving method according to claim 10, wherein each of the N regions includes M rows of pixel units, M being an integer greater than 1, the driving method further comprising:

And in a data writing stage of the data writing sub-period, M scanning signals are provided for M rows of pixel units of each area.