TWI783615B - Switching converter circuit and driver circuit having adaptive dead time thereof - Google Patents

Abstract

A switching converter circuit for switching one terminal of an inductor therein to different voltages according to a pulse width modulation (PWM) signal to convert an input power to an output power. The switching converter circuit includes a high side MOSFET, a low side MOSFET, and a driver circuit. The driver circuit includes a high side driver, a low side driver, and a dead time control circuit. The dead time control circuit adaptively delays a low side driver signal according to an output current to generate a high side enable signal for enabling the high side driver to generate a high side driver signal according to the PWM signal to drive the high side MOSFET; and/or adaptively delays the high side driver signal according to the output current to generate a low side enable signal for enabling the low side driver to generate the low side driver signal according to the PWM signal to drive the low side MOSFET, so as to adaptively control a dead time which is a time period when the high side MOSFET and the low side MOSFET are both not conductive.

Description

Switching converter circuit and drive circuit with adaptive dead time therein

The present invention relates to a switching converter circuit, in particular to a switching converter circuit with adaptive dead time and avoiding short-circuit current. The invention also relates to a driver circuit in a switching converter circuit.

FIG. 1A shows a schematic circuit diagram of a prior art switching converter circuit 10 . The switching converter circuit 10 includes a driving circuit 11 and a power stage circuit 12 . As shown in the figure, the power stage circuit 12 includes an upper bridge switch 121 , a lower bridge switch 122 and an inductor 123 . The driving circuit 11 generates an up-bridge signal UG and a down-bridge signal LG according to a pulse width modulation (PWM) signal P1. The upper bridge switch 121 and the lower bridge switch 122 respectively operate according to the upper bridge signal UG and the lower bridge signal LG to convert the input voltage Vin to the output voltage Vout and generate an inductor current IL to flow through the inductor 123 of the power stage circuit 12 .

In the switching converter circuit 10 shown in FIG. 1A , the power stage circuit 12 is a step-down power stage circuit. During normal operation, the upper bridge switch 121 and the lower bridge switch 122 are turned on in turn to switch the end of the inductor 123 electrically connected to the phase node LX between the input voltage Vin and the ground potential GND, so that the inductor current IL is between the following two The current channels are alternately switched: one is from the input voltage Vin flowing through the upper bridge switch 121 to the phase node LX and then flowing through the inductor L to the output terminal; the other is from the ground potential GND flowing through the lower bridge switch 122 to the phase node LX and then Flow through the inductor L to the output. In normal operation, the upper bridge switch 121 and the lower bridge switch 122 must avoid being turned on at the same time, so as to avoid circuit shoot through and cause circuit damage. Therefore, a dead time in which both the upper bridge switch 121 and the lower bridge switch 122 are off is required to separate the conduction periods of the upper bridge switch 121 and the lower bridge switch 122 .

FIG. 1B shows a schematic circuit diagram of a driving circuit 11 in the prior art. As shown in FIG. 1B , the driving circuit 11 includes latch circuits 111 and 112 , a level shift circuit 113 , an inverter 114 , delay circuits 115 and 116 and other complex inverters. Among them, the PWM signal P1 is used as the reset signal of the latch circuit 111. When the PWM signal P1 is at a low potential, the latch circuit 111 outputs a high potential. The upper bridge signal UG is at low potential, and the upper bridge switch 121 is not turned on. When the PWM signal P1 turns to a high potential, it is necessary to determine whether to turn the up-bridge signal UG into a high potential according to the output signal of the delay circuit 116 to turn on the up-bridge switch 121 .

On the other hand, the PWM signal P1 passes through the inverter 114, and its inverted signal is used as a reset signal for the latch circuit 112. When the PWM signal P1 is at a high potential, the latch circuit 112 outputs a high potential and passes through three inverters. The generated low-bridge signal LG is low, and the low-bridge switch 122 is not turned on. When the PWM signal P1 turns low, it needs to determine whether to turn the low-bridge signal LG high according to the output signal of the delay circuit 115 to turn on the high-bridge switch 121 .

The output signal of the latch circuit 111 is input to the latch circuit 112 after being delayed by the delay circuit 115 for a preset fixed bridge delay time as the setting signal of the latch circuit 112, so that the latch circuit 112 can be set according to the PWM signal P1. Invert the signal to generate the lower bridge signal LG. On the other hand, the output signal of the latch circuit 112 is input to the latch circuit 111 after being delayed by the delay circuit 116 for a predetermined and fixed low-bridge delay time as the setting signal of the latch circuit 111, so that the latch circuit 111 can be enabled. According to the PWM signal P1, an up-bridge signal UG is generated.

Wherein, the upper bridge delay time must be long enough to cover the dead time after the upper bridge switch 121 ends conducting; and the lower bridge delay time must be long enough to cover the dead time after the lower bridge switch 122 ends conducting, so as to avoid the upper bridge switch 121 and the lower bridge switch 122 are turned on at the same time. Wherein, the driving circuit 11 generates the bootstrap voltage BOOT according to the DC voltage VCC. The level shift circuit 113 shifts the level of the PWM signal P1 after passing through the latch circuit 111 to a boot voltage domain.

Also referring to FIG. 1A , in the normal operation of the switching converter circuit 10 , the dead time is fixed for a predetermined period. After the lower bridge switch 122 is turned on, after a fixed dead time, the upper bridge switch 121 is turned on. After this dead time, the parasitic diode LD in the lower bridge switch 122 is converted from a forward bias to a reverse bias . And in another dead time, after the upper bridge switch 121 finishes conduction, but the dead time before the lower bridge switch 122 is not turned on, the parasitic diode LD in the lower bridge switch 122 is converted from reverse bias to forward bias , during this dead time, the inductor current IL only flows from the ground potential GND through the parasitic diode LD in the lower bridge switch 122 to the phase node LX and then flows through the inductor L. That is to say, in a switching period between the upper bridge switch 121 and the lower bridge switch 122, during the aforementioned two dead times, the PN interface of the parasitic diode LD in the lower bridge switch 122 has two bias reversals, The electrical energy and time loss caused by reverse recovery charge (reverse recovery charge, Qrr).

In the normal operation of the switching converter circuit 10 in the prior art, the dead time must be preset as a fixed time long enough to meet the errors caused by various manufacturing processes of the electronic components and circuits in the switching converter circuit 10, resulting in different dead time requirements. That is to say, the dead time must be preset to exceed the maximum value among different dead time requirements caused by various errors, so as to avoid the simultaneous conduction of the upper bridge switch 121 and the lower bridge switch 122 . As a result, most switching converter circuits 10 that only require a relatively short dead time will generate relatively serious power and time loss of the reverse recovery charge, resulting in relatively low conversion efficiency.

Compared with the aforementioned prior art, the present invention proposes a switching converter circuit and a driving circuit therein which have adaptive dead time and can avoid the short-circuit current caused by simultaneous conduction of the upper-side switch and the lower-side switch.

In one aspect, the present invention provides a switching converter circuit for switching one terminal of an inductor between a first voltage and a second voltage according to a pulse width modulation (PWM) signal. In order to convert an input power supply into an output power supply, the switching converter circuit includes: a metal oxide semiconductor field effect transistor (MOSFET) on the upper bridge, having an N-type conductivity, coupled to Between the first voltage and the end of the inductance; a lower bridge MOSFET, with N-type conductivity, coupled between the second voltage and the end of the inductance; and a driving circuit, including: an upper bridge The driver is used to generate an upper-bridge driving signal to drive the upper-bridge MOSFET according to a PWM signal based on an upper-bridge enable signal; the lower-bridge driver is used to enable the lower-bridge enable signal to generate an upper-bridge MOSFET according to the A PWM signal for generating a lower-bridge driving signal to drive the lower-bridge MOSFET; and a dead-time control circuit for generating a dead-time signal according to an output current of the output power supply to adaptively delay the lower-bridge driving signal or its in-phase signal, and/or adaptively delay the upper bridge drive signal or its in-phase signal to generate the upper bridge enable signal and/or the lower bridge enable signal to adaptively control a dead time; wherein the empty The dead time is a period during which the high-side MOSFET and the low-side MOSFET are both off.

From another point of view, the present invention also provides a driving circuit for a switching converter circuit, including: an upper bridge driver, which is used for enabling an upper bridge driver according to a PWM signal to generate an upper bridge driver signal to drive an upper bridge MOSFET; a lower bridge driver is used to enable the lower bridge enable signal and generate a lower bridge driving signal according to the PWM signal to drive the lower bridge MOSFET; and a dead time control circuit for According to the output current of the output power supply, a dead time signal is generated to adaptively delay the lower bridge drive signal or its in-phase signal, and/or adaptively delay the upper bridge drive signal or its in-phase signal to generate the upper bridge drive signal The bridge enable signal and/or the lower bridge enable signal are used to adaptively control a dead time; wherein the upper bridge MOSFET and the lower bridge MOSFET are used to switch one end of an inductor between a first voltage and a second voltage During this period, an input power supply is converted to the output power supply; wherein the dead time is a period during which both the high-side MOSFET and the low-side MOSFET are not turned on.

In a preferred embodiment, the dead time length is inversely proportional to the output current.

In a preferred embodiment, the dead time control circuit includes a sensing MOSFET with N-type conductivity, the gate of the sensing MOSFET is coupled to the gate of the high-side MOSFET or the low-side MOSFET, the The sensing MOSFET is used to generate the dead time in a sense resistor coupled in series with the sensing MOSFET according to an upper current flowing through the upper MOSFET or a lower current flowing through the lower MOSFET. signal.

In a preferred embodiment, the dead time control circuit further includes a zener diode coupled between the gate and source of the sensing MOSFET to clamp the gate-source of the sensing MOSFET pole voltage.

In a preferred embodiment, the dead time control circuit further includes a clamping MOSFET with N-type conductivity, the clamping MOSFET is coupled in series with the sensing MOSFET, and the gate of the clamping MOSFET is coupled to A fixed voltage clamps the dead-time signal.

In a preferred embodiment, the dead time control circuit further includes a clamping MOSFET with P-type conductivity, the clamping MOSFET is coupled in series with the sensing MOSFET, and the gate of the clamping MOSFET is coupled to a bias voltage to clamp the dead-time signal, wherein: the bias voltage is a voltage of a phase node coupled between the high-side MOSFET and the low-side MOSFET; or the bias voltage is passed through At least one MOSFET diode is connected in series between an input voltage of the input power source and the gate of the clamping MOSFET.

In a preferred embodiment, the dead-time control circuit further includes an analog-to-digital converter coupled to the sensing MOSFET for converting the dead-time signal into a digital signal.

In a preferred embodiment, the dead time control circuit further includes a latch circuit coupled to the analog-to-digital converter for locking the digital bit when enabled by the high-bridge driving signal or the low-bridge driving signal signal to generate a digital latch signal.

In a preferred embodiment, the dead-time control circuit further includes a delay circuit coupled to the latch circuit for delaying the low-bridge driving signal or the high-bridge driving signal according to the digital latch signal to The up-bridge enable signal or the down-bridge enable signal is correspondingly generated to adaptively adjust the dead time.

In a preferred embodiment, the dead time control circuit further includes: a clamping MOSFET coupled in series with the sense MOSFET to clamp the dead time signal; and an amplifier, the amplifier The inverting input of the amplifier is coupled to the source of the sense MOSFET, the non-inverting input of the amplifier is coupled to the source of the high-side MOSFET, and the output of the amplifier controls the clamp MOSFET to feedback control the sense MOSFET The source of the MOSFET and the source of the high-side MOSFET have the same voltage to ensure that the operating points of the sense MOSFET and the high-side MOSFET are consistent.

In the following detailed description by means of specific embodiments, it will be easier to understand the purpose, technical content, characteristics and effects of the present invention.

The diagrams in the present invention are all schematic and mainly intended to show the coupling relationship between various circuits and the relationship between various signal waveforms. As for the circuits, signal waveforms and frequencies, they are not drawn to scale.

FIG. 2 shows a schematic diagram of a switching converter circuit 20 according to the present invention. The switching converter circuit 20 is used for switching one end of the inductor 223 (in this embodiment, the end electrically connected to the phase node LX) to the first voltage (at In this embodiment, between the input voltage Vin) and a second voltage (in this embodiment, the ground potential GND), the output power supply (including the output voltage Vout and the output current Iout), and provide power to the load circuit 23. The switching converter circuit 20 includes: a high-side metal oxide semiconductor field effect transistor (MOSFET) 221 , a low-side MOSFET 222 , an inductor 223 and a driving circuit 21 .

In this embodiment, the high-side MOSFET 221 has N-type conductivity and is coupled between the input voltage Vin and the phase node LX (the end of the inductor). The low-side MOSFET 222 has N-type conductivity and is coupled between the ground potential GND and the phase node LX (the end of the inductor). It should be noted that, in addition to the step-down power stage circuit, the present invention can also be applied to a step-up type power stage circuit and a buck-boost type power stage circuit, as long as the power stage circuit has an N-type upper-side MOSFET and an N-type lower-side MOSFET , can apply the present invention to improve the conversion efficiency and reduce the reverse recovery charge loss, only need to change the corresponding node of the inductance coupled to this end, and change the opposite node coupled to the upper-side MOSFET and the lower-side MOSFET to: input Voltage, ground potential, phase nodes, and output voltage are sufficient.

The driving circuit 21 is used to generate the PWM signal P1 according to the feedback signal related to the output voltage Vout, and then generate the upper bridge driving signal UG and the lower bridge driving signal LG, so as to operate the upper bridge MOSFET 221 and the lower bridge MOSFET 222 correspondingly, and the inductor 223 The terminal is switched between a first voltage (input voltage Vin) and a second voltage (ground potential GND). The driving circuit 21 includes: an upper bridge driver 211 , a lower bridge driver 212 and a dead time control circuit 213 .

The high-side driver 211 is used for generating the high-side drive signal UG according to the PWM signal P1 by the high-side enable signal ENH to drive the high-side MOSFET 221 . The low-side driver 212 is used for enabling the low-side enable signal ENL to generate a low-side driving signal LG according to the PWM signal P1 to drive the low-side MOSFET 222 . The dead time control circuit 213 is used to generate a dead time signal (not shown, described in detail later) according to the output current Iout of the output power supply, so as to adaptively delay the lower bridge driving signal LG or its in-phase signal, and/or Adaptively delay the upper bridge drive signal UG or its in-phase signal to generate the upper bridge enable signal ENH and/or the lower bridge enable signal ENL to adaptively control the upper bridge MOSFET221 and the lower bridge MOSFET222. time.

In a preferred embodiment, the dead time is inversely proportional to the output current Iout, the higher the output current Iout, the shorter the dead time.

FIG. 3 shows an embodiment of a driving circuit according to the present invention. As shown in FIG. 3 , the driving circuit 31 includes: an upper bridge driver 311 , a lower bridge driver 312 , a dead time control circuit 313 and a level shifting circuit 315 . Wherein, the upper-bridge driver 311 is used to enable the upper-bridge enable signal ENH to generate the upper-bridge PWM signal SH according to the same phase as the PWM signal P1 (in this embodiment, the upper-bridge PWM signal SH is the PWM signal P1). The upper bridge driving signal UG drives the upper bridge MOSFET 221 . The low-side driver 312 is used for enabling the low-side enable signal ENL to generate the low-side PWM signal SL through the inverter according to the PWM signal P1 to generate the low-side driving signal LG to drive the low-side MOSFET 222 . The dead time control circuit 313 is used to generate the dead time signal ADH according to the output current Iout of the output power supply, so as to adaptively delay the lower bridge driving signal LG or its in-phase signal, and generate the upper bridge enabling signal ENH for adaptive delay. Controlling a period of dead time during which both the upper-bridge MOSFET 221 and the lower-bridge MOSFET 222 are not turned on.

As shown in FIG. 3 , the high bridge driver 311 includes an enabling logic circuit 3111 , a level shifting circuit 314 and three inverters connected in series. The lower bridge driver 312 includes an enabling logic circuit 3121 and three inverters connected in series. The dead time control circuit 313 includes a sense MOSFET 3131 and a sense resistor 3132 . The level shifting circuit 315 shifts the level of the upper bridge driving signal UG downward to generate the lower bridge enable signal ENL, which is input to the lower bridge driver 312, so that the lower bridge driver 312 can operate according to the lower bridge enable signal ENL. When the upper bridge MOSFET221 is turned on, the lower bridge driver 312 is disabled to generate the lower bridge drive signal LG according to the lower bridge PWM signal SL; and when the upper bridge MOSFET221 is not turned on, the lower bridge driver 312 is enabled to generate the lower bridge driver 312 according to the lower bridge PWM signal SL. Drive signal LG.

Please continue to refer to FIG. 3 , the sensing MOSFET 3131 has N-type conductivity, and the gate of the sensing MOSFET 3131 is coupled to the gate of the high-side MOSFET 221 . The sense MOSFET 3131 is used to generate the dead time signal ADH in the sense resistor 3132 connected in series between the sense MOSFET 3131 and the ground potential GND according to the upper bridge current Ih flowing through the upper bridge MOSFET 221 . In a preferred embodiment, the size of the sensing MOSFET 3131 is reduced in proportion to that of the upper-bridge MOSFET 221, that is, the dimensions of the gate, source, and drain of the sensing MOSFET 3131 are equal to the gate, source, and drain of the upper-bridge MOSFET 221. The dimensions of the source and the drain are scaled down proportionally, so that the sense current Is flowing through the sense MOSFET 3131 is proportional to the high-side current Ih flowing through the high-side MOSFET 221 . In a preferred embodiment, the size ratio of the gate, source and drain of the sensing MOSFET 3131 to the gate, source and drain of the upper bridge MOSFET 221 is 1:10000.

The dead-time control circuit 313 generates a dead-time signal ADH according to the sense current Is flowing through the sense resistor 3132 , and adaptively delays the low-side driving signal LG according to the dead-time signal ADH to generate the high-side enable signal ENH. The high-side enabling signal ENH enables the high-side driver 311 to generate the high-side driving signal UG according to the high-side PWM signal SH to drive the high-side MOSFET 221 . That is to say, the dead-time signal ADH adaptively delays the low-side driving signal LG to determine the time point when the high-side enable signal ENH enables the high-side driver 311 , so as to adaptively adjust the dead-time.

The upper bridge current Ih is proportional to the output current Iout. Therefore, the sensing current Is is proportional to the output current Iout, that is, the dead time signal ADH is proportional to the output current Iout. When the output current Iout is higher, the dead time signal ADH is also higher, and the time for delaying the lower bridge driving signal LG is shorter, so that the upper bridge enabling signal ENH reaches a low level earlier, and the earlier the upper bridge driver 311 is enabled according to The upper-bridge PWM signal SH generates the upper-bridge driving signal UG to drive the upper-bridge MOSFET 221 , so the dead-time length is also shorter, so that the dead-time length is inversely proportional to the output current Iout.

In the lower bridge driver 312 shown in FIG. 3 , the enable logic circuit 3121 is, for example, an inverse-AND latch circuit as shown in FIG. 3 . Therefore, one input terminal of the enabling logic circuit 3121, such as the reset pin of the NAND latch circuit, receives the low-bridge PWM signal SL; the other terminal, for example, the setting pin of the NAND latch circuit, receives the lower Bridge enable signal ENL. The low-bridge PWM signal SL is an inverse signal to the PWM signal P1.

For example, as shown in FIG. 3 , when the high-side MOSFET 221 is turned on, it means that the low-side MOSFET 222 should not be turned on. In this case, the low-side enabling signal ENL is at a disabling level (high potential in this embodiment) to disable the low-side driver 312 so that the low-side driver 312 does not operate the low-side MOSFET 222 according to the low-side PWM signal SL. To ensure that the lower bridge MOSFET222 is not turned on.

Specifically, the bridge enable signal ENL is input to enable the logic circuit 3121 under the high potential. The enabling logic circuit 3121 is, for example, an inverse-AND latch circuit as shown in FIG. 3 . Therefore, one input terminal of the enabling logic circuit 3121, such as the reset pin of the NAND latch circuit, receives the low-bridge PWM signal SL; the other terminal, for example, the setting pin of the NAND latch circuit, receives the lower Bridge enable signal ENL.

The lower bridge PWM signal SL is a low potential representing 0, and the enable logic circuit 3121 outputs a high potential representing 1. The high potential then passes through 3 inverters to generate a lower bridge drive signal LG as a low potential, and the lower bridge MOSFET 222 does not conduction.

The lower bridge PWM signal SL changes from a low potential representing 0 to a high potential representing 1. At this time, the logic level of the lower bridge enable signal ENL is still a high potential representing 1, for example, and the enabling logic circuit 3121 outputs a high potential representing 1. , the lower bridge drive signal LG is at low potential, and the lower bridge MOSFET 222 is not turned on. That is to say, when the low-side enable signal ENL is at high potential (disable level), regardless of the logic level of the low-side PWM signal SL, the low-side driving signal LG is at low potential, and the low-side MOSFET 222 is not turned on.

On the other hand, when the high-side MOSFET 221 is not turned on, it also means that the low-side MOSFET 222 can operate according to the low-side PWM signal SL. In this case, the low-side enable signal ENL changes to an enable level (low level in this embodiment) to enable the low-side driver 312 , so that the low-side driver 312 operates the low-side MOSFET 222 according to the low-side PWM signal SL.

Specifically, the enable signal ENL of the lower bridge under low potential is input into the enabling logic circuit 3121, which is the setting pin of the NAND gate latch circuit, and the output signal of the NAND gate latch circuit is the inverse phase of the lower bridge PWM signal SL. The signal passes through three inverters to make the lower bridge drive signal LG and the lower bridge PWM signal SL in phase, and the three inverters also form a tapered buffer. That is to say, when the upper-side MOSFET 221 is not turned on, the lower-side enable signal ENL is at a low potential (enable level), and the lower-side driver 312 switches the lower-side MOSFET 222 according to the lower-side PWM signal SL which is opposite to the PWM signal P1. .

Please continue to refer to FIG. 3 , the DC voltage VCC is used to generate the bootstrap voltage BOOT of the upper bridge driver 311 . The level shift circuit 314 is used to level shift the output signal of the enable logic circuit 3111 to the boot voltage domain (boot voltage domain), so that the high-bridge driver 311 can pass the dead time signal ADH The upper bridge enabling signal ENH generated by the lower bridge driving signal LG is adaptively delayed, and the upper bridge driving signal UG is adjusted, thereby adaptively adjusting the dead time.

For example, as shown in FIG. 3, one input end of the enabling logic circuit 3111, such as the reset pin of the latch circuit, receives the high-bridge PWM signal SH; the other end is, for example, the setting of the NAND latch circuit The pin is used to receive the enable signal ENH of the upper bridge. The upper bridge PWM signal SH is in phase with the PWM signal P1. When the dead-time signal ADH rises with the increase of the output current Iout, the shorter the delay time of the lower bridge driving circuit LG is, the faster the upper bridge enable signal ENH reaches the enable level (low level in this embodiment) , and the enabling logic circuit 3111 is enabled, so that the upper-bridge driving circuit 311 generates the upper-bridge driving signal UG earlier according to the upper-bridge PWM signal SH, thereby shortening the dead time.

FIG. 4 shows a more specific embodiment of the driving circuit 31 according to the present invention. As shown in FIG. 4 , the driving circuit 31 includes: an upper bridge driver 311 , a lower bridge driver 312 , a dead time control circuit 313 and a level shifting circuit 315 . Among them, the PWM signal P1 is the upper bridge PWM signal SH, indicating that the PWM signal P1 is in phase with the upper bridge PWM signal SH; the PWM signal P1 generates the lower bridge PWM signal SL through an inverter, indicating that the PWM signal P1 and the lower bridge PWM signal SL are inverted. Mutually. The upper bridge driver 311 is enabled by the upper bridge enable signal ENH and generates an upper bridge driving signal UG according to the PWM signal P1 to drive the upper bridge MOSFET 221 . The low-side driver 312 is enabled by the low-side enable signal ENL and generates a low-side driving signal LG according to the PWM signal P1 to drive the low-side MOSFET 222 . The dead time control circuit 313 generates the dead time signal ADH according to the output current Iout of the output power supply to adaptively delay the lower bridge driving signal LG, and generates the upper bridge enable signal ENH to adaptively control the upper bridge MOSFET 221 and the lower bridge. A dead time during which none of the bridge MOSFETs 222 conduct.

As shown in FIG. 4, compared with FIG. 3, the dead time control circuit 313 of this embodiment includes a Zener diode 3133, a clamping MOSFET 3134, and an analog-to-digital converter 3135 in addition to a sensing MOSFET 3131 and a sensing resistor 3132. , a latch circuit 3136 and a delay circuit 3137. Wherein, the Zener diode 3133 is coupled between the gate and the source of the sensing MOSFET 3131 to clamp the gate-source voltage of the sensing MOSFET 3131 to prevent the sensing current Is from being too high.

Please continue to refer to FIG. 4 , the clamping MOSFET 3134 is, for example, N-type conductive, and the clamping MOSFET 3134 is coupled in series between the sensing MOSFET 3131 and the sensing resistor 3132 , and the gate of the clamping MOSFET 3134 is, for example, but not limited to, coupled to a fixed voltage Vg (such as but not limited to 5V) is used to clamp the dead-time signal ADH.

Please continue to refer to FIG. 4 , the analog-to-digital converter 3135 is coupled in series between the sensing MOSFET 3131 and the latch circuit 3136 for converting the dead-time signal ADH into a digital signal DGT for input to the latch circuit 3136 .

Please continue to refer to FIG. 4 , the latch circuit 3136 is coupled to the analog-to-digital converter 3135 , and is enabled according to the upper bridge driving signal UG to latch the digital signal DGT to generate a digital latch signal DGL.

Please continue to refer to FIG. 4, the delay circuit 3137 is coupled in series with the latch circuit 3136, and is used to delay the low-side drive signal LG according to the digital latch signal DGL to generate the high-side enable signal ENH for inputting the enable logic circuit 3111, while the adaptive delay adjusts the dead time.

For example, when the low-side drive signal LG is low, it means that the low-side MOSFET 222 is not turned on, and the delay circuit 3137 adaptively delays the low-side drive signal LG for a period of time according to the digital latch signal DGL to generate the high-side enable signal ENH , so as to enable the logic circuit 3111 . When the output current Iout is higher, the dead time signal ADH is also higher, and the digital latch signal DGL is higher, and the delay circuit 3137 delays the lower bridge driving signal LG. The PWM signal SH operates the upper bridge MOSFET221, so the dead time is shorter

In this embodiment, the function of the latch circuit 3136 is similar to a memory circuit for latching (memorizing) the digital signal DGT to generate a digital latch signal DGL (locked digital signal DGT). The falling edge of the upper bridge drive signal UG latches (memorizes) the digital latch signal DGT in the latch circuit 3136 to generate a digital latch signal DGL (locked digital latch signal DGT), so that later, When the driving signal LG of the lower bridge changes from a high potential (and the driving signal UG of the upper bridge is already a low potential) to a low potential (the driving signal UG of the upper bridge has not yet changed to a high potential), it will be based on the output current Iout and remain in the The digital latch signal DGT of the latch circuit 3136 determines the duration of the delay of the lower bridge driving signal LG.

Apart from that, the rest of this embodiment is the same as the embodiment shown in FIG. 3 , please refer to the description of FIG. 3 .

FIG. 5 shows another more specific embodiment of the driving circuit 31 according to the present invention. As shown in FIG. 5 , the driving circuit 31 includes: an upper bridge driver 311 , a lower bridge driver 312 , a dead time control circuit 313 and a level shifting circuit 315 . Among them, the PWM signal is the upper-bridge PWM signal SH, indicating that the PWM signal P1 is in phase with the upper-bridge PWM signal SH; the PWM signal P1 generates the lower-bridge PWM signal SL through an inverter, indicating that the PWM signal P1 and the lower-bridge PWM signal SL are out of phase . The upper bridge driver 311 is used for generating the upper bridge driving signal UG according to the PWM signal P1 to drive the upper bridge MOSFET 221 . The lower bridge driver 312 is used for generating a lower bridge driving signal LG according to the PWM signal P1 to drive the lower bridge MOSFET 222 . The dead time control circuit 313 is used to generate the dead time signal ADH according to the output current Iout of the output power supply, so as to adjust the driving signal UG of the upper bridge, and adaptively control a period of dead time when both the upper bridge MOSFET 221 and the lower bridge MOSFET 222 are non-conductive. time.

The difference between this embodiment and the embodiment shown in FIG. 4 is that, in this embodiment, the clamping MOSFET 3134 has, for example, a P-type conductivity type, and the clamping MOSFET 3134 is coupled in series with the sensing MOSFET 3131, and the gate of the clamping MOSFET 3134 It is coupled to a bias voltage to clamp the dead time signal ADH. In a preferred embodiment, as shown in FIG. 5, the bias voltage is the voltage of the phase node LX, and the phase node LX is coupled to the upper bridge Between MOSFET221 and lower bridge MOSFET222. This embodiment omits the zener diode 3133 shown in FIG. The dead time signal ADH is too high. In addition, in this embodiment, the drain of the sensing MOSFET 3131 is electrically connected to the input voltage Vin, while in the embodiment shown in FIG. 4 , the drain of the sensing MOSFET 3131 is electrically connected to the bootstrap voltage BOOT. Apart from that, the rest of this embodiment is the same as the embodiment shown in FIG. 4 , please refer to the description of FIG. 4 .

FIG. 6 shows another more specific embodiment of the driving circuit 31 according to the present invention. As shown in FIG. 6 , the driving circuit 31 includes: an upper bridge driver 311 , a lower bridge driver 312 , a dead time control circuit 313 and a level shifting circuit 315 . Among them, the PWM signal is the upper-bridge PWM signal SH, indicating that the PWM signal P1 is in phase with the upper-bridge PWM signal SH; the PWM signal P1 generates the lower-bridge PWM signal SL through an inverter, indicating that the PWM signal P1 and the lower-bridge PWM signal SL are out of phase . The upper bridge driver 311 is used for generating the upper bridge driving signal UG according to the PWM signal P1 to drive the upper bridge MOSFET 221 . The lower bridge driver 312 is used for generating a lower bridge driving signal LG according to the PWM signal P1 to drive the lower bridge MOSFET 222 . The dead time control circuit 313 is used to generate the dead time signal ADH according to the output current Iout of the output power supply, so as to adjust the driving signal UG of the upper bridge, and adaptively control a period of dead time when both the upper bridge MOSFET 221 and the lower bridge MOSFET 222 are non-conductive. time.

The difference between this embodiment and the embodiment shown in FIG. 5 is that, in this embodiment, the clamping MOSFET 3134 has, for example, a P-type conductivity type, and the clamping MOSFET 3134 is coupled in series with the sensing MOSFET 3131, and the gate of the clamping MOSFET 3134 Coupled to a bias voltage to clamp the dead time signal ADH, in a preferred embodiment, as shown in Figure 6, the bias voltage is connected to the input voltage Vout of the input power supply through at least one MOSFET diode connected in series It is generated between the gate of clamp MOSFET3134. The number of MOSFET diodes is not limited to three as shown in FIG. 6 , and can also be a single one, or other numbers can be connected in series to provide the bias voltage. Apart from that, the rest of this embodiment is the same as the embodiment shown in FIG. 5 , please refer to the description of FIG. 5 .

FIG. 7 shows another more specific embodiment of the driving circuit 31 according to the present invention. As shown in FIG. 7 , the driving circuit 31 includes: an upper bridge driver 311 , a lower bridge driver 312 , a dead time control circuit 313 and a level shifting circuit 315 . Among them, the PWM signal is the upper-bridge PWM signal SH, indicating that the PWM signal P1 is in phase with the upper-bridge PWM signal SH; the PWM signal P1 generates the lower-bridge PWM signal SL through an inverter, indicating that the PWM signal P1 and the lower-bridge PWM signal SL are out of phase . The upper bridge driver 311 is used for generating the upper bridge driving signal UG according to the PWM signal P1 to drive the upper bridge MOSFET 221 . The lower bridge driver 312 is used for generating a lower bridge driving signal LG according to the PWM signal P1 to drive the lower bridge MOSFET 222 . The dead time control circuit 313 is used to generate the dead time signal ADH according to the output current Iout of the output power supply, so as to adjust the driving signal UG of the upper bridge, and adaptively control a period of dead time when both the upper bridge MOSFET 221 and the lower bridge MOSFET 222 are non-conductive. time.

The difference between this embodiment and the embodiment shown in FIG. 6 is that, in this embodiment, the dead time control circuit 313 further includes an amplifier 3138, the inverting input terminal of which is coupled to the source of the sensing MOSFET 3131, and its non- The inverting input terminal is coupled to the source of the high-side MOSFET 221, and the output terminal of the amplifier 3138 controls the clamp MOSFET 3134 to feedback control the source of the sense MOSFET 3131 and the source of the high-bridge MOSFET 221 to have the same voltage to ensure the sense The operating points of the sensing MOSFET 3131 and the high-side MOSFET 221 are consistent, forming the effect of a current mirror circuit, even though the sensing MOSFET 3131 and the high-side MOSFET 221 operate in the linear region. It should be noted that, in this embodiment, the clamp MOSFET 3134 is a P-type MOSFET. According to the present invention, the clamping MOSFET 3134 can also be an N-type MOSFET, and the inverting input terminal of the amplifier 3138 needs to be coupled to the source of the high-side MOSFET 221, and the non-inverting input terminal of the amplifier 3138 is coupled to the source of the sensing MOSFET 3131. Can. Apart from that, the rest of this embodiment is the same as the embodiment shown in FIG. 6 , please refer to the description of FIG. 6 .

FIG. 8 shows a more specific embodiment of the delay circuit 3137 according to the present invention. As shown in FIG. 8 , the delay circuit 3137 receives the digital latch signal DGL and delays the lower bridge driving signal LG. Wherein, the digital latch signal DGL is positively related to the dead time. As shown in Figure 8, when the lower bridge driving signal LG changes from high potential to low potential, the transistor Q0 of the delay circuit 3137 is turned on, and the current provided by the transistor Q11 and the transistors Q20-Q2n is added to charge the capacitor Cd , and then through an inverter, the upper bridge enable signal ENH is generated. Wherein, the currents provided by the transistors Q20-Q2n are respectively adjusted by corresponding digital bit signals DT<0>-DT<n>. Wherein, the digital bit signals DT<0>-DT<n> are complex bits corresponding to the digital latch signal DGL. In a preferred implementation, the higher the dead-time signal ADH, the greater the value of the digital latch signal DGL, and the greater the current provided by the transistors Q20-Q2n, so that the summed current is greater. The higher the voltage generated after the capacitor Cd is charged, the lower the delay signal DAH will be after passing through the inverter, so that the upper bridge enable signal ENH will reach a low potential sooner so that the upper bridge driver 311 can drive the upper bridge according to the PWM signal P1. The bridge MOSFET 221 makes the dead time adaptively shortened.

FIG. 9 shows another more specific embodiment of the driving circuit 31 according to the present invention. As shown in FIG. 9 , the driving circuit 31 includes: an upper bridge driver 311 , a lower bridge driver 312 , a dead time control circuit 313 and a level shifting circuit 315 . Among them, the PWM signal P1 is the upper bridge PWM signal SH, indicating that the PWM signal P1 is in phase with the upper bridge PWM signal SH; the PWM signal P1 generates the lower bridge PWM signal SL through an inverter, indicating that the PWM signal P1 and the lower bridge PWM signal SL are inverted. Mutually. The upper bridge driver 311 is enabled by the upper bridge enable signal ENH and generates an upper bridge driving signal UG according to the PWM signal P1 to drive the upper bridge MOSFET 221 . The low-side driver 312 is enabled by the low-side enable signal ENL, and generates a low-side driving signal LG according to the low-side PWM signal SL, which is the opposite phase of the PWM signal P1, to drive the low-side MOSFET 222 . The dead time control circuit 313 generates the dead time signal ADL according to the output current Iout of the output power supply to adaptively delay the upper bridge offset signal SG which is in phase with the upper bridge drive signal UG to generate the lower bridge enable signal ENL, A period of dead time during which both the high-side MOSFET 221 and the low-side MOSFET 222 are not turned on is adaptively controlled. Wherein, the level offset circuit shifts the level of the upper-bridge driving signal UG downward to generate the upper-bridge offset signal SG, so that the dead time control circuit 313 can process the upper-bridge offset signal in phase with the upper-bridge driving signal UG. Shift signal SG.

As shown in FIG. 9 , different from the previous embodiments, in the dead time control circuit 313 of this embodiment, the sense MOSFET 3131 is used to output current Iout according to the current flow through the lower bridge MOSFET 222. The current Ilo generates a dead-time signal ADL at the sensing resistor 3132 connected in series between the sensing MOSFET 3131 and the DC voltage VCC. In a preferred embodiment, the size of the sensing MOSFET 3131 is reduced in proportion to that of the lower-bridge MOSFET 222, that is, the dimensions of the gate, source and drain of the sensing MOSFET 3131 are equal to the gate, source, and drain of the lower-bridge MOSFET 222. The dimensions of the source and the drain are scaled down proportionally so that the sense current Is flowing through the sense MOSFET 3131 is proportional to the low bridge current Ilo flowing through the low bridge MOSFET 222 . In a preferred embodiment, the size ratio of the gate, source and drain of the sensing MOSFET 3131 to the gate, source and drain of the lower bridge MOSFET 222 is 1:10000.

Besides the sensing MOSFET 3131 and the sensing resistor 3132 , it further includes a Zener diode 3133 , a clamping MOSFET 3134 , an analog-to-digital converter 3135 , a latch circuit 3136 and a delay circuit 3137 . Wherein, the Zener diode 3133 is coupled between the gate and the source of the sensing MOSFET 3131 to clamp the gate-source voltage of the sensing MOSFET 3131 to prevent the sensing current Is from being too high.

Please continue to refer to FIG. 9 , the dead time control circuit 313 generates a dead time signal ADL according to the sense current Is flowing through the sensing resistor 3132, and adaptively delays the upper phase of the upper bridge drive signal UG according to the dead time signal ADL. The bridge shifts the signal SG to generate the lower bridge enable signal ENL. The low-side enabling signal ENL enables the low-side driver 312 to generate a low-side driving signal LG to drive the low-side MOSFET 222 according to the low-side PWM signal SL. That is to say, the dead-time signal ADL adaptively delays the upper-side offset signal SG which is in phase with the upper-side driving signal UG to determine the time point when the lower-side enable signal ENL enables the lower-side driver 312 , and adaptively adjusts dead time.

The lower bridge current Ilo is proportional to the output current Iout. Therefore, the sensing current Is is proportional to the output current Iout, that is, the dead time signal ADL is proportional to the output current Iout. When the output current Iout is higher, the dead time signal ADL is also higher, and the time for delaying the upper bridge offset signal SG is shorter, so that the lower bridge enabling signal ENL reaches a low level earlier, and the lower bridge driver 312 is enabled earlier. The low-side driving signal UG is generated according to the low-side PWM signal SL to drive the low-side MOSFET 222 , so the dead time is also shorter, and the dead time is inversely proportional to the output current Iout.

The present invention has been described above with reference to preferred embodiments, but the above description is only for making those skilled in the art easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. The various embodiments described are not limited to single application, and can also be used in combination. For example, two or more embodiments can be used in combination, and some components in one embodiment can also be used to replace another embodiment. corresponding components. For example, the upper bridge driver 311 shown in FIG. 3 to FIG. 6 can also be applied to the lower bridge driver 312 correspondingly, only needing to sense the lower bridge current and adjust the upper bridge enable signal, the lower bridge enable signal, The dead time signal has a corresponding relationship with the lower bridge current, and the upper bridge driver 311 can be changed correspondingly. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the term "processing or computing according to a certain signal or generating a certain output result" in the present invention is not limited to According to the signal itself, it also includes performing voltage-current conversion, current-voltage conversion, and/or ratio conversion on the signal when necessary, and then processing or computing the converted signal to generate a certain output result. It can be seen that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which will not be listed here. Accordingly, the scope of the invention should encompass the above and all other equivalent variations.

10, 20: Switched Converter Circuit 11, 21, 31: Drive circuit 12: Power stage circuit 23: Load circuit 111, 112, 3136: Latch circuits 113, 314, 315: Level offset circuit 114: Inverter 115, 116: delay circuit 121: Upper bridge switch 122: Lower bridge switch 123, 223: Inductance 211, 311: Upper bridge driver 213, 313: Dead Time Control Circuit 212, 312: Lower side driver 221: High side MOSFET 222: Lower side MOSFET 3111, 3121 : enable logic circuit 3132: Sense Resistor 3133: Zener Diode 3134: Clamp MOSFET 3135: Analog to Digital Converter 3137: Delay Circuit 3138: Amplifier ADH, ADL: dead time signal BOOT: bootstrap voltage DGL: Digital Latch Signal DGT: digital signal DT<0>-DT<n>: digital bit signal ENH: Upper bridge enable signal ENL: Lower bridge enable signal GND: ground potential Iin: input current Ih: Upper bridge current IL: inductor current Ilo: lower bridge current Iout: output current Is: sense current LD: parasitic diode LG: Lower bridge signal LX: phase node P1: PWM signal Q0, Q11, Q20-Q2n: Transistors SG: upper bridge offset signal SH: High bridge PWM signal SL: Lower bridge PWM signal VCC: DC voltage Vin: input voltage Vg: fixed voltage Vout: output voltage UG: Upper bridge signal

FIG. 1A shows a schematic diagram of a prior art switching converter circuit 10 .

FIG. 1B shows a schematic circuit diagram of a driving circuit 11 in the prior art.

FIG. 2 shows a schematic diagram of a switching converter circuit 20 according to the present invention.

FIG. 3 shows an embodiment of a driving circuit 31 according to the present invention.

FIG. 4 shows a more specific embodiment of the driving circuit 31 according to the present invention.

FIG. 5 shows another more specific embodiment of the driving circuit 31 according to the present invention.

FIG. 6 shows another more specific embodiment of the driving circuit 31 according to the present invention.

FIG. 7 shows another more specific embodiment of the driving circuit 31 according to the present invention.

FIG. 8 shows a more specific embodiment of the delay circuit 3137 according to the present invention.

FIG. 9 shows another more specific embodiment of the driving circuit 31 according to the present invention.

20: Switched Converter Circuit 21: Drive circuit 23: Load circuit 211: Upper bridge driver 212: Lower bridge driver 213: Dead Time Control Circuit 221: High side MOSFET 222: Lower side MOSFET 223: Inductance ENH: Upper bridge enable signal ENL: Lower bridge enable signal GND: ground potential IL: inductor current Iout: output current LG: Lower bridge signal LX: phase node P1: PWM signal Vin: input voltage Vout: output voltage UG: Upper bridge signal

Claims (18)

A switching converter circuit for switching one end of an inductor between a first voltage and a second voltage according to a pulse width modulation (PWM) signal to convert an input power supply to an output The power supply, the switching converter circuit includes: a metal oxide semiconductor field effect transistor (MOSFET) on the upper side, with N-type conductivity, coupled to the first voltage and the inductor between the ends; the lower bridge MOSFET has N-type conductivity, coupled between the second voltage and the end of the inductance; and a drive circuit, including: an upper bridge driver, used for being enabled by an upper bridge The signal is enabled to generate an upper bridge drive signal according to a PWM signal to drive the upper bridge MOSFET; the lower bridge driver is used to enable the lower bridge enable signal to generate a lower bridge drive signal according to the PWM signal to driving the lower bridge MOSFET; and a dead time control circuit for generating a dead time signal according to an output current of the output power supply to adaptively delay the lower bridge driving signal or its in-phase signal, and/or adaptively Delaying the upper bridge drive signal or its in-phase signal to generate the upper bridge enable signal and/or the lower bridge enable signal to adaptively control a dead time; wherein the dead time is the upper bridge MOSFET and the lower bridge A period during which the bridge MOSFETs are not turned on; wherein the dead time control circuit includes a sense MOSFET with N-type conductivity, and the gate of the sense MOSFET is coupled to the gate of the upper bridge MOSFET or the lower bridge MOSFET , the sense MOSFET is used according to the high-side current flowing through one of the high-side MOSFETs or the current The dead-time signal is generated through a low-side current of the low-side MOSFET to a sense resistor coupled in series with the sense MOSFET. The switch-mode converter circuit as claimed in claim 1, wherein the dead time length is inversely proportional to the output current. The switching converter circuit as described in Claim 1, wherein the dead time control circuit further includes a Zener diode coupled between the gate and source of the sense MOSFET to clamp the sense MOSFET. Measure the gate-source voltage of MOSFET. The switching converter circuit as described in claim 1, wherein the dead time control circuit further includes a clamping MOSFET with N-type conductivity, the clamping MOSFET is coupled in series with the sensing MOSFET, and the clamping MOSFET The gate is coupled to a constant voltage to clamp the dead-time signal. The switching converter circuit as described in claim 1, wherein the dead time control circuit further includes a clamping MOSFET having a P-type conductivity, the clamping MOSFET is coupled in series with the sensing MOSFET, and the clamping MOSFET The gate is coupled to a bias voltage to clamp the dead time signal, wherein: the bias voltage is a voltage of a phase node coupled between the upper MOSFET and the lower MOSFET; Or the bias voltage is generated by connecting at least one MOSFET diode in series between an input voltage of the input power supply and the gate of the clamping MOSFET. The switching converter circuit as claimed in claim 1, wherein the dead-time control circuit further includes an analog-to-digital converter coupled to the sense MOSFET for converting the dead-time signal into a digital signal. The switching converter circuit as described in claim 6, wherein the dead time control circuit further includes a latch circuit coupled to the analog-to-digital converter for receiving the upper bridge drive signal or the lower bridge drive signal Enable and latch the digital signal to generate a digital latch signal. The switching converter circuit as described in claim 7, wherein the dead time control circuit further includes a delay circuit coupled to the latch circuit for delaying the lower bridge drive signal or the digital latch signal according to the digital latch signal The upper bridge driving signal is correspondingly generated to the upper bridge enable signal or the lower bridge enable signal, so as to adaptively adjust the dead time. The switching converter circuit as described in claim 1, wherein the dead time control circuit further includes: a clamping MOSFET coupled in series with the sense MOSFET to clamp the dead time signal; and an amplifier, the inverting input of the amplifier is coupled to the source of the sense MOSFET, the non-inverting input of the amplifier is coupled to the source of the high-side MOSFET, and the output of the amplifier controls the clamping MOSFET to The source of the feedback control sense MOSFET and the source of the high-side MOSFET have the same voltage to ensure that the operating points of the sense MOSFET and the high-side MOSFET are consistent. A drive circuit for a switching converter circuit, comprising: an upper bridge driver, which is used for enabling an upper bridge enable signal to generate an upper bridge driving signal according to a PWM signal to drive an upper bridge MOSFET; The driver is used to enable the lower bridge enable signal to generate a lower bridge driving signal according to the PWM signal to drive the lower bridge MOSFET; and a dead time control circuit is used to generate an output current according to an output power supply. A dead time signal to adaptively delay the lower bridge drive signal or its in-phase signal, and/or adaptively delay the upper bridge drive signal or its in-phase signal to generate the upper bridge enable signal and/or the lower bridge enable signal signal to adaptively control a dead time; Wherein the upper bridge MOSFET and the lower bridge MOSFET are used to switch one end of an inductor between a first voltage and a second voltage to convert an input power supply to the output power supply; wherein the dead time is the upper bridge MOSFET A period of non-conduction with the lower bridge MOSFET; wherein the dead time control circuit includes a sense MOSFET with N-type conductivity, and the gate of the sense MOSFET is coupled to the upper bridge MOSFET or the lower bridge MOSFET The gate of the sense MOSFET is used to connect in series with a sense resistor of the sense MOSFET according to an upper bridge current flowing through the upper bridge MOSFET or a lower bridge current flowing through the lower bridge MOSFET, The dead-time signal is generated. The driving circuit according to claim 10, wherein the dead time is inversely proportional to the output current. The driving circuit as described in claim 10, wherein the dead time control circuit further includes a Zener diode coupled between the gate and source of the sensing MOSFET to clamp the sensing MOSFET Gate-Source Voltage. The drive circuit as described in claim 10, wherein the dead time control circuit further includes a clamp MOSFET with N-type conductivity, the clamp MOSFET is coupled in series with the sense MOSFET, and the gate of the clamp MOSFET Coupled to a constant voltage to clamp the dead-time signal. The driving circuit as described in claim item 10, wherein the dead time control circuit further includes a clamping MOSFET having a P-type conductivity, the clamping MOSFET is coupled in series with the sensing MOSFET, and the gate of the clamping MOSFET coupled to a bias voltage to clamp the dead-time signal, wherein: the bias voltage is the voltage of a phase node coupled between the high-side MOSFET and the low-side MOSFET; or The bias voltage is generated by connecting at least one MOSFET diode in series between an input voltage of the input power source and the gate of the clamping MOSFET. The driving circuit according to claim 10, wherein the dead time control circuit further includes an analog-to-digital converter coupled to the sensing MOSFET for converting the dead time signal into a digital signal. The driving circuit as described in claim 15, wherein the dead time control circuit further includes a latch circuit coupled to the analog-to-digital converter for being enabled by the upper bridge driving signal or the lower bridge driving signal The digital signal is latched to generate a digital latch signal. The drive circuit as described in claim 16, wherein the dead time control circuit further includes a delay circuit coupled to the latch circuit for delaying the lower bridge drive signal or the upper bridge drive signal according to the digital latch signal The driving signal is generated correspondingly to the upper bridge enable signal or the lower bridge enable signal, so as to adaptively adjust the dead time. The driving circuit as described in claim 10, wherein the dead time control circuit further includes: a clamping MOSFET coupled in series with the sense MOSFET to clamp the dead time signal; and an amplifier , the inverting input of the amplifier is coupled to the source of the sense MOSFET, the non-inverting input of the amplifier is coupled to the source of the high-side MOSFET, and the output of the amplifier controls the clamp MOSFET for feedback control The source of the sense MOSFET and the source of the high-side MOSFET have the same voltage to ensure that the operating points of the sense MOSFET and the high-side MOSFET are consistent.

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