TWI780908B - Ring oscillator circuit and information processing device - Google Patents

Abstract

The present invention mainly discloses a ring oscillator circuit, which basically includes a first bias unit, a second bias unit and a ring oscillator unit, wherein the first bias unit generates a first bias according to a power supply voltage setting voltage and a second bias voltage, and the second bias unit generates a first working voltage and a second working voltage according to the power supply voltage and the first bias voltage. In addition, the ring oscillator unit is coupled to the power supply voltage and the ground terminal, and is simultaneously coupled to the second bias voltage transmitted from the first bias unit and the first working voltage transmitted from the second bias unit. voltage and the second operating voltage. According to the design of the present invention, the ring oscillator unit includes N cascaded inverters, and the first operating voltage supplies power to a first bias terminal of each of the inverters, and the second operating voltage The voltage is then supplied to a second bias terminal of each of the inverters. Designed in this way, each of the inverters is not biased by the power supply voltage of the electronic chip, so the frequency of the clock signal output by the Nth inverter is not affected by the power supply voltage and temperature, thereby maintaining the frequency of the clock signal. Stablize.

Description

Ring oscillator circuit and information processing device

The invention relates to the technical field of oscillators, in particular to a ring oscillator circuit with low temperature drift coefficient and low power supply drift coefficient.

It is known that an electronic oscillator is a special electronic circuit used to generate a periodic analog signal (such as a sine wave, a square wave, or a triangle wave), and has been widely used in integrated circuit chips (ie , electronic chip), to provide a clock signal, so that the circuit units in the electronic chip work together according to the clock signal.

·········································· (a) FIG. 1 shows a circuit topology diagram of a conventional ring oscillator (Ring oscillator) circuit. As shown in FIG. 1, electronic engineers know that the known ring oscillator circuit 1a includes N cascaded inverters 11a, where N is an odd number greater than or equal to 3, and the first inverter 11a is connected to the first inverter 11a. N inverters 11a are cascaded end to end. When the Barkhausen criterion is met, the ring oscillator circuit 1a starts to oscillate and outputs a clock signal CLK. And, the frequency of the clock signal CLK can be represented by the following formula (a):

···································(a)

································ (b) In the above formula (a), N is the number of the inverters 11a, and Td is the delay time of a single inverter 11a. In more detail, as shown in FIG. 1 , the inverter 11 a includes a P-type MOSFET element 111 a and an N-type MOSFET element 112 a stacked on each other. Therefore, the frequency of the clock signal CLK can be represented by the following formula (b):

·····························(b)

In the above formula (b), Ceff is the equivalent capacitance of the input and output nodes of the inverter 11a, VDD is the first power supply voltage (usually high voltage) of the electronic chip, and VSS is the second power supply voltage of the electronic chip (usually is ground or a low voltage relative to VDD), and I is the operating current of the inverter 11a. Furthermore, it can be found from equations (a) and (b) that the drift of the operating voltage (or power supply voltage) and operating current will definitely have a significant impact on the frequency of the clock signal CLK. It is worth noting that when the electronic chip is working, due to the influence of signal coupling, noise, chip self-heating, etc., the operating voltage and operating temperature will inevitably change, which will cause the frequency of the clock signal CLK to shift, making the chip The circuit units in the electronic chip cannot work together perfectly, resulting in abnormal operation of the electronic chip.

From the above description, it can be seen that there is an urgent need in the art for a ring oscillator circuit with low temperature drift coefficient and low power supply drift coefficient.

The main object of the present invention is to provide a ring oscillator circuit, which basically includes a first bias unit, a second bias unit and a ring oscillator unit, wherein the first bias unit generates a The first bias voltage and a second bias voltage, and the second bias unit generates a first operating voltage and a second operating voltage according to the power supply voltage and the first bias voltage. In addition, the ring oscillator unit is coupled to the power supply voltage and the ground terminal, and is simultaneously coupled to the second bias voltage transmitted from the first bias unit and the first working voltage transmitted from the second bias unit. voltage and the second operating voltage. According to the design of the present invention, the ring oscillator unit includes N cascaded inverters, and the first operating voltage supplies power to a first bias terminal of each of the inverters, and the second operating voltage The voltage is then supplied to a second bias terminal of each of the inverters. Designed in this way, each of the inverters is not biased by the power supply voltage of the electronic chip, so the frequency of the clock signal output by the Nth inverter is not affected by the power supply voltage and temperature, thereby maintaining the frequency of the clock signal. Stablize.

To achieve the above object, the present invention proposes an embodiment of the ring oscillator circuit, which includes:

a first bias unit, coupled to a power supply voltage and a ground terminal, for generating a first bias voltage and a second bias voltage;

a second bias unit, coupled to the first bias voltage transmitted from the first bias unit, the power supply voltage and the ground terminal, for generating a first operating voltage and a second operating voltage; and

A ring oscillator unit, coupled to the second bias voltage transmitted from the first bias unit, the first operating voltage and the second operating voltage transmitted from the second bias unit, the power supply voltage, and The ground terminal, and includes N cascaded inverters, where N is an odd number greater than or equal to 3, and the first inverter is cascaded end-to-end with the Nth inverter;

Wherein, the first working voltage is supplied to a first bias terminal of each of the inverters, and the second working voltage is supplied to a second bias terminal of each of the inverters.

In one embodiment, the ring oscillator circuit of the present invention further includes: a startup unit coupled to the power supply voltage and the ground terminal for starting the first bias unit.

In one embodiment, the second bias unit includes:

A first P-type MOSFET element, one source end of which is coupled to the power supply voltage, and one gate end of which is coupled to the first bias voltage;

A first N-type MOSFET element, a drain end of which is coupled to a drain end of the first P-type MOSFET element, and a source end of which is coupled to the ground end; wherein, the drain end of the first N-type MOSFET element Also coupled to one gate terminal;

A second P-type MOSFET element, one source end of which is coupled to the power supply voltage, and one gate end of which is coupled to the first bias voltage; and

A second N-type MOSFET element, a drain end of which is coupled to a drain end of the second P-type MOSFET element, and a source end of which is coupled to the ground end; wherein, the drain end of the second N-type MOSFET element Also couple to one of its gate terminals.

In one embodiment, the startup unit includes:

A third P-type MOSFET element, one source end of which is coupled to the power supply voltage, and one gate end of which is coupled to the ground end through a first resistor;

A third N-type MOSFET element, a drain end of which is coupled to a drain end of the third P-type MOSFET element, and a source end of which is coupled to the ground end;

A fourth P-type MOSFET element, one source terminal of which is coupled to the power supply voltage;

A fourth N-type MOSFET element, one drain end of which is coupled to a drain end of the fourth P-type MOSFET element, one source end thereof is coupled to the ground end, and one gate end thereof is coupled to the third N-type MOSFET element a gate terminal of the fourth N-type MOSFET element; wherein, the drain terminal of the fourth N-type MOSFET element is also coupled to the gate terminal thereof; and

A fifth N-type MOSFET element, one drain end is coupled to a gate end of the fourth P-type MOSFET element, one source end is coupled to the ground end, and one gate end is coupled to the third P-type MOSFET element A first common point between the drain terminal of the third N-type MOSFET element and the drain terminal of the third N-type MOSFET element.

In a feasible embodiment, the first bias unit includes:

a fifth P-type MOSFET element, one source end of which is coupled to the power supply voltage;

A sixth N-type MOSFET element, one drain end of which is coupled to a drain end of the fifth P-type MOSFET element, one source end thereof is coupled to the ground end, and one gate end thereof is coupled to the drain end thereof;

A sixth P-type MOSFET element, one source end of which is coupled to the power supply voltage, and one gate end of which is coupled to a gate end of the fifth P-type MOSFET element; wherein, the drain end of the fifth N-type MOSFET element is connected to the A second common point between the gate terminals of the fourth P-type MOSFET element is coupled to the gate terminal between the gate terminal of the sixth P-type MOSFET element and the gate terminal of the fifth P-type MOSFET element. a third common point, and a drain end of the sixth P-type MOSFET element is coupled to the third common point;

At least one seventh N-type MOSFET element, wherein a drain end of each of the seventh N-type MOSFET elements is coupled to the drain end of the sixth P-type MOSFET element, and a source end thereof is coupled to the drain end through a second resistor connected to the ground terminal; wherein, a gate terminal of each seventh N-type MOSFET element is coupled to the gate terminal of the sixth N-type MOSFET element.

In another feasible embodiment, the first bias unit includes:

a fifth P-type MOSFET element, one source end of which is coupled to the power supply voltage;

A sixth P-type MOSFET element, one source end of which is coupled to the power supply voltage, and one gate end of which is coupled to a gate end of the fifth P-type MOSFET element; wherein, the drain end of the fifth N-type MOSFET element is connected to the A second common point between the gate terminals of the fourth P-type MOSFET element is coupled to the gate terminal between the gate terminal of the sixth P-type MOSFET element and the gate terminal of the fifth P-type MOSFET element. - a third common contact;

An operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and is coupled to a drain terminal of the sixth P-type MOSFET element with its positive input terminal, and coupled to the sixth P-type MOSFET element with its negative input terminal. a drain end of the fifth P-type MOSFET element, and the output end thereof is simultaneously coupled to the third common point;

a first BJT element, an emitter end of which is coupled to the negative input end of the operational amplifier, and a collector end and a base end of which are both coupled to the ground end;

at least one second BJT element, wherein an emitter of each second BJT element is coupled to the drain end of the sixth P-type MOSFET element through a second resistor, and a collector end and a base end thereof are both coupled Connect to the ground terminal.

In one embodiment, the ring oscillator unit further includes:

a first buffer, one input end of which is coupled to the source end of the first N-type MOSFET element to receive the first operating voltage, and an output end thereof to output a first buffered operating voltage;

a second buffer, one input end of which is coupled to the source end of the second N-type MOSFET element to receive the second operating voltage, and an output end thereof to transmit a second buffered operating voltage;

a first active load, a first terminal of which is coupled to the output terminal of the first buffer;

A first active element having a first end, a second end and a third end, wherein the first end is coupled to the gate end of the sixth N-type MOSFET element and the seventh N-type MOSFET element a fourth common point between the gate terminals, the second terminal is coupled to a second terminal of the active load, and the third terminal is coupled to the ground terminal;

a second active load, a first end of which is coupled to the output end of the second buffer;

A second active element has a first end, a second end and a third end, wherein the first end is coupled to the third common point, and the second end is coupled to a first end of the second active load two terminals, and the third terminal is coupled to the power supply voltage;

N first bias voltage transmission elements, wherein each of the first bias voltage transmission elements has a first end, a second end and a third end, and the first end is coupled to the first active element. the second terminal, the second terminal is coupled to the first bias terminal of the inverter, and the third terminal is coupled to the output terminal of the first buffer;

N second bias voltage transmission elements, wherein each of the second bias voltage transmission elements has a first end, a second end and a third end, and the first end is coupled to the second active element. the second terminal, the second terminal is coupled to the second bias terminal of the inverter, and the third terminal is coupled to the output terminal of the second buffer; and

A third buffer, one input end of which is coupled to the output end of the Nth inverter, and one output end of which outputs a clock signal.

In one embodiment, the first active load is a diode-connected P-type MOSFET device, and the second active load is a diode-connected N-type MOSFET device.

In one embodiment, both the first active element and the second bias voltage transmission element are N-type MOSFET elements, and the second active element and the first bias voltage transmission element are P-type MOSFETs element.

The present invention also provides an information processing device, which has at least one electronic chip, and the electronic chip includes the ring oscillator circuit of the present invention as mentioned above.

In one embodiment, the information processing device is selected from smart TVs, smart phones, smart watches, smart bracelets, tablet computers, desktop computers, industrial computers, notebook computers, all-in-one computers, An electronic device in the group consisting of access control devices, fingerprint punching devices, and electronic door locks.

In order to enable your examiners to further understand the structure, features, purpose, and advantages of the present invention, drawings and detailed descriptions of preferred specific embodiments are hereby attached.

FIG. 2 shows a block diagram of a ring oscillator circuit of the present invention. After comparing Fig. 2 with Fig. 1, it can be seen that, in addition to a ring oscillator unit 13 comprising N cascaded inverters 131, the ring oscillator circuit 1 of the present invention further includes: a startup unit 10, a first A bias unit 11 and a second bias unit 12 . The ring oscillator circuit 1 of the present invention is applied to an electronic chip, and the first bias unit 11 is used to generate a first bias voltage Vbp and a second bias voltage Vbn according to the power supply voltage VDD of the electronic chip. , and use the second bias unit 12 to generate a first operating voltage VH and a second operating voltage VL according to the power supply voltage VDD and the first bias voltage Vbp, so as to supply power with the first operating voltage VH to a first bias terminal (that is, a high voltage bias terminal) of each of the inverters 131 of the ring oscillator unit 13, and to supply power to the ring oscillator unit 13 with the second operating voltage VL A second bias terminal (ie, a low voltage bias terminal) of each of the inverters 131 . Such design makes each of the inverters 131 not biased by the power supply voltage VDD of the electronic chip, so the frequency of the clock signal CLK output by the Nth inverter 131 is not affected by the power supply voltage VDD and temperature , so as to keep the frequency of the clock signal stable.

FIG. 3 shows the first circuit topology of the ring oscillator circuit of the present invention. As shown in FIG. 2 and FIG. 3, the startup unit 10 is coupled to the power supply voltage V _DD and the ground terminal GND, and includes a third P-type MOSFET element Mp3, a third N-type MOSFET element Mn3, a fourth P-type MOSFET element N-type MOSFET element Mp4, a fourth N-type MOSFET element Mn4, and a fifth N-type MOSFET element Mn5. It is worth noting that the so-called "first", "second",. ． ． , "Seventh" is only used to distinguish different N-type MOSFET components and/or P-type MOSFET components, and is not used to indicate the sequence relationship of components. According to the design of the present invention, the source terminal of the third P-type MOSFET element Mp3 is coupled to the power supply voltage VDD, and the gate terminal thereof is coupled to the ground terminal GND through a first resistor R1. On the other hand, the drain terminal of the third N-type MOSFET element Mn3 is coupled to the drain terminal of the third P-type MOSFET element Mp3 , and the source terminal thereof is coupled to the ground terminal GND.

According to the above description, the source terminal of the fourth P-type MOSFET element Mp4 is coupled to the power supply voltage VDD. On the other hand, the drain terminal of the fourth N-type MOSFET element Mn4 is coupled to a drain terminal of the fourth P-type MOSFET element Mp4, its source terminal is coupled to the ground terminal GND, and its gate terminal is coupled to the third N-type MOSFET element Mp4. A gate terminal of the type MOSFET element Mn3. Moreover, the drain terminal of the fourth N-type MOSFET element Mn4 is also coupled to the gate terminal thereof. As shown in FIG. 3 , the drain terminal of the fifth N-type MOSFET element Mn5 is coupled to the gate terminal of the fourth P-type MOSFET element Mp4 , and the source terminal thereof is coupled to the ground terminal GND. Moreover, the gate terminal of the fifth N-type MOSFET element Mn5 is also coupled to a first common node N1 between the drain terminal of the third P-type MOSFET element Mp3 and the drain terminal of the third N-type MOSFET element Mn3 .

As shown in FIG. 2 and FIG. 3 , the first bias unit 11 is coupled to the power supply voltage VDD and the ground terminal GND for generating a first bias voltage Vbp and a second bias voltage Vbn, and includes: a first bias voltage Five P-type MOSFET elements Mp5, a sixth P-type MOSFET element Mp6, an operational amplifier 111, a first BJT element Q1, and at least one second BJT element Q2. Wherein, the source terminal of the fifth P-type MOSFET element Mp5 is coupled to the power supply voltage VDD. On the other hand, the source terminal of the sixth P-type MOSFET element Mp6 is coupled to the power supply voltage VDD, and the gate terminal thereof is coupled to the gate terminal of the fifth P-type MOSFET element Mp5. Moreover, a second common contact N2 between the drain terminal of the fifth N-type MOSFET element Mn5 and the gate terminal of the fourth P-type MOSFET element Mp4 is coupled to the gate terminal of the sixth P-type MOSFET element Mp6 and a third common contact N3 between the gate terminal of the fifth P-type MOSFET element Mp5. In more detail, the operational amplifier 111 has a positive input terminal, a negative input terminal and an output terminal, and its positive input terminal is coupled to the drain terminal of the sixth P-type MOSFET element Mp6, and its negative input terminal is coupled to connected to the drain end of the fifth P-type MOSFET element Mp5, and simultaneously coupled to the third common node N3 with its output end. As shown in FIG. 3 , the emitter terminal of the first BJT element Q1 is coupled to the negative input terminal of the operational amplifier 121 , and both its collector terminal and base terminal are coupled to the ground terminal GND. According to the design of the present invention, there is an element quantity ratio between the first BJT element Q1 and the at least one second BJT element Q2, and the element quantity ratio is 1:m. Wherein, the emitter terminal of each second BJT element Q2 is coupled to the drain terminal of the sixth P-type MOSFET element Mp6 through a second resistor R2, and its collector terminal and base terminal are both coupled to the ground terminal GND.

As shown in FIG. 2 and FIG. 3, the second bias unit 12 is coupled to the first bias voltage Vbp transmitted from the first bias unit 11, the power supply voltage VDD and the ground terminal GND for generating a The first working voltage VH and a second working voltage VL, and include: a first P-type MOSFET element Mp1, a first N-type MOSFET element Mn1, a second P-type MOSFET element Mp2, and a second N-type MOSFET Element Mn2. Wherein, the source terminal of the first P-type MOSFET element Mp1 is coupled to the power supply voltage VDD, and the gate terminal thereof is coupled to the third common node N3 to receive the first bias voltage Vbp. On the other hand, the drain terminal of the first N-type MOSFET element Mn1 is coupled to the drain terminal of the first P-type MOSFET element Mp1 , and the source terminal thereof is coupled to the ground terminal GND. Moreover, the drain terminal of the first N-type MOSFET element Mn1 is also coupled to the gate terminal thereof. As shown in FIG. 3 , the source terminal of the second P-type MOSFET Mp2 is coupled to the power supply voltage VDD, and the gate terminal thereof is coupled to the third common node N3 to receive the first bias voltage Vbp. On the other hand, the drain terminal of the second N-type MOSFET element Mn2 is coupled to the drain terminal of the second P-type MOSFET element Mp2 , and the source terminal thereof is coupled to the ground terminal GND. Moreover, the drain terminal of the second N-type MOSFET element Mn2 is also coupled to its gate terminal.

As shown in FIG. 2 and FIG. 3 , the ring oscillator unit 13 is coupled to the second bias voltage Vbn transmitted from the first bias unit 11 and the first operating voltage transmitted from the second bias unit 12. VH, the second working voltage VL, the power supply voltage V _DD , and the ground terminal GND. In addition to N cascaded inverters 131, the ring oscillator unit 13 also includes: a first buffer 13H, a second buffer 13L, a first active load Mp8, a first active element Mn8, a The second active load Mn9, a second active element Mp9, N first bias voltage transmission elements (Mp10, Mp11, Mp12), N second bias voltage transmission elements (Mn10, Mn11, Mn12), and a first bias voltage transmission element Three buffers 133 . Wherein, the first bias voltage transmission element is a P-type MOSFET element, and the second bias voltage transmission element is an N-type MOSFET element.

As can be seen from FIG. 3 , N is an odd number greater than or equal to 3, and the first inverter 131 and the Nth inverter 111 are cascaded end to end. According to the design of the present invention, the input end of the first buffer 13H is coupled to the source end of the first N-type MOSFET element Mn1 to receive the first operating voltage VH, and the output end outputs a first buffer operation Voltage VH_buf. On the other hand, the input terminal of the second buffer 13L is coupled to the source terminal of the second N-type MOSFET element Mn2 to receive the second operating voltage VL, and transmits a second buffering operating voltage VL_buf through its output terminal. . In more detail, the first end of the first active load Mp8 is coupled to the output end of the first buffer 13H. Moreover, the first active element Mn8 has a first end, a second end and a third end, wherein the first end is coupled to the gate end of the sixth N-type MOSFET element Mn6 and the seventh N-type MOSFET element Mn6. A fourth common point N4 between the gate terminals of the MOSFET element Mn7 , the second terminal is coupled to a second terminal of the active load Mp8 , and the third terminal is coupled to the ground terminal GND. On the other hand, the first end of the second active load Mn9 is coupled to the output end of the second buffer 13L. Similarly, the second active element Mp9 has a first end, a second end and a third end, wherein the first end is coupled to the third common node N3, and the second end is coupled to the second active element. The second end of the load Mn9 is coupled to the power supply voltage VDD.

According to the above description, N is an odd number greater than or equal to 3. Moreover, each of the first bias voltage transmission elements has a first end, a second end and a third end, the first end is coupled to the second end of the first active element Mn8, and the second end is coupled to connected to the first bias terminal (ie, high voltage bias terminal) of the inverter 131, and the third terminal is coupled to the output terminal of the first buffer 13H. Similarly, each of the second bias voltage transmission elements has a first end, a second end and a third end, the first end is coupled to the second end of the second active element Mp9, and the second end The second bias terminal (ie, low voltage bias terminal) of the inverter 131 is coupled, and the third terminal is coupled to the output terminal of the second buffer 13L. Moreover, the input end of the third buffer 133 is coupled to the output end of the Nth inverter 111 , and outputs a clock signal CLK through an output end thereof. It is supplemented that, as shown in FIG. 3, the first active load Mp8 is a P-type MOSFET element of a diode-connected form, and the second active load Mn9 is also a diode-connected form N-type MOSFET components. On the other hand, the first active device Mn8 is an N-type MOSFET device, and the second active device Mp9 is also a P-type MOSFET device.

As shown in FIG. 3 , the working principle of the ring oscillator circuit 1 of the present invention is as follows: after the power supply voltage VDD is powered on, the third P-type MOSFET element Mp3 is turned on so as to turn on the fifth N-type MOSFET element Mn5 . After being turned on, the potential of the drain terminal of the fifth N-type MOSFET element Mn5 is pulled down, so that the fifth P-type MOSFET element Mp5 and the sixth P-type MOSFET element Mp6 are turned on, thereby completely starting the entire first bias unit 11. Then, the fourth P-type MOSFET element Mp4 transmits a bias current to the fourth N-type MOSFET element Mn4. Since the fourth N-type MOSFET element Mn4 and the third N-type MOSFET element Mn3 form a current mirror, the third N-type MOSFET element Mn3 generates a drain current according to the bias current, and the drain current is related to the bias current. The current value of the bias current is the same. Afterwards, since the potential of the gate terminal of the fifth N-type MOSFET element Mn5 is pulled down by the turned-on third N-type MOSFET element Mn3, the fifth N-type MOSFET element Mn5 is turned off. In this case, the electrical connection between the starting unit 10 and the first bias unit 11 is cut off.

Subsequently, the seventh P-type MOSFET element Mp7 mirrors the element currents of the fifth P-type MOSFET element Mp5 and the sixth P-type MOSFET element Mp6 and transfers to the sixth N-type MOSFET element Mn6. At the same time, the first P-type MOSFET element Mp1/second P-type MOSFET element Mp2 mirrors the element current of the fifth P-type MOSFET element Mp5/sixth P-type MOSFET element Mp6 and transmits it to the first N-type MOSFET element Mn1/second N N-type MOSFET element Mn2, so that the first N-type MOSFET element Mn1/second N-type MOSFET element Mn2 generates the first working voltage VH/the second working voltage VL.

······················ (1) Then, the first buffer 13H/the second buffer 13L output the first working voltage VH/the second working voltage VL as the first buffering working voltage VH_buf/the second buffering working voltage VL_buf. And, the first active element Mn8 mirrors the element current of the sixth N-type MOSFET element Mn6 to the first active load Mp8, and then the first active load Mp8 mirrors the current to N first bias voltage transmission elements ( Mp10, Mp11, Mp12) and as a "pull-up" current for the ring oscillator circuit. At the same time, the second active element Mp9 mirrors the bias current of the first bias unit 11 and transmits it to the second active load Mn9, and then N second bias voltage transmission elements (Mn10, Mn11, Mn12) mirror the second active load The load Mn9 current acts as a "pull-down" current for the ring oscillator (ie, N cascaded inverters 131). Finally, the ring oscillator performs stable periodic oscillation after the pull-up current and the pull-down current are stable, so as to output a clock signal CLK. And, the frequency of the clock signal CLK can be represented by the following equation (1):

······················ (1)

······································ (2) And, the bias current of the first bias unit 11 can be represented by the following formula (2):

······································ (2)

為第一BJT元件Q1/第二BJT元件Q2的基極端與射極端的電壓差，VT為熱電壓，m前述之元件數量比。並且，在該第一BJT元件Q1與該第二BJT元件Q2的數量皆為1的情況下，該第一BJT元件Q1和該第二BJT元件Q2之間具有一面積比，且該面積比亦為1:m。忽略第二電阻R2的溫度係數，偏置電流I為正溫度係數電流。換句話說，該時鐘信號CLK的頻率不受溫度係數漂移之影響。 In the above formula (2),

is the voltage difference between the base terminal and the emitter terminal of the first BJT element Q1/the second BJT element Q2, VT is the thermal voltage, and m is the aforementioned element quantity ratio. Moreover, in the case where the numbers of the first BJT element Q1 and the second BJT element Q2 are both 1, there is an area ratio between the first BJT element Q1 and the second BJT element Q2, and the area ratio is also is 1:m. Neglecting the temperature coefficient of the second resistor R2, the bias current I is a positive temperature coefficient current. In other words, the frequency of the clock signal CLK is not affected by temperature coefficient drift.

······························ (3) On the other hand, when working in the subthreshold state, the Vgs of the MOSFET element can be expressed by the following formula (3):

····························(3)

················ (4) In the above formula (3), W and L are the element width and length of the MOSFET element respectively, Vth is the critical voltage, n is the process parameter, and I ₀ is the diffusion current per unit area. Make the first P-type MOSFET element Mp1 and the second P-type MOSFET element Mp2 have the same aspect ratio, and make an element number between the first P-type MOSFET element Mp1 and the second P-type MOSFET element Mp2 The ratio is α/1. In this way, VH_buf-VL_buf in the above formula (1) can be expressed by the following formula (4):

················(4)

··································· (1.1) Therefore, the above formula (1) can be rewritten as the following formula (1.1):

・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・ (1.1)

It can be known from the above formula (1.1) that the frequency of the clock signal CLK is not affected by temperature drift and power voltage VDD drift.

FIG. 4 shows a second circuit topology of the ring oscillator circuit of the present invention. 4 and FIG. 3, in the second circuit topology, the first bias unit 11 for generating a first bias voltage Vbp and a second bias voltage Vbn includes: a fifth The P-type MOSFET element Mp5, a sixth N-type MOSFET element Mn6, a sixth P-type MOSFET element Mp6, and at least one seventh N-type MOSFET element Mn7. Wherein, the drain terminal of the sixth N-type MOSFET element Mn6 is coupled to the drain terminal of the fifth P-type MOSFET element Mp5 , the source terminal thereof is coupled to the ground terminal GND, and the gate terminal thereof is coupled to the drain terminal thereof. On the other hand, the source terminal of the sixth P-type MOSFET element Mp6 is coupled to the power supply voltage VDD, and the gate terminal thereof is coupled to the gate terminal of the fifth P-type MOSFET element Mp5. Moreover, a second common contact N2 between the drain terminal of the fifth N-type MOSFET element Mn5 and the gate terminal of the fourth P-type MOSFET element Mp4 is coupled to the gate terminal of the sixth P-type MOSFET element Mp6 A third common point N3 between the gate terminal of the fifth P-type MOSFET element Mp5, and the drain end of the sixth P-type MOSFET element Mp6 is coupled to the third common point N3. As shown in FIG. 4 , according to the design of the present invention, there is an element number ratio between the sixth N-type MOSFET element Mn6 and the at least one seventh N-type MOSFET element Mn7 , and the element number ratio is 1:m. Wherein, the drain terminal of each seventh N-type MOSFET element Mn7 is coupled to the drain terminal of the sixth P-type MOSFET element Mp6 , and the source terminal thereof is coupled to the ground terminal GND through a second resistor R2 . Moreover, the gate terminal of each seventh N-type MOSFET element Mn7 is coupled to the gate terminal of the sixth N-type MOSFET element Mn6.

·································· (2.a) According to the circuit design of FIG. 4, the bias current of the first bias unit 11 can be represented by the following formula (2.1):

·····························(2.a)

…………………(2.b) In the above formula (2.1), k=μCox is a process transconductance parameter (process transconductance parameter) of the MOSFET element, and m is a sixth N-type MOSFET element Mn6 and the at least one seventh N-type MOSFET element Mn7. quantity ratio. Moreover, when the number of the sixth N-type MOSFET element Mn6 and the number of the seventh N-type MOSFET element Mn7 are both 1, there is a gap between the sixth N-type MOSFET element Mn6 and the seventh N-type MOSFET element Mn7. area ratio, and the area ratio is also 1:m. Neglecting the temperature coefficient of the second resistor R2, the above formula (2.1) can be rewritten as the following formula (2.b).

………………(2.b)

······································· (3.a) In the above formula (2.2), I ₀ is a constant that has nothing to do with temperature, so the magnitude of the bias current I is only related to the process transconductance parameters of MOSFET components. When working in the subthreshold state, the Vgs of the MOSFET element can be expressed by the following formula (3.a):

・・・・・・・・・・・・・・・・・・・・・・・・・・・・ (3.a)

···································· (5) In this way, VH_buf-VL_buf in the above formula (1) can be expressed by the following formula (5):

·································(5)

··································· (1.a) Therefore, the above formula (1) can be rewritten as the following formula (1.a):

·······························(1.a)

································· (5.a) Make the first P-type MOSFET element Mp1 and the second P-type MOSFET element Mp2 have the same aspect ratio, and make an element number between the first P-type MOSFET element Mp1 and the second P-type MOSFET element Mp2 The ratio is λ/1. In this way, VH_buf-VL_buf in the above formula (5) can be expressed by the following formula (5.a):

·····························(5.a)

·································· (1.b) Finally, the above formula (1.a) can be rewritten as the following formula (1.b):

······························(1.b)

It can be known from the above formula (1.b) that the frequency of the clock signal CLK is not affected by temperature drift and power supply voltage VDD drift.

Experimental example

In the experimental example, the power supply voltage VDD is 3.3V. Moreover, the basic parameters of MOSFET elements are: W _Mp3 /L _Mp3 = 1/20μm, W _Mn5 /L _Mn5 = 0.4/20μm, W _Mp1 /L _Mp1 = 8/3μm, W _Mp2 /L _Mp2 = 8/3μm, W _Mp4 /L _Mp4 = 8/3 μm, W _Mp5 /L _Mp5 = 8/3 μm, W _Mp6 /L _Mp6 = 8/3 μm, W _Mp7 /L _Mp7 = 8/3 μm, W _Mp8 /L _Mp8 = 8/3 μm, W _Mp9 /L _Mp9 = 8/3 μm, W _Mp10 /L _Mp10 = 8/3 μm, W _Mp11 /L _Mp11 = 8/3 μm, W _Mp12 /L _Mp12 = 8/3 μm, W _Mn1 /L _Mn1 = 2/3 μm, W _Mn2 /L _Mn2 = 2/3 μm, W _Mn3 /L _Mn3 = 4/2 μm, W _Mn4 /L _Mn4 = 4/2 μm, W _Mn6 /L _Mn6 = 4/2 μm, W _Mn8 /L _Mn8 = 4/2 μm, W _Mn9 /L _Mn9 =4/2 μm, W _Mn10 /L _Mn10 =4/2 μm, W _Mn11 /L _Mn11 =4/2 μm, W _Mn12 /L _Mn12 =4/2 μm. In addition, R1=1kΩ, R2=30kΩ, the ratio of the number of elements between the first P-type MOSFET element Mp1 and the second P-type MOSFET element Mp2 is 20/6, and the first BJT element Q1 and the second BJT The element number ratio among the elements Q2 is 1/8.

The operating frequency f _CLK of the clock signal CLK output by the experimental example of the ring oscillator circuit 1 of the present invention can be calculated using the above formula (1.1). The output frequency f obtained by circuit simulation is about 80MHz (the output frequency is close to 80Mhz by adjusting the resistance value of different process angles), and Fig. 5 is the temperature drift curve of the ring oscillator circuit of the present invention under different process angle conditions, and Fig. 6 is Power supply drift curves of the ring oscillator circuit of the present invention under different process angle conditions. Moreover, the following table (1) sorts out the frequencies of different process corners and different temperature conditions, and table (2) sorts out the frequencies of different process corners and different power supply voltages. It can be seen from the results that the ring oscillator circuit of the present invention has a temperature drift coefficient <±1.99% caused by a temperature change from -40°C to 120°C under different process angles, and <±1.02% at the TT process angle %. On the other hand, the frequency drift coefficient caused by the power supply variation of ±10% is less than ±0.07% at each process angle.

Table 1) temperature(℃) TT FF SS FS SF -40 78.44 80.65 79.2 81.62 78.53 40 79 80.96 80.15 80.59 80.1 120 78.2 79.38 79.85 79.02 81.12 Frequency drift (%) -0.72 -0.39 -1.19 1.30 -1.94 -1.02 -1.99 -0.38 -1.99 -1.26

Table 2) Power supply voltage (V) TT FF SS FS SF 2.97 78.87 80.77 80.07 80.17 80.15 3.3 78.86 80.78 80.02 80.13 80.1 3.63 78.85 80.79 80 80.11 80.16 Frequency drift (%) 0.01 -0.01 0.06 0.05 0.06 0.01 0.01 0.02 0.02 -0.07

Thus, the above-mentioned complete and clearly illustrates a ring oscillator circuit of the present invention; and, through the above, it can be known that the present invention has the following advantages:

(1) The present invention discloses a ring oscillator circuit, which basically includes a first bias unit, a second bias unit and a ring oscillator unit, wherein the first bias unit generates a first bias unit according to a power supply voltage A bias voltage and a second bias voltage, and the second bias unit generates a first operating voltage and a second operating voltage according to the power supply voltage and the first bias voltage. In addition, the ring oscillator unit is coupled to the power supply voltage and the ground terminal, and is simultaneously coupled to the second bias voltage transmitted from the first bias unit and the first working voltage transmitted from the second bias unit. voltage and the second operating voltage. According to the design of the present invention, the ring oscillator unit includes N cascaded inverters, and the first operating voltage supplies power to a first bias terminal of each of the inverters, and the second operating voltage The voltage is then supplied to a second bias terminal of each of the inverters. Designed in this way, each of the inverters is not biased by the power supply voltage of the electronic chip, so the frequency of the clock signal output by the Nth inverter is not affected by the power supply voltage and temperature, thereby maintaining the frequency of the clock signal. Stablize.

(2) The present invention also provides an information processing device, which has at least one electronic chip, and the electronic chip includes the ring oscillator circuit of the present invention as described above. Moreover, the information processing device is selected from smart TVs, smart phones, smart watches, smart bracelets, tablet computers, desktop computers, industrial computers, notebook computers, all-in-one computers, access control devices, fingerprint A type of electronic device in the group consisting of a card punching device and an electronic door lock.

It must be emphasized that what is disclosed in the above-mentioned case is a preferred embodiment, and all partial changes or modifications derived from the technical ideas of this case and easily deduced by those familiar with the technology are all inseparable from the patent of this case. category of rights.

To sum up, the purpose, means and efficacy of this case all show that it is very different from the conventional technology, and its first invention is practical, and indeed meets the patent requirements of the invention. I implore your review committee to be aware and grant a patent as soon as possible to benefit you. Society is for the Most Prayer.

1a: Ring Oscillator Circuit 11a: Inverter 111a: P-type MOSFET element 112a: N-type MOSFET element 1: Ring Oscillator Circuit 10:Start the unit 11: The first bias unit 111: Operational amplifier 12: Second bias unit 13: Ring oscillator unit 131: Inverter 13H: the first buffer 13L: Second buffer 133: The third buffer Mp1: the first P-type MOSFET element Mn1: the first N-type MOSFET element Mp2: The second P-type MOSFET element Mn2: The second N-type MOSFET element Mp3: The third P-type MOSFET element Mn3: The third N-type MOSFET element Mp4: The fourth P-type MOSFET element Mn4: The fourth N-type MOSFET element Mp5: Fifth P-type MOSFET element Mn5: Fifth N-type MOSFET element Mp6: The sixth P-type MOSFET element Mn6: the sixth N-type MOSFET element Mp7: The seventh P-type MOSFET element Mn7: The seventh N-type MOSFET element Mp8: The first active load Mn8: the first active component Mp9: Second Active Component Mn9: second active load Mp10, Mp11, Mp12: first bias voltage transfer elements Mn10, Mn11, Mn12: second bias voltage transmission elements Q1: First BJT component Q2: Second BJT component

Fig. 1 is the circuit topology diagram of a known ring oscillator circuit; Fig. 2 is the block diagram of a kind of ring oscillator circuit of the present invention; Fig. 3 is the first circuit topology diagram of the ring oscillator circuit of the present invention; Fig. 4 is the second circuit topology diagram of the ring oscillator circuit of the present invention; Fig. 5 is the temperature drift curve of the ring oscillator circuit of the present invention under different process angle conditions; and FIG. 6 is a power supply drift curve of the ring oscillator circuit of the present invention under different process corner conditions.

1: Ring Oscillator Circuit

10:Start the unit

11: The first bias unit

12: Second bias unit

13: Ring oscillator unit

131: Inverter

Claims (7)

A ring oscillator circuit, comprising: a first bias unit, coupled between a power supply voltage and a ground terminal, for generating a first bias voltage and a second bias voltage; a second bias A unit, coupled between the power supply voltage and the ground terminal, for generating a first operating voltage and a second operating voltage according to the first bias voltage; a start unit, coupled between the power supply voltage and the ground terminal, used to start the first bias unit; and a ring oscillator unit, coupled between the power supply voltage and the ground terminal, used for The first bias voltage and the second bias voltage generate a clock signal, and it includes N cascaded inverters, where N is an odd number greater than or equal to 3, and the first inverter and the first inverter N said inverters are cascaded end to end; wherein, said first operating voltage is supplied to a first bias terminal of each said inverter, and said second operating voltage is supplied to each said inverter A second bias terminal; the second bias unit includes: a first P-type MOSFET element, one source terminal of which is coupled to the power supply voltage, and one gate terminal of which is coupled to the first bias voltage; a first An N-type MOSFET element, a drain end of which is coupled to a gate end and a drain end of the first P-type MOSFET element, and a source end of which is coupled to the ground end; a second P-type MOSFET element, one of which A source terminal is coupled to the power supply voltage, and a gate terminal thereof is coupled to the first bias voltage; and a second N-type MOSFET element, a drain terminal thereof is coupled to a gate terminal thereof and the second P-type MOSFET element A drain terminal, and a source terminal of which is coupled to the ground terminal; and the startup unit includes: a third P-type MOSFET element, a source terminal of which is coupled to the power supply voltage, and a gate terminal of which is coupled to the ground terminal through a first resistor connected to the ground terminal; a third N-type MOSFET element, a drain end coupled to a drain end of the third P-type MOSFET element, and a source end coupled to the ground end; a fourth P-type MOSFET element, One source end is coupled to the power supply voltage; a fourth N-type MOSFET element, one drain end is coupled to a drain end of the fourth P-type MOSFET element, one source end is coupled to the ground end, and one gate a terminal coupled to the drain terminal thereof and a gate terminal of the third N-type MOSFET element; and a fifth N-type MOSFET element, a drain terminal of which is coupled to the fourth P-type MOSFET element A gate end of the MOSFET element, a source end of which is coupled to the ground end, and a gate end of which is coupled to the drain end of the third P-type MOSFET element and the drain end of the third N-type MOSFET element. - the first common contact. The ring oscillator circuit as described in Claim 1, wherein the first bias unit includes: a fifth P-type MOSFET element, one source terminal of which is coupled to the power supply voltage; a sixth N-type MOSFET element, one of which A drain end is coupled to a drain end of the fifth P-type MOSFET element, a source end thereof is coupled to the ground end, and a gate end thereof is coupled to the drain end; a sixth P-type MOSFET element, a source of which terminal is coupled to the power supply voltage, and a gate terminal thereof is coupled to a gate terminal of the fifth P-type MOSFET element; wherein, the drain terminal of the fifth N-type MOSFET element is connected to the gate terminal of the fourth P-type MOSFET element A second common point between them is coupled to a third common point between the gate terminal of the sixth P-type MOSFET element and the gate terminal of the fifth P-type MOSFET element, and the sixth A drain end of a P-type MOSFET element is coupled to the third common point; and at least one seventh N-type MOSFET element, wherein a drain end of each of the seventh N-type MOSFET elements is coupled to the sixth P-type MOSFET The drain end of the element, and one source end thereof is coupled to the ground end through a second resistor; wherein, a gate end of each of the seventh N-type MOSFET elements is coupled to the gate of the sixth N-type MOSFET element extreme. The ring oscillator circuit as described in Claim 1, wherein the first bias unit includes: a fifth P-type MOSFET element, one source terminal of which is coupled to the power supply voltage; a sixth P-type MOSFET element, one of which The source end is coupled to the power supply voltage, and a gate end thereof is coupled to a gate end of the fifth P-type MOSFET element; wherein, the drain end of the fifth N-type MOSFET element is connected to the gate end of the fourth P-type MOSFET element A second common point between the terminals is coupled to a third common point between the gate terminal of the sixth P-type MOSFET element and the gate end of the fifth P-type MOSFET element; An operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and is coupled to a drain terminal of the sixth P-type MOSFET element with its positive input terminal, and coupled to the sixth P-type MOSFET element with its negative input terminal. A drain end of the fifth P-type MOSFET element, and the output end thereof is coupled to the third common point at the same time; a first BJT element, an emitter end thereof is coupled to the negative input end of the operational amplifier, and a collector terminal and a base terminal thereof are coupled to the ground terminal; and at least one second BJT element, wherein an emitter terminal of each of the second BJT elements is coupled to the sixth P-type MOSFET through a second resistor The drain terminal of the element, and a collector terminal and a base terminal thereof are coupled to the ground terminal. The ring oscillator circuit as described in claim 2 or claim 3, wherein the ring oscillator unit further includes: a first buffer, an input end of which is coupled to the source end of the first N-type MOSFET element for receiving the first operating voltage, and outputting a first buffering operating voltage through an output end thereof; a second buffer, an input end of which is coupled to the source end of the second N-type MOSFET element to receive the first buffering operating voltage Two operating voltages, and a second buffering operating voltage is transmitted through an output end; a first active load, a first end of which is coupled to the output end of the first buffer; a first active element, having a first active load One terminal, a second terminal and a third terminal, wherein the first terminal is coupled to a fourth terminal between the gate terminal of the sixth N-type MOSFET element and the gate terminal of the seventh N-type MOSFET element. A common point, the second terminal is coupled to a second terminal of the active load, and the third terminal is coupled to the ground terminal; a second active load, a first terminal of which is coupled to the second buffer Output terminal; a second active element, having a first terminal, a second terminal and a third terminal, wherein the first terminal is coupled to the third common point, and the second terminal is coupled to the second active load a second terminal of the power supply voltage, and the third terminal is coupled to the power supply voltage; N first bias voltage transmission elements, wherein each of the first bias voltage transmission elements has a first terminal, a second terminal and a third end, the first end is coupled to the second end of the first active element, the second end is coupled to the first bias end of the inverter, and the third end is coupled to the first end the output terminal of a buffer; N second bias voltage transmission elements, wherein each of the second bias voltage transmission elements has a first end, a second end and a third end, and the first end is coupled to the second active element. the second terminal, the second terminal is coupled to the second bias terminal of the inverter, and the third terminal is coupled to the output terminal of the second buffer; and a third buffer, one of which The input end is coupled to the output end of the Nth inverter, and a clock signal is output from one output end thereof. The ring oscillator circuit as claimed in claim 4, wherein the first active load is a P-type MOSFET element connected with a diode, and the second active load is an N-type MOSFET element connected with a diode . The ring oscillator circuit according to claim 4, wherein both the first active element and the second bias voltage transfer element are N-type MOSFET elements, and the second active element and the first bias voltage The voltage transmitting element is a P-type MOSFET element. An information processing device has at least one electronic chip, and the electronic chip includes the ring oscillator circuit according to any one of claim 1 to claim 6.

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