TWI780566B - Semiconductor strcuture - Google Patents
Semiconductor strcuture Download PDFInfo
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- TWI780566B TWI780566B TW110100849A TW110100849A TWI780566B TW I780566 B TWI780566 B TW I780566B TW 110100849 A TW110100849 A TW 110100849A TW 110100849 A TW110100849 A TW 110100849A TW I780566 B TWI780566 B TW I780566B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 162
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000004020 conductor Substances 0.000 claims description 40
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 229910021332 silicide Inorganic materials 0.000 claims description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 description 15
- 230000005684 electric field Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910021334 nickel silicide Inorganic materials 0.000 description 3
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Abstract
Description
本發明是有關於一種半導體結構,且特別是有關於一種具有浮體場環(floating field ring,FFR)的半導體結構。The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure having a floating field ring (FFR).
一些半導體元件(如,功率元件)在主接面(main junction)的最邊緣處容易產生崩潰(breakdown)現象。目前的解決方式是藉由環繞半導體元件區的浮體場環來提升半導體元件的崩潰電壓,以防止崩潰現象產生。然而,如何更進一步提升半導體元件的崩潰電壓為目前持續努力的目標。Some semiconductor devices (eg, power devices) are prone to breakdown at the edge of the main junction. The current solution is to increase the breakdown voltage of the semiconductor element by means of a floating field ring surrounding the semiconductor element region, so as to prevent the breakdown phenomenon. However, how to further increase the breakdown voltage of semiconductor devices is the goal of ongoing efforts.
本發明提供一種半導體結構,其可提升半導體元件的崩潰電壓。The invention provides a semiconductor structure, which can increase the breakdown voltage of semiconductor elements.
本發明提出一種半導體結構,包括基底、半導體層、浮體場環結構與導體層。半導體層設置在基底上。半導體層具有第一導電型。浮體場環結構位在半導體層中。浮體場環結構包括多個浮體場環。浮體場環具有第二導電型。導體層位在浮體場環的一側。以兩個相鄰的浮體場環為一組,在至少一組浮體場環之間不設有導體層。The invention proposes a semiconductor structure, including a base, a semiconductor layer, a floating field ring structure and a conductor layer. The semiconductor layer is disposed on the substrate. The semiconductor layer has a first conductivity type. The floating body field ring structure is located in the semiconductor layer. The floating body field ring structure includes a plurality of floating body field rings. The floating body field ring has a second conductivity type. The conductor layer is located on one side of the field ring of the floating body. Two adjacent floating body field rings are taken as a group, and no conductor layer is provided between at least one group of floating body field rings.
依照本發明的一實施例所述,在上述半導體結構中,相鄰的兩組浮體場環可共用一個浮體場環。According to an embodiment of the present invention, in the above semiconductor structure, two adjacent groups of floating body field rings may share one floating body field ring.
依照本發明的一實施例所述,在上述半導體結構中,導體層可位在兩個相鄰的浮體場環之間。According to an embodiment of the present invention, in the above semiconductor structure, the conductor layer may be located between two adjacent floating body field rings.
依照本發明的一實施例所述,在上述半導體結構中,導體層可為摻雜區、金屬、摻雜多晶矽、金屬矽化物或其組合。According to an embodiment of the present invention, in the above semiconductor structure, the conductive layer can be a doped region, metal, doped polysilicon, metal silicide or a combination thereof.
依照本發明的一實施例所述,在上述半導體結構中,導體層可連接於浮體場環結構。According to an embodiment of the present invention, in the above semiconductor structure, the conductor layer may be connected to the floating body field ring structure.
依照本發明的一實施例所述,在上述半導體結構中,導體層可不連接於浮體場環結構。According to an embodiment of the present invention, in the above semiconductor structure, the conductive layer may not be connected to the floating body field ring structure.
依照本發明的一實施例所述,在上述半導體結構中,導體層的底面可高於浮體場環的底面。According to an embodiment of the present invention, in the above semiconductor structure, the bottom surface of the conductive layer may be higher than the bottom surface of the floating body field ring.
依照本發明的一實施例所述,在上述半導體結構中,整個導體層可位在半導體層中。According to an embodiment of the present invention, in the above semiconductor structure, the entire conductor layer may be located in the semiconductor layer.
依照本發明的一實施例所述,在上述半導體結構中,導體層可位在半導體層的頂面上。According to an embodiment of the present invention, in the above semiconductor structure, the conductor layer may be located on the top surface of the semiconductor layer.
依照本發明的一實施例所述,在上述半導體結構中,導體層的一部分可位在半導體層中,且導體層的另一部分可突出於半導體層的頂面。According to an embodiment of the present invention, in the above semiconductor structure, a part of the conductor layer can be located in the semiconductor layer, and another part of the conductor layer can protrude from the top surface of the semiconductor layer.
依照本發明的一實施例所述,在上述半導體結構中,導體層的數量可為一個。According to an embodiment of the present invention, in the above semiconductor structure, the number of conductive layers may be one.
依照本發明的一實施例所述,在上述半導體結構中,導體層的數量可為多個。According to an embodiment of the present invention, in the above semiconductor structure, the number of conductive layers may be multiple.
依照本發明的一實施例所述,在上述半導體結構中,基底可包括半導體元件區。浮體場環結構可環繞半導體元件區。半導體結構更可包括半導體元件。半導體元件可包括第一摻雜區與第二摻雜區。第一摻雜區位在半導體元件區的半導體層中。第一摻雜區可具有第二導電型。第二摻雜區位在基底中,且鄰近於半導體層。第二摻雜區可具有第一導電型。According to an embodiment of the present invention, in the above semiconductor structure, the base may include a semiconductor element region. The floating body field ring structure can surround the semiconductor element region. The semiconductor structure may further include semiconductor elements. The semiconductor device may include a first doped region and a second doped region. The first doped region is located in the semiconductor layer of the semiconductor element region. The first doped region may have a second conductivity type. The second doped region is located in the base and adjacent to the semiconductor layer. The second doped region may have the first conductivity type.
依照本發明的一實施例所述,在上述半導體結構中,半導體元件更可包括井區。井區位在半導體元件區的半導體層中。井區可具有第二導電型。第一摻雜區位在井區中。According to an embodiment of the present invention, in the above semiconductor structure, the semiconductor device may further include a well region. The well region is located in the semiconductor layer in the semiconductor element region. The well region may have a second conductivity type. The first doped region is in the well region.
依照本發明的一實施例所述,在上述半導體結構中,半導體元件更可包括第三摻雜區。第三摻雜區位在浮體場環結構的遠離半導體元件區的一側的半導體層中。According to an embodiment of the present invention, in the above semiconductor structure, the semiconductor element may further include a third doped region. The third doping region is located in the semiconductor layer on the side of the floating body field ring structure away from the semiconductor element region.
依照本發明的一實施例所述,在上述半導體結構中,更可包括第四摻雜區。第四摻雜區位在浮體場環結構與第三摻雜區之間的半導體層中。第四摻雜區可具有第一導電型。According to an embodiment of the present invention, the above semiconductor structure may further include a fourth doped region. The fourth doping region is located in the semiconductor layer between the floating body field ring structure and the third doping region. The fourth doped region may have the first conductivity type.
基於上述,在本發明所提出的半導體結構中,導體層位在浮體場環的一側,藉此可改變浮體場環結構所產生的能帶,且對電場造成干擾。此外,在導體層處可產生電場聚集。因此,藉由導體層可達到分散電場的效果,進而提升半導體元件的崩潰電壓。另外,由於本發明所提出的半導體結構可提升半導體元件的崩潰電壓,因此即使縮小浮體場環結構的面積,也可以維持與現有技術相同的崩潰電壓,且可具有更小的元件尺寸。另一方面,本發明所提出的半導體結構的製程可輕易地與現行製程進行整合。Based on the above, in the semiconductor structure proposed by the present invention, the conductor layer is located on one side of the floating body field ring, thereby changing the energy band generated by the floating body field ring structure and causing interference to the electric field. Furthermore, an electric field concentration may be generated at the conductor layer. Therefore, the effect of dispersing the electric field can be achieved by the conductive layer, thereby increasing the breakdown voltage of the semiconductor device. In addition, since the semiconductor structure proposed by the present invention can increase the breakdown voltage of the semiconductor element, even if the area of the floating body field ring structure is reduced, the same breakdown voltage as the prior art can be maintained, and the element size can be smaller. On the other hand, the manufacturing process of the semiconductor structure proposed by the present invention can be easily integrated with the existing manufacturing process.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.
圖1為根據本發明一實施例的半導體結構的上視圖。在圖1中,省略圖2A中的部分構件,以清楚地描述圖1中的構件之間的配置關係。圖2A為沿著圖1中的I-I’剖面線的半導體結構的剖面圖。圖2B至圖2I為本發明另一些實施例的沿著圖1中的I-I’剖面線的半導體結構的剖面圖。在圖2A至圖2I中,相同或相似的構件以相同的符號表示。FIG. 1 is a top view of a semiconductor structure according to an embodiment of the present invention. In FIG. 1 , some components in FIG. 2A are omitted to clearly describe the configuration relationship among the components in FIG. 1 . 2A is a cross-sectional view of the semiconductor structure along the line I-I' in FIG. 1 . 2B to 2I are cross-sectional views of semiconductor structures along the line I-I' in FIG. 1 according to other embodiments of the present invention. In FIGS. 2A to 2I , the same or similar components are denoted by the same symbols.
請參照圖1與圖2A,半導體結構10包括基底100、半導體層102、浮體場環結構104與導體層106。基底100可為半導體基底,如矽基底。此外,基底100可包括半導體元件區R。Referring to FIG. 1 and FIG. 2A , the
半導體層102設置在基底100上。半導體層102的材料例如是磊晶矽等半導體材料。半導體層102具有第一導電型(如,N型)。此外,第一導電型與第二導電型可為不同導電型。第一導電型與第二導電型可分別為N型與P型中的一者與另一者。在本實施例中,第一導電型是以N型為例,且第二導電型是以P型為例,但本發明並不以此為限。在另一些實施例中,第一導電型可為P型,且第二導電型可為N型。The
浮體場環結構104位在半導體層102中。浮體場環結構104可環繞半導體元件區R(圖1)。浮體場環結構104包括多個浮體場環104a。以兩個相鄰的浮體場環104a為一組。在本實施例中,浮體場環結構104可包括多組浮體場環104a,但本發明並不以此為限。相鄰的兩組浮體場環104a可共用一個浮體場環104a。舉例來說,由於兩個相鄰的浮體場環104a可組成一組浮體場環104a,因此圖2A中的七個浮體場環104a可組成六組浮體場環104a,但本發明的浮體場環104a的數量與組數並不以此為限。在另一些實施例中,浮體場環結構104可僅包括一組浮體場環104a,亦即浮體場環結構104可僅包括兩個相鄰的浮體場環104a。浮體場環104a具有第二導電型(如,P型)。舉例來說,浮體場環104a可為第二導電型(如,P型)的摻雜區。另外,多個浮體場環104a的寬度W可彼此相同或不同。The floating body
導體層106位在浮體場環104a的一側,藉此可改變浮體場環結構104所產生的能帶,且對電場造成干擾。此外,在導體層106處可產生電場聚集,以達到分散電場的效果,進而提升崩潰電壓。在一些實施例中,當崩潰電壓達到最佳化時,在導體層106附近會產生另一個電流路徑,以達到分散電流的效果。The
此外,以兩個相鄰的浮體場環104a為一組,在至少一組浮體場環104a之間不設有導體層106。舉例來說,如圖2A所示,在五組浮體場環104a之間不設有導體層106,但本發明並不以此為限。只要在至少一組浮體場環104a之間不設有導體層106即屬於本發明所涵蓋的範圍。另外,導體層106的底面BS1可高於浮體場環104a的底面BS2。In addition, two adjacent floating body field rings 104a are taken as a group, and no
如圖2A所示,導體層106可位在兩個相鄰的浮體場環104a之間,但本發明並不以此為限。此外,導體層106可位在任一組浮體場環104a之間。舉例來說,導體層106可位在左側第二組浮體場環104a之間。在另一些實施例中,如圖2B所示,導體層106可不位在兩個相鄰的浮體場環104a之間,而是位在最內側(如,最靠近半導體元件區R)的浮體場環104a的靠近半導體元件區R的一側。在另一些實施例中,導體層106可位在最外側(如,最遠離半導體元件區R)的浮體場環104a的遠離半導體元件區R的一側(未示出)。此外,當導體層106的位置越靠近半導體元件區R時,提升崩潰電壓的效果越佳。As shown in FIG. 2A , the
如圖2A所示,整個導體層106可位在半導體層102中,亦即導體層106可不突出於半導體層102的頂面TS,但本發明並不此為限。導體層106可為摻雜區、金屬(如,鋁、銅、金、銀等金屬或其合金等)、摻雜多晶矽、金屬矽化物(如,矽化鈷或矽化鎳等)或其組合。此外,當導體層106為摻雜區時,摻雜區可具有第二導電型(如,P型)。在另一些實施例中,如圖2C所示,若導體層106是利用自對準金屬矽化物製程(self-aligned-silicide (salicide) process)所形成的金屬矽化物,則整個導體層106可位在半導體層102中的開口OP的表面上。As shown in FIG. 2A , the entire
在另一些實施例中,如圖2D所示,導體層106可位在半導體層102的頂面TS上。在此情況下,導體層106可為金屬(如,鋁、銅、金、銀等金屬或其合金)、摻雜多晶矽或金屬矽化物(如,矽化鈷或矽化鎳等)或其組合。In other embodiments, as shown in FIG. 2D , the
在另一些實施例中,如圖2E所示,導體層106的一部分可位在半導體層102中,且導體層106的另一部分可突出於半導體層102的頂面TS。在此情況下,導體層106可為摻雜區、金屬(如,鋁、銅、金、銀等金屬或其合金等)、摻雜多晶矽或金屬矽化物(如,矽化鈷或矽化鎳等)或其組合。在一些實施例中,位在半導體層102中的導體層106與突出於半導體層102的頂面TS的導體層106可為相同材料。在另一些實施例中,位在半導體層102中的導體層106與突出於半導體層102的頂面TS的導體層106可為不同材料。In other embodiments, as shown in FIG. 2E , a part of the
如圖2A所示,導體層106的數量可為一個,但本發明並不以此為限。在另一些實施例中,如圖2F所示,導體層106的數量可為多個,且不限於圖2F中的數量。在圖2F中,多個導體層106可採用圖2A的配置方式,亦即多個導體層106可均為整個位在半導體層102中,但本發明並不以此為限。在另一些實施例中,多個導體層106可採用圖2D的配置方式,亦即多個導體層106可均為位在半導體層102的頂面TS上(未示出)。在另一些實施例中,多個導體層106可採用圖2E的配置方式,亦即多個導體層106可均為部分位在半導體層102中且部分突出於半導體層102的頂面TS(未示出)。在另一些實施例中,多個導體層106可採用圖2A、圖2D與圖2E的配置方式的任意組合。舉例來說,至少一個導體層106可整個位在半導體層102中,至少一個導體層106可位在半導體層102的頂面TS上,且至少一個導體層106可部分位在半導體層102中且部分突出於半導體層102的頂面TS(未示出)。As shown in FIG. 2A , the number of conductor layers 106 may be one, but the invention is not limited thereto. In some other embodiments, as shown in FIG. 2F , the number of conductor layers 106 may be multiple, and is not limited to the number in FIG. 2F . In FIG. 2F , the plurality of
如圖2A至圖2F所示,導體層106可連接於浮體場環結構104。舉例來說,導體層106可連接於相鄰的浮體場環104a,但本發明並不以此為限。在另一些實施例中,導體層106可不連接於浮體場環結構104。舉例來說,請參照圖2A與圖2G,可將圖2A中的導體層106與浮體場環104a設置成相隔一距離,而形成圖2G中的不連接於浮體場環結構104的導體層106。在另一些實施例中,亦可將圖2B至圖2F中的導體層106設置成不連接於浮體場環結構104。As shown in FIGS. 2A to 2F , the
在另一些實施例中,導體層106可通過至少一個浮體場環結構104a。如圖2H所示,導體層106通過一個浮體場環結構104a,但本發明並不以此為限。在其他實施例中,如圖2I所示,導體層106可通過兩個浮體場環結構104a。In some other embodiments, the
此外,半導體結構10更可包括半導體元件108。半導體元件108可為主動元件,如功率元件。在一些實施例中,半導體元件108例如是金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field-effect transistor,MOSFET)、二極體(diode)或絕緣閘雙極電晶體(insulated gate bipolar transistor,IGBT)等。In addition, the
半導體元件108可包括摻雜區110與摻雜區112。摻雜區110位在半導體元件區R的半導體層102中。摻雜區110可具有第二導電型(如,P型)。摻雜區112位在基底100中,且鄰近於半導體層102。在一些實施例中,摻雜區112可均勻分布在整個基底100中。摻雜區112可具有第一導電型(如,N型)。The
此外,半導體元件108更可包括井區114與摻雜區116中的至少一者。井區114位在半導體元件區R的半導體層102中。井區114可具有第二導電型(如,P型)。摻雜區110位在井區114中。另外,摻雜區110的摻雜濃度可大於浮體場環104a的摻雜濃度與井區114的摻雜濃度。摻雜區116位在浮體場環結構104的遠離半導體元件區R的一側的半導體層102中。另一方面,半導體元件108更可依據元件類型包括其他所需的構件,於此省略其說明。In addition, the
在一些實施例中,依據半導體元件108的類型,摻雜區116可為第一導電型(如,N型)或第二導電型(如,P型)。在一些實施例中,在摻雜區116為第一導電型(如,N型)的情況下,摻雜區116可耦接於摻雜區112,但本發明並不以此為限。In some embodiments, according to the type of the
另外,半導體結構10更可包括摻雜區118。摻雜區118位在浮體場環結構104與摻雜區116之間的半導體層102中。摻雜區118可具有第一導電型(如,N型)。摻雜區118可作為通道終止區(channel stop region)。In addition, the
基於上述實施例可知,在半導體結構10中,導體層106位在浮體場環104a的一側,藉此可改變浮體場環結構104所產生的能帶,且對電場造成干擾。因此,藉由導體層106可達到分散電場的效果,進而提升半導體元件108的崩潰電壓。另外,由於半導體結構10可提升半導體元件108的崩潰電壓,因此即使縮小浮體場環結構104的面積,也可以維持與現有技術相同的崩潰電壓,且可具有更小的元件尺寸。另一方面,半導體結構10的製程可輕易地與現行製程進行整合。Based on the above-mentioned embodiments, in the
綜上所述,在上述實施例的半導體結構中,可藉由位在浮體場環一側的導體層來達到分散電場的效果,因此可提升半導體元件的崩潰電壓。To sum up, in the semiconductor structure of the above embodiments, the effect of electric field dispersion can be achieved by the conductor layer on one side of the field ring of the floating body, so the breakdown voltage of the semiconductor device can be increased.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.
10: 半導體結構
100: 基底
102: 半導體層
104: 浮體場環結構
104a: 浮體場環
106: 導體層
108: 半導體元件
110, 112, 116, 118: 摻雜區
114: 井區
BS1, BS2: 底面
OP: 開口
R: 半導體元件區
TS: 頂面
W: 寬度
10: Semiconductor Structure
100: base
102: Semiconducting layer
104: Floating Body
圖1為根據本發明一實施例的半導體結構的上視圖。 圖2A為沿著圖1中的I-I’剖面線的半導體結構的剖面圖。 圖2B至圖2I為本發明另一些實施例的沿著圖1中的I-I’剖面線的半導體結構的剖面圖。 FIG. 1 is a top view of a semiconductor structure according to an embodiment of the present invention. 2A is a cross-sectional view of the semiconductor structure along the line I-I' in FIG. 1 . 2B to 2I are cross-sectional views of semiconductor structures along the line I-I' in FIG. 1 according to other embodiments of the present invention.
10: 半導體結構
100: 基底
102: 半導體層
104: 浮體場環結構
104a: 浮體場環
106: 導體層
108: 半導體元件
110, 112, 116, 118: 摻雜區
114: 井區
BS1, BS2: 底面
R: 半導體元件區
TS: 頂面
W: 寬度
10: Semiconductor Structure
100: base
102: Semiconducting layer
104: Floating Body
Claims (16)
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| US9391271B1 (en) * | 2014-12-31 | 2016-07-12 | Powerchip Technology Corporation | Resistive random access memory and manufacturing method thereof |
| US9419053B2 (en) * | 2014-11-25 | 2016-08-16 | Powerchip Technology Corporation | Resistive random access memory structure and method for operating resistive random access memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9419053B2 (en) * | 2014-11-25 | 2016-08-16 | Powerchip Technology Corporation | Resistive random access memory structure and method for operating resistive random access memory |
| US9391271B1 (en) * | 2014-12-31 | 2016-07-12 | Powerchip Technology Corporation | Resistive random access memory and manufacturing method thereof |
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