JP2008294028A - Semiconductor device - Google Patents

Abstract

An object of the present invention is to improve the breakdown voltage of a semiconductor device having a super junction structure.
[Solution]
A drift layer having a pillar structure in which columnar first-conductivity-type first semiconductor layers and second-conductivity-type second semiconductor layers are alternately and periodically formed is formed on a semiconductor substrate. In the termination region around the element region, the first conductivity type impurity of the pillar structure is excessive with respect to the second conductivity type impurity. In the termination region, the edge portion of the electrode layer formed on the pillar structure via the interlayer insulating layer to be connected to the gate of the transistor or the bent portion of less than 180 degrees is the second conductivity type semiconductor having the pillar structure in the termination region. It is formed immediately above the layer.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device, and more particularly to a power semiconductor device having a high breakdown voltage structure.

In response to the recent demand for miniaturization and high performance of power supply equipment in the field of power electronics, power semiconductor elements have been focused on improving performance against low loss and high speed as well as high withstand voltage and high current. .
Among them, a power MOSFET (Metal Oxide Field Effect Effect Transistor) has a high-speed switching performance and has been established as a key device in the field of switching power supplies.

  Since a MOSFET is a majority carrier device, it has the advantage of fast switching with no minority carrier accumulation time. However, on the other hand, since there is no conductivity modulation, a high breakdown voltage element is disadvantageous in terms of on-resistance as compared with a bipolar element such as an IGBT (Insulated Gate Bipolar Transistor). This is because, in order to obtain a high breakdown voltage in the MOSFET, it is necessary to increase the thickness of the drift layer and reduce the impurity concentration. Therefore, the higher the breakdown voltage, the higher the on-resistance of the MOSFET.

  The on-resistance of the power MOSFET greatly depends on the electric resistance of the conductive layer (N-type drift layer) portion. The impurity concentration that determines the electrical resistance of the N-type drift layer has an upper limit because it corresponds to the breakdown voltage of the PN junction formed by the P-type base and the N-type drift layer. Therefore, there is a trade-off relationship between element breakdown voltage and on-resistance. Improving this trade-off is important for realizing a low power consumption element.

  This trade-off has a limit because it is determined by the material of the element, and exceeding this limit leads to the realization of a low on-resistance element exceeding the existing power element.

  In order to solve this problem, a structure called a super junction structure in which a P-type drift layer (P-type pillar layer) is embedded in an N-type drift layer (N-type pillar layer) is known. Specifically, in Patent Documents 1 and 2, the drift layer is formed by a parallel PN layer in which N-type regions and P-type regions having an increased impurity concentration are alternately arranged. A semiconductor device having a structure in which the breakdown voltage is maintained is disclosed.

  In the semiconductor devices described in Patent Documents 1 and 2, as a method of forming an N-type pillar layer and a P-type pillar layer, an N-type semiconductor layer is formed by epitaxial growth, a resist pattern is formed, and boron (B) After repeating a series of processes of forming a P-type semiconductor region by removing ions, removing a resist pattern, and epitaxially growing another N-type semiconductor layer, a P-type pillar layer and an N-type pillar are formed by thermal diffusion. A method of alternating layers is disclosed.

  Such a semiconductor device in which P-type pillar layers and N-type pillar layers are alternately formed has an element region in which a transistor is formed and a termination region in which a transistor surrounding the periphery is not formed.

Even in the case where a transistor is not formed in the termination region, a P-type pillar layer and an N-type pillar layer may be alternately formed in the termination region due to a process or the like. There is a problem that the breakdown voltage of the region is lowered and the entire semiconductor device is destroyed. Specifically, a breakdown voltage drop due to a leak current due to local electric field concentration in the termination region, or a breakdown due to hot carriers occurs.
JP 2000-40822 A JP 2001-168036 A

  An object of the present invention is to increase the breakdown voltage of a semiconductor device having a so-called super junction structure.

  A semiconductor device according to one embodiment of the present invention includes a pillar in which a columnar first conductive type first semiconductor layer and a second conductive type second semiconductor layer are alternately and periodically formed on a semiconductor substrate. A semiconductor device having a drift layer having a structure, wherein an element region in which a plurality of transistors each including the first semiconductor layer and the second semiconductor layer are arranged, and a periphery of the element region, A termination region in which the first conductivity type impurity in the pillar structure drift layer in which no transistor is formed is excessive with respect to the second conductivity type impurity, and is connected to the gate of the transistor in the termination region Therefore, an electrode layer formed on the pillar structure via an interlayer insulating layer is provided, and an edge portion of the electrode layer or a bent portion of less than 180 degrees is a second of the pillar structure in the termination region. Characterized in that it is formed directly on the conductive type semiconductor layer.

  In the semiconductor device according to one embodiment of the present invention, a columnar first conductive type first semiconductor layer and a second conductive type second semiconductor layer are alternately and periodically formed over a semiconductor substrate. A semiconductor device having a drift layer having a pillar structure, wherein an element region in which a plurality of transistors each including the first semiconductor layer and the second semiconductor layer are arranged, and a periphery of the element region. And a termination region in which the first conductivity type impurity in the pillar structure drift layer in which the transistor is not formed is excessive with respect to the second conductivity type impurity, and in the termination region, on the pillar structure An edge portion of an electrode terminal formed through an interlayer insulating layer or a bent portion of less than 180 degrees is formed immediately above the second conductivity type semiconductor layer of the pillar structure.

  In the semiconductor device according to one embodiment of the present invention, a columnar first conductive type first semiconductor layer and a second conductive type second semiconductor layer are alternately and periodically formed over a semiconductor substrate. A semiconductor device having a drift layer having a pillar structure, wherein an element region in which a plurality of transistors each including the first semiconductor layer and the second semiconductor layer are arranged, and a periphery of the element region. And a termination region in which the first conductivity type impurity in the pillar structure drift layer in which the transistor is not formed is excessive with respect to the second conductivity type impurity, and in the termination region, the pillar structure A first conductivity type resurf layer formed between the drift layer and the interlayer insulating layer, wherein an edge portion of the resurf layer or a bent portion of less than 180 degrees is the second conductivity type semiconductor layer of the pillar structure; Straight Characterized in that it is formed in.

  A semiconductor device according to one embodiment of the present invention is a semiconductor device including a drift layer having a pillar structure in which columnar N-type semiconductor layers and P-type semiconductor layers are alternately and periodically formed over a semiconductor substrate. An element region in which a plurality of transistors each composed of the N-type semiconductor layer and the P-type semiconductor layer are arranged, and a drift layer having the pillar structure around the element region where the transistor is not formed And an electrode layer formed on the pillar structure via an interlayer insulating layer to connect to the gate of the transistor in the termination region, and an edge portion in the electrode layer, or 180 Among the bent portions less than the degree, the edge portion or the bent portion existing on the side closer to the element region than the reference position is formed immediately above the P-type semiconductor layer, The edge portion or the bent portion exists farther to as seen from the device region than reference position is characterized by being formed directly on the N-type semiconductor layer.

  A semiconductor device according to one embodiment of the present invention is a semiconductor device including a drift layer having a pillar structure in which columnar N-type semiconductor layers and P-type semiconductor layers are alternately and periodically formed over a semiconductor substrate. An element region in which a plurality of transistors each composed of the N-type semiconductor layer and the P-type semiconductor layer are arranged, and a drift layer having the pillar structure around the element region where the transistor is not formed A terminal region having an electrode terminal formed on the pillar structure via an interlayer insulating layer, and an edge portion of the electrode terminal or a bent portion of less than 180 degrees The edge portion or the bent portion present on the side closer to the element region than the reference position is formed immediately above the P-type semiconductor layer, and is on the side farther from the element region than the reference position. The edge portion or the bent portion exists is characterized by being formed directly on the N-type semiconductor layer.

  The present invention can easily increase the breakdown voltage of a semiconductor device having a so-called super junction structure.

[First Embodiment]
One embodiment of the present invention will be described below. A semiconductor device in this embodiment mode is shown in FIG. The semiconductor device in this embodiment is a power semiconductor device, and is composed of an element region 1 and a termination region 2.

  The transistor formed in the element region 1 has a super junction structure (pillar structure) including an N-type drift layer 11 and a plurality of P-type pillar layers 12 formed in the N-type drift layer 11. Yes. An N + type drain layer 13 having an impurity concentration higher than that of the N type drift layer 11 is formed on one surface of the N type drift layer 11 (the lower surface in FIG. 1). A drain electrode (not shown) is formed.

  In the present embodiment, the drift layer 14 includes the N-type drift layer 11 and the P-type pillar layer 12. The N type drift layer 11 and the N + type drain layer 13 can be formed by diffusing impurities on one side of the N type drift layer 11 or by growing the N type drift layer 11 using the N + type drain layer 13 as a substrate. Formed by the method.

  As described above, the P-type pillar layer 12 is periodically formed on the surface of the N-type drift layer 11 where the N + type drain layer 13 is not formed. The N-type drift layer 11 formed between the adjacent P-type pillar layer 12 and the P-type pillar layer 12 may be referred to as an N-type pillar layer 11A separately. In a region extending on the surface of the P-type pillar layer 12, a P-type base layer 15 is formed by ion implantation. Two N-type source layers 16 are formed on the surface of each P-type base layer 15 thus formed.

  Further, the surface of the N-type drift layer 11 sandwiched between the adjacent P-type base layer 15 and the P-type base layer 15, that is, between the adjacent N-type source layer 16 and the N-type source layer 16, In the meantime, a gate insulating film 18 is formed in the surface region having the N-type drift layer 11 sandwiched between the P-type base layers 15. The gate insulating film 18 is made of, for example, a silicon oxide film having a thickness of about 0.1 [μm].

  Further, a gate electrode 19 is formed on the gate insulating film 18, and the gate electrodes 19 are connected to each other. An interlayer insulating film 20 is formed on the gate electrode 19.

  In a region sandwiched between the gate electrode 19 and the gate electrode 19, the source electrode is in contact with the P-type base layer 15 and the two N-type source layers 16 provided in the P-type base layer 15. 17 is formed. The source electrode 17 is formed so as to cover the interlayer insulating film 20, and is connected to each. Further, the source electrode 17 and the gate electrode 19 are electrically insulated through the interlayer insulating film 20.

  On the other hand, also in the termination region 2, the N-type drift layer 11 (including the N-type pillar layer 11A) and the P-type pillar layer 12 are formed, and a super junction structure (pillar structure) is formed. In the termination region 2, a P + type guard ring layer 21 is formed by ion implantation on the surface in the vicinity of the element region 1 where the N type drift layer 11 and the P type pillar layer 12 are formed. The surface of the layer 21 is in contact with the source electrode 17.

  In the termination region 2, a P-type RESURF layer 22 is formed on the surface so as to be in contact with the P + -type guard ring layer 21 and spread on the opposite side to the element region 1. Further, an interlayer insulating film 23 is formed on the surface of the P-type RESURF layer 22, the N-type drift layer 11, and the P-type pillar layer 12 in the termination region 2, and the connection with the gate electrode 19 is formed in the inside. A field plate 24 is formed and connected to the gate terminal 25.

  Next, the configuration of the semiconductor device in this embodiment will be described in more detail. The semiconductor device according to the present embodiment relates to a structure for preventing destruction of the semiconductor device due to a decrease in breakdown voltage in the termination region 2 or the like.

  FIG. 2 shows the structure of the termination region in the present embodiment. 2A is a top view and FIG. 2B is a cross-sectional view. 3A shows an enlarged cross-sectional view of FIG. 2B, and FIG. 3B shows an electric field distribution in the drift layer 14 including the P-type pillar layer 12 and the N-type pillar layer 11A. .

  In the present embodiment, the drift layer 14 composed of the P-type pillar layer 12 and the N-type pillar layer 11A in the termination region is N-rich with more N-type impurities than P-type impurities, and FIG. The electric field distribution is as shown.

  In the case where the drift layer 14 is N-rich, if the edge of the conductive member such as an electrode is formed so as to be located immediately above the N-type pillar layer 11A, between the edge of the electrode and the N-type pillar layer 11A, As a result of researches, the inventors have obtained a phenomenon that destruction tends to occur. The present embodiment is based on this result and is characterized in that the edge portion of the electrode or the like and the bending position of the electrode or the like are formed on the P-type pillar layer 12 instead of on the N-type pillar layer 11A. It is.

  Specifically, the P + type guard ring layer 21 and the P type RESURF layer 22 are formed on the drift layer 14 composed of the P type pillar layer 12 and the N type pillar layer 11A. Both end positions a 1 and a 8 of the P-type RESURF layer 22 are formed at positions directly above the P-type pillar layer 12.

  Further, an interlayer insulating film 23 is formed thereon, and a field plate 24 for connection to a gate electrode (not shown) is formed therein. At both end positions a2 and a6 of the field plate 24 and the field plate 24, the bending positions a3 and a4 having a predetermined angle, for example, a narrow angle of less than 180 degrees (in FIG. 3, the bending angle is approximately 90 °) are respectively P It is formed at a position directly above the mold pillar layer 12.

  Furthermore, a gate electrode 25 connected to the source electrode 17 and the field plate 24 is formed thereon as a metal electrode. At the end position a2 of the source electrode 17, the both end positions (edges) a3 and a7 of the gate terminal 25, and the gate terminal 25, the bent positions a4 and a5 having a predetermined angle, for example, less than 180 degrees are directly above the P-type pillar layer 12. It is formed in the position.

  Note that not only the edges of electrodes and the like, but also the bent positions at a narrow angle of a predetermined angle, for example, less than 180 degrees, are targeted because the electric field tends to concentrate at the bent positions of the electrodes, and the breakdown is particularly likely to occur. This is because these parts can also be considered in the same manner as both end positions (edges). Here, the angle at the bending position is defined as less than 180 degrees, but depending on the situation, an angle of 120 degrees or less may be defined as the bending position, or an angle of about 90 degrees or less may be defined. It may be defined as a bending position.

  As described above, when the drift layer 14 composed of the P-type pillar layer 12 and the N-type pillar layer 11A in the termination region is in the N-rich state, the P-type RESURF layer 22, the field plate 24, the source electrode 17, and the gate terminal Since the edge of 25 and the bending position of an angle narrower than a predetermined angle are formed immediately above the P-type pillar layer 12 and not directly above the N-type pillar layer 11A, they are resistant to breakdown without causing a decrease in breakdown voltage. A semiconductor device can be obtained.

[Second Embodiment]
Next, the structure of the semiconductor device in this embodiment is described. FIG. 4 shows the structure of the termination region in the present embodiment. 4A is a top view and FIG. 4B is a cross-sectional view. 5A shows an enlarged cross-sectional view of FIG. 4B, and FIG. 5B shows an electric field distribution in the drift layer 34 including the P-type pillar layer 32 and the N-type pillar layer 31A. .

  In the present embodiment, the drift layer 34 composed of the P-type pillar layer 32 and the N-type pillar layer 31A in the termination region is P-rich with more P-type impurities than N-type impurities, and FIG. The electric field distribution is as shown.

  In the case where the drift layer 34 is P-rich, if the edge of the conductive member such as an electrode is formed so as to be located immediately above the P-type pillar layer 32, the edge between the edge of the electrode and the P-type pillar layer 32, As a result of researches, the inventors have obtained a phenomenon that destruction tends to occur. The present embodiment is based on this result and is characterized in that the edge portion of the electrode or the like and the bending position of the electrode or the like are formed not on the P-type pillar layer 32 but on the N-type pillar layer 31A. It is.

  Specifically, the P + type guard ring layer 41 and the P type RESURF layer 42 are formed on the drift layer 34 composed of the P type pillar layer 32 and the N type pillar layer 31A. Both end positions b1 and b8 of the P-type RESURF layer 42 are formed at positions directly above the N-type pillar layer 31A. Further, an interlayer insulating film 43 is formed thereon, and a field plate 44 for connection to a gate electrode (not shown) is formed therein.

  In both end positions b2 and b6 of the field plate 44 and the field plate 44, bent positions b3 and b4 having an angle narrower than a predetermined angle are formed at positions directly above the N-type pillar layer 31A.

  Furthermore, a gate electrode 45 connected to the source electrode 37 and the field plate 44 is formed thereon as a metal electrode. At the end position b2 of the source electrode 37, both end positions b3 and b7 of the gate terminal 45, and the gate terminal 45, the bent positions b4 and b5 having an angle narrower than a predetermined angle are formed at positions directly above the N-type pillar layer 31A. The

  Note that not only the edges of electrodes etc., but also the bent position of an angle narrower than a predetermined angle are targeted, because electric field concentration tends to occur at the bent position of the electrode, and this is particularly likely to cause destruction. This is because the bent positions can be considered in the same manner as the edges.

  As described above, when the drift layer 34 composed of the P-type pillar layer 32 and the N-type pillar layer 31A in the termination region is in the P-rich state, the P-type RESURF layer 42, the field plate 44, the source electrode 37, and the gate terminal Since the edge of 45 and the bending position of an angle narrower than a predetermined angle are formed immediately above the N-type pillar layer 31A and not directly above the P-type pillar layer 32, they are resistant to breakdown without causing a decrease in breakdown voltage. A semiconductor device can be obtained.

[Third Embodiment]
Next, the structure of the semiconductor device in this embodiment is described. FIG. 6 shows the structure of the termination region in the present embodiment. 6A is a top view, and FIG. 6B is a cross-sectional view. 7A shows an enlarged cross-sectional view of FIG. 6B, and FIG. 7B shows an electric field distribution in the drift layer 54 including the P-type pillar layer 52 and the N-type pillar layer 51A. .

  In the present embodiment, in the drift layer 54 composed of the P-type pillar layer 52 and the N-type pillar layer 51A in the termination region, the P-type impurity and the N-type impurity are in substantially the same state, and FIG. ) As shown in FIG.

In the case where the impurity concentration in the drift layer 34 is almost the same, the phenomenon that the edge of a conductive member such as an electrode or a bent portion of less than 180 degrees is likely to break if the following positional relationship exists. The inventors obtained as a result of research.
(1) On the side closer to the element region than the certain reference position (inward direction), the edge or bent portion of the electrode or the like is located immediately above the N-type pillar layer. (2) As viewed from the element region than the certain reference position. The edge or bent part of the electrode or the like is located immediately above the P-type pillar layer on the far side (outward direction). This embodiment is based on this result, and the edge part of the electrode and the like such as the electrode Among the bending positions, those existing in the inner direction are formed on the P-type pillar layer 52, and those existing in the outer direction among the edge portions of the electrodes and the bending positions of the electrodes are N It is formed on the mold pillar layer 51. The boundary between the inner direction and the outer direction in the present embodiment is based on the center of the contact surface between the gate terminal 65 and the field plate 64.

  Specifically, the P + type guard ring layer 61 and the P type RESURF layer 62 are formed on the drift layer 54 composed of the P type pillar layer 52 and the N type pillar layer 51A. Of both end positions (edges) of the P-type RESURF layer 62, an end position (edge) c <b> 1 in the inner direction is formed at a position directly above the P-type pillar layer 52. Further, an end position (edge) c8 in the outer direction is formed at a position directly above the N-type pillar layer 51A.

  Further, an interlayer insulating film 63 is formed thereon, and a field plate 64 for connection with a gate electrode (not shown) is formed therein. Of the both end positions of the field plate 64, an end position (edge) c <b> 2 in the inner direction is formed at a position directly above the P-type pillar layer 52. Further, an end position (edge) c6 in the outer direction is formed at a position directly above the N-type pillar layer 51A. Further, in the field plate 64, the bending positions c3 and c4 having an angle narrower than a predetermined angle are both positioned inward of the center of the contact surface between the gate terminal 65 and the field plate 64, and thus the P-type pillar layer. It is formed at a position directly above 52.

  Furthermore, a gate electrode 65 connected to the source electrode 57 and the field plate 64 is formed thereon as a metal electrode. An end position (edge) c <b> 3 in the inner direction among the end position c <b> 2 of the source electrode 57 and the both end positions of the gate terminal 65 is formed at a position directly above the P-type pillar layer 52.

  Further, of the both end positions of the gate terminal 65, the end position (edge) c7 in the outer direction is formed at a position directly above the N-type pillar layer 51A. In the gate terminal 65, the end position c <b> 4 (edge) in the inner direction is formed at a position directly above the P-type pillar layer 52 among the bent positions having an angle smaller than a predetermined angle. An end position (edge) c5 in the outer direction is formed at a position immediately above the N-type pillar layer 51A.

  As described above, in the state where the drift layer 54 composed of the P-type pillar layer 52 and the N-type pillar layer 51A in the termination region is neither N-rich nor P-rich and the charge balance is maintained, the P-type RESURF layer 62, Of the edge of the field plate 64, the source electrode 57, and the gate terminal 65 and the bending position narrower than a predetermined angle, the one located in the inner direction is formed immediately above the P-type pillar layer 52 and located in the outer direction. Since the semiconductor device is formed immediately above the N-type pillar layer 51A, a semiconductor device that is resistant to breakdown can be obtained without causing a decrease in breakdown voltage. In the present embodiment, when the drift layer 54 is unknown whether it is N-rich or P-rich, it is most resistant to destruction.

  As described above, in the super junction structure MOS transistor, the breakdown voltage can be improved without greatly increasing the leakage current at the time of reverse bias.

  As described above, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately added and combined.

Structure overview of a semiconductor device with a super junction structure Structure diagram of the semiconductor device in the first embodiment Structure enlarged view of the semiconductor device in the first embodiment Structure diagram of semiconductor device according to second embodiment Structure enlarged view of semiconductor device according to second embodiment Structure diagram of semiconductor device according to third embodiment The structure enlarged view of the semiconductor device in 3rd Embodiment

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Element area | region, 2 ... Termination area | region, 11A ... N-type pillar layer, 12 ... P-type pillar layer, 14 ... Drift layer, 17 ... Source electrode, 21 ... P + type guard ring layer, 22 ... P type RESURF layer, 23 ... interlayer insulation film, 24 ... field plate, 25 ... gate terminal

Claims (5)

A semiconductor device having a drift layer having a pillar structure in which columnar first conductivity type first semiconductor layers and second conductivity type second semiconductor layers are alternately and periodically formed on a semiconductor substrate,
An element region in which a plurality of transistors each composed of the first semiconductor layer and the second semiconductor layer are arranged;
A termination region in which the first conductivity type impurity in the drift layer of the pillar structure around the element region where the transistor is not formed is excessive with respect to the second conductivity type impurity; and
In the termination region, comprising an electrode layer formed on the pillar structure via an interlayer insulating layer to connect to the gate of the transistor,
An edge part of the electrode layer or a bent part of less than 180 degrees is formed immediately above the second conductivity type semiconductor layer of the pillar structure in the termination region. A semiconductor device having a drift layer having a pillar structure in which columnar first conductivity type first semiconductor layers and second conductivity type second semiconductor layers are alternately and periodically formed on a semiconductor substrate,
An element region in which a plurality of transistors each composed of the first semiconductor layer and the second semiconductor layer are arranged;
A termination region in which the first conductivity type impurity in the drift layer of the pillar structure around the element region where the transistor is not formed is excessive with respect to the second conductivity type impurity, and the termination In the region, an edge portion of an electrode terminal formed on the pillar structure via an interlayer insulating layer or a bent portion of less than 180 degrees is formed immediately above the second conductivity type semiconductor layer of the pillar structure. A semiconductor device. A semiconductor device having a drift layer having a pillar structure in which columnar first conductivity type first semiconductor layers and second conductivity type second semiconductor layers are alternately and periodically formed on a semiconductor substrate,
An element region in which a plurality of transistors each composed of the first semiconductor layer and the second semiconductor layer are arranged;
A termination region in which the first conductivity type impurity in the drift layer of the pillar structure around the element region where the transistor is not formed is excessive with respect to the second conductivity type impurity, and the termination In the region, a resurf layer of the first conductivity type formed between the drift layer of the pillar structure and the interlayer insulating layer,
An edge portion of the RESURF layer or a bent portion of less than 180 degrees is formed immediately above the second conductivity type semiconductor layer of the pillar structure. A semiconductor device having a pillar structure drift layer in which columnar N-type semiconductor layers and P-type semiconductor layers are alternately and periodically formed on a semiconductor substrate,
An element region in which a plurality of transistors each composed of the N-type semiconductor layer and the P-type semiconductor layer are arranged;
A termination region having a drift layer of the pillar structure around the element region and in which the transistor is not formed; Comprising an electrode layer formed through an insulating layer;
Of the edge part in the electrode layer or the bent part of less than 180 degrees, the edge part or the bent part existing on the side closer to the element region than the reference position is formed immediately above the P-type semiconductor layer,
The semiconductor device according to claim 1, wherein the edge portion or the bent portion existing on a side farther from the element region than the reference position is formed immediately above the N-type semiconductor layer. A semiconductor device having a pillar structure drift layer in which columnar N-type semiconductor layers and P-type semiconductor layers are alternately and periodically formed on a semiconductor substrate,
An element region in which a plurality of transistors each composed of the N-type semiconductor layer and the P-type semiconductor layer are arranged;
And a termination region having a drift layer of the pillar structure in which the transistor is not formed around the element region, and the termination region is formed on the pillar structure via an interlayer insulating layer With electrode terminals,
Of the edge portion of the electrode terminal or the bent portion of less than 180 degrees, the edge portion or the bent portion present on the side closer to the element region than the reference position is formed immediately above the P-type semiconductor layer,
The semiconductor device according to claim 1, wherein the edge portion or the bent portion existing on a side far from the element region from the reference position is formed immediately above the N-type semiconductor layer.

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