TWI773018B - Recovery boosting circuit and ldo regulator with output-drop recovery - Google Patents

Abstract

An electronic circuit for voltage regulation includes a voltage regulator and a recovery boosting circuit. The recovery boosting circuit is configured to detect a voltage drop occurring in an output voltage of the voltage regulator, to generate (i) a first electrical current that is derived from the output voltage of the voltage regulator and (ii) a second electrical current that is derived from a supply voltage of the voltage regulator, to generate a pulse whose energy depends on the first electrical current and on the second electrical current, and to assist the voltage regulator in recovering from the voltage drop, by applying the pulse to the voltage regulator.

Description

Recovery booster circuit, electronic circuit for voltage regulation and method thereof

The present invention mainly relates to a power supply circuit system, in particular to a voltage regulation method and system with output voltage drop recovery.

Low-dropout (LDO) voltage regulators are commonly used in electronic circuit power supplies. Various low pressure drop pressure configurations are common knowledge in the art. For example, US Pat. No. 7,199,565 describes a low-dropout voltage regulator that includes a start-up circuit, a curvature-corrected bandgap circuit, an error amplifier, a metal-oxide-semiconductor transfer device, and a voltage-slew rate-efficient transient response boost circuit. The metal-oxide-semiconductor transfer device has a gate node coupled to the output of the error amplifier, and a drain node that generates the output voltage. A voltage conversion efficiency transient response boost circuit applies a voltage to the gate node of the MOS pass device to speed up the error amplifier response time, enabling the LDR to achieve its final regulation when a voltage drop occurs The output voltage.

An embodiment of the invention described herein provides a recovery boost circuit. The recovery boost circuit is configured to: detect a voltage drop occurring in the output voltage of the voltage regulator; generate a first current from the output voltage of the voltage regulator; generate a pulse whose energy is related to the first current; and by applying the pulse to the voltage regulator to help the voltage regulator recover from voltage drops.

In another embodiment, the recovery boost circuit includes a cutoff circuit configured to cut off the pulse after a duration that depends on the first current.

In some embodiments, the recovery boost circuit is further configured to generate a second current from the supply voltage of the voltage regulator, and the energy of the pulse depends on the first and second currents.

In some embodiments, the voltage regulator includes a low dropout regulator having two stages, and a restore boost circuit configuration to apply pulses between the two stages.

In some embodiments, the voltage regulator includes an output stage having a resistive ladder, and the boost circuit configuration is restored to detect the voltage drop by comparing the first and second voltages obtained from the branches of the resistive ladder. In one embodiment, the recovery boost circuit includes (1) a low-pass filter configured to filter the first voltage; and (2) a comparator configured to compare the filtered first voltage with the second voltage to detect voltage drop.

In a disclosed embodiment, the energy of the pulse depends on the sum of the first current and the second current. In another embodiment, the recovery boost circuit includes a cutoff circuit configured to cut off the pulse after a duration that depends on the first current and the second current.

In another embodiment, the recovery boost circuit includes a Native Field-Effect Transistor (FET) configured to compensate for pulse variations caused by differences in supply voltages. In another embodiment, the recovery boost circuit includes a series capacitor configured to be charged in pulses and then discharged to apply the pulses to the voltage regulator. In another embodiment, the recovery boost circuit includes a native field effect transistor whose drain is connected to a voltage regulator for applying the pulse.

According to an embodiment of the present invention, the present invention further provides an electronic circuit for voltage regulation, which includes a voltage regulator and any one of the above recovery boosting circuits.

According to an embodiment of the present invention, the present invention further provides a voltage regulation method, which includes: detecting a voltage drop occurring in an output voltage of a voltage regulator; generating a first current derived from the output voltage of the voltage regulator; energy is associated with the first current; and by applying pulses to the voltage regulator, assisting the voltage regulator in recovering from the voltage drop.

According to an embodiment of the present invention, the present invention further provides an integrated circuit (IC), which includes: an electronic circuit system; and a voltage regulation circuit system configured to generate an output voltage for powering the electronic circuit system. The voltage regulation circuitry includes: a voltage regulator configured to generate an output voltage; and any of the recovery boost circuits described above.

20: Circuits

24: Low drop voltage regulator

26: load

28: Operational Transconductance Amplifier

32: P-type metal oxide semiconductor field effect transistor

36, 40, 52, 60: Restore boost unit

44: Low Pass Filter

48: Surge detector

56: Pulse generator

64: Differential Current Amplifier

70, 74, 78, 82, 86, 90, 94, 98: Curves

100: Integrated Circuits

104: Circuit System

FB: Feedback voltage

Vref: reference voltage

Vcc: power supply voltage

Vout: output voltage

R1A, R1B, R2: Resistors

The present invention will be fully understood from the following detailed description of its embodiments in conjunction with the accompanying drawings, wherein: FIG. 1 is a low drop voltage regulation with improved output voltage drop recovery according to an embodiment of the present invention. Figure 2 to Figure 4 are block diagrams of Recovery Boost Units (RBUs) for the low dropout voltage regulator of Figure 1 according to an embodiment of the present invention; Figure 5 is a block diagram of the RBUs according to the present invention. FIG. 4 is a circuit diagram of a differential amplifier used in a recovery boost unit of an embodiment of the invention; FIG. 6 is an analog performance of a low-dropout voltage regulator with and without improved output dropout recovery according to an embodiment of the invention. 7 is a block diagram of an integrated circuit including a low dropout voltage regulator with improved output dropout recovery according to an embodiment of the present invention.

Overview

Embodiments of the invention described herein provide improved methods and apparatus for voltage regulation. The disclosed technique improves the recovery of the voltage regulator from output voltage drops, which may be caused by, for example, transient changes in load conditions. The disclosed techniques are very effective in avoiding overshoot during recovery from voltage drops and perform well over a wide range of supply voltages.

In some embodiments, the electronic circuit includes a two-stage low-dropout voltage regulator, and a recovery boost unit. restoring the boost unit configuration to detect a voltage drop occurring in the output voltage of the low dropout voltage regulator, generate a pulse responsive to the detected voltage drop, and by applying the pulse to a midpoint between the two stages of the low dropout voltage regulator, to help the low dropout voltage regulator recover from voltage drops. Pulses generally help to draw current from the first stage output of the low dropout voltage regulator, thus increasing the speed at which the low dropout voltage regulator can respond to voltage drops.

In some disclosed embodiments, the recovery boost unit sets the energy (eg, pulse amplitude and/or duration) of the pulses according to (1) the actual output voltage including the voltage drop and (2) the actual supply voltage. In one embodiment, the recovery boost unit generates (1) a first current from the output voltage of the low dropout voltage regulator, and (2) a second current from the supply voltage. Dependencies are usually inverse dependencies, ie, lower output voltages and/or lower supply voltages translate into stronger pulses and vice versa. The recovery boost unit generates pulses based on these two currents.

By generating the pulses in this way, the pulse energy can be matched to the actual characteristics of the voltage drop (due to the dependence on the first current). Therefore, recovery is fast and accurate, and almost no overshoot occurs. In addition, recovery speed and accuracy (due to the dependence of the pulse on the second current) can be improved over a wide range of supply voltages.

In addition, the disclosed technique serves as a built-in protection mechanism that can actually disable the recovery boost unit during transitions of the low dropout voltage regulator, such as wake-up or transition from sleep mode to normal operation. The reliability of the recovery boost unit is thus significantly improved. The disclosed technique obviates the need to add dedicated protection hardware for this purpose, thus reducing size and cost.

Other advantageous features that contribute to high performance are, for example, the use of native field effect transistors and the use of a pair of voltages taken from the same resistor ladder to detect the voltage drop, which is also used in the output low drop voltage regulator the output voltage. The features of the recovery boost unit, the implementation of several examples, will be described and explained as follows.

System specification

FIG. 1 is a block diagram of a circuit 20 including a low dropout voltage regulator 24 with improved output dropout recovery in accordance with an embodiment of the present invention. The low dropout voltage regulator 24 provides power to a load 26, which may include any suitable circuitry. In many practical situations, instantaneous changes in the current consumption of the load 26 can cause a voltage drop in the output voltage of the low dropout voltage regulator 24 . It is important to recover quickly from this voltage drop with little overshoot. The manner in which the output voltage drop is recovered as described herein can help the low drop voltage regulator 24 to recover.

Circuit 20 can be used in a variety of systems that require a regulated power supply under different load conditions. A typical use case is a controller or other integrated circuit that can switch between sleep mode and normal mode.

In the embodiment of FIG. 1, the low dropout voltage regulator 24 comprises a two-stage low dropout voltage regulator. The first stage includes a differential amplifier, in this example an Operational Transconductance Amplifier (OTA) 28 . The second stage includes a P-type Metal-Oxide-Semiconductor Field-Effect Transistor (PMOS FET) 32, which is represented by M1 in the drawings. Both stages are connected to a supply voltage expressed as Vcc.

In this example, Vcc varies in the range of 1.8-3.3V. In some embodiments, an extension of about 1.7-3.6V may be considered. At 1.2V in this example, the regulated output voltage produced by the low dropout voltage regulator 24 is denoted as Vout.

The output of operational transconductance amplifier 28 may be used to drive the gate of P-type metal oxide semiconductor field effect transistor 32 . The midpoint between these two levels is denoted by VG. The output voltage Vout is taken from the source of the P-type metal oxide semiconductor field effect transistor 32 . The drain of the P-type metal oxide semiconductor field effect transistor 32 is connected to Vcc. The source of the PMOS transistor 32 (from which Vout is obtained) is grounded through a resistor ladder, which in this example includes three series resistors R1A, R1B, R2. The feedback voltage FB is taken from the node of R1B and R2 and fed back to one of the differential input terminals of the operational transconductance amplifier 28 . The other differential input terminal of the operational transconductance amplifier 28 is connected to the reference voltage Vref. For example, Vref can be generated by a bandgap voltage reference (not shown).

The electronic circuit 20 further includes a recovery boost circuit 36, which is also intended to be a recovery boost unit herein. Recovery boost unit 36 may detect a voltage drop occurring in Vout, and in response to detecting the voltage drop, may generate a current pulse at node VG. The energy (eg, amplitude and/or duration) and timing of the pulses are matched to the detected voltage drop characteristics. The pulses facilitate rapid discharge from node VG and are beyond the capability of operational transconductance amplifier 28 . Specifically, in a system operating at a low supply voltage of 1.8V, the current in the output branch of the operational transconductance amplifier is generally limited to keep the operational transconductance amplifier below saturation. Therefore, the bandwidth of the LDR feedback loop increases significantly during the pulse. The pulses produced by the recovery boost unit are therefore also referred to as "discharge pulses".

The presence of the pulse improves the recovery of the low drop voltage regulator 24 from voltage drops. In general, when assisted by the pulses generated by the recovery boost unit 36, the depth of the voltage drop in Vout is less, so the return to normal output voltage is faster. Attention must be paid to the effect of pulse energy on recovery performance have considerable impact. If the pulse energy is too small, the recovery ability will be relatively slow. If the pulse energy is too high, overshoot may occur in Vout. As described below, since the pulse energy setting using the disclosed technique is quite precise, the recovery speed is fast and there is little overshoot. This behavior can be achieved over a wide range of Vcc, eg between 1.8-3.3V. Examples of simulated performance with and without the assistance of the recovery boost unit 36 are shown in Figure 6 below.

In addition to Vcc and ground, the recovery boost unit 36 has two inputs and one output. The two inputs, denoted 1.20V and 1.15V in the diagram, are taken from two different branches (ie, voltage dividers) of the resistive ladder of the low dropout voltage regulator 24 . Indicates that an input of 1.20V is equal to Vout. Design the resistors in the resistor ladder so that the second input, expressed at 1.15V, is 50mV below Vout. The generated discharge pulse is supplied from the output of the recovery boost unit 36 to the node VG (the input of the operational transconductance amplifier, that is, the gate of the P-type metal oxide semiconductor field effect transistor 32, that is, the two terminals of the low-dropout voltage regulator 24). midpoint between stages).

Taking a 1.20V input and a 1.15V input from a resistor ladder is helpful for several reasons. First, the inputs at both ends match each other. Second, Vref is not loaded or used to provide these inputs. Third, glitch detection is performed directly on the Vout (1.20V) node, thus improving the speed and reliability of detection.

Restoring the boost unit configuration example

FIG. 2 is a block diagram of the recovery boosting unit 40 according to an embodiment of the present invention. This configuration can be used to implement the recovery boost unit 36 of FIG. 1 .

The recovery boost unit 40 receives as inputs two voltages, which are Vout and VrefA which is 50 mV lower than Vout. When there is a voltage drop in Vout, this voltage drop also occurs in VrefA. However, VrefA is filtered by a Low-Pass Filter (LPF) 44, which in this example is a resistor capacitor (resistance-capacitance, RC) filter. Due to the low-pass filtering, the output of the low-pass filter (represented by VrefA_Filter) is approximately constant at 1.15V, even during the voltage drop of Vout.

A glitch detector 48, which typically includes a high speed comparator, can be used to detect the voltage drop in Vout. The glitch detector 48 compares Vout to VrefA_Filter (a low pass filtered version of VrefA, ie 50mV lower than Vout). The output of glitch detector 48 will go high (equal to Vcc) whenever the instantaneous amplitude of Vout drops by more than 50mV. Otherwise, the output of the glitch detector 48 is low (0V). The output of glitch detector 48 is denoted BP1. In other words, the glitch detector 48 outputs a pulse of amplitude Vcc, which begins to generate when the voltage drops below 50 mV.

In the embodiment of FIG. 2 , the recovery boost unit 40 includes a native N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS FET), which is represented by NATIVE1. The gate of NATIVE1 is connected to Vout, and the drain of NATIVE1 is connected to BP1. The function of NATIVE1 is to clip the pulse amplitude at the output of the glitch detector 48 from Vcc to approximately Vout (1.2V), regardless of the actual value of Vcc. This operation helps match the pulse to voltage drop characteristics over a wide range of supply voltages.

The source of NATIVE1 is connected to a capacitor, designated C_BOOST, which couples the clipping pulse to the gate of another native NMOS FET, designated NATIVE2. C_BOOST charges rapidly at the beginning of the pulse and then gradually discharges.

The drain of NATIVE2 is connected to the midpoint VG (between the two stages of the low-dropout voltage regulator 24). The source of NATIVE2 is grounded by an additional NMOS field effect transistor, denoted by NDIS. NATIVE2 acts as a switch, turned on and off by pulses from BP2. When turned off, the recovery boost unit 40 draws current from VG to help the low dropout voltage regulator recover from voltage drops, as described above. The gate of the transistor NDIS is connected to BP1 , that is, to the output of the surge detector 48 . when When the output of the glitch detector 48 goes low (when the voltage drop is less than 50mV), the transistor NDIS can be used to terminate the pulse.

In view of the fact that the threshold voltage is about zero, the primary transistor is usually suitable for clipping the pulse (operating mode as NATIVE1), and suitable for switching current in response to the pulse (operating mode as NATIVE2). The native transistor NATIVE2 is particularly suitable for use because it has a relatively low input gate voltage of 1.2V (ie, the clipping result of NATIVE1, regardless of the supply voltage range). Additionally, primary transistors typically have a very small physical area and are capable of delivering high currents at the same time. However, the disclosed techniques are not limited to implementation using native transistors, and other suitable types of transistors may be used in alternative embodiments.

In an alternative embodiment, the transistor NDIS may be omitted. In one embodiment, the ideal condition is usually that the off current of NATIVE2 is negligible.

In this embodiment, the recovery boost unit 40 further includes two current sources configured to generate two currents denoted by I1 and I2. The current source for I1 consists of an N-type metal oxide semiconductor field effect transistor denoted N1A and a resistor R1A. This current source is powered by Vout, so I1 depends on Vout. In particular, the current I1 drops whenever a voltage drop occurs in Vout. The current source for I2 consists of an N-type metal-oxide-semiconductor field effect transistor denoted N2A and a resistor R2A. This current source is powered by Vcc, so I2 depends on Vcc.

The recovery boost unit 40 includes two current mirrors using N-type metal oxide semiconductor field effect transistors N1B and N2B. N1B and N2B use bias voltages BIAS1 and BIAS2 to mirror currents I1 and I2, respectively. The sum of the two currents (I1+I2) can be applied to BP2. In other words, node BP2 can be discharged using two current sources.

The energy of the discharge pulses discharged at node BP2 depends on Vout and Vcc, and their dependencies are usually inversely dependent, ie, lower Vout and/or lower Vcc translate into higher energy pulses and vice versa. More specifically, the discharge pulse energy, which defines the discharge current strength at VG, follows the state of Vout during the actual Vout buck, and serves as a real-time negative feedback for the discharge pulse. The energy of the discharge pulse decays slowly as Vout drops deeper and/or longer, and quickly decays as Vout drops back.

This dependence thus causes the pulse energy to match the actual characteristics of the Vout voltage drop in real time and over a wide range of Vcc. Therefore, recovery from voltage drops is fast and almost no overshoot occurs.

As described above, the disclosed techniques can act as a built-in protection mechanism to prevent the low dropout voltage regulator 24 from discharging at VG during transitions (eg, wake-up or transition from sleep mode to normal operation). During this transition, the levels of Vout and VrefA may be difficult to stabilize, and it may be difficult to activate the glitch detector 48 to generate an output "1" until the low dropout voltage regulator 24 stabilizes. However, the resulting discharge pulses are very short relative to this transition (eg, wake-up time), thus keeping the output of the glitch detector at "0" for most of the transition, allowing the low dropout voltage regulator 24 keep it steady.

Also, since Vout and VrefA are taken from the same resistor ladder, the design guarantees that Vout will be higher than VrefA. This guarantee also applies during the conversion process.

FIG. 3 is a block diagram of the recovery boosting unit 52 according to an embodiment of the present invention. This configuration can also be used to implement the recovery boost unit 36 of FIG. 1 . The recovery boost unit 52 is similar in structure and operation to the recovery boost unit 40 of FIG. 2 except for the following differences.

The first difference between this embodiment and the above-mentioned embodiment is that, in this embodiment, the recovery boosting unit omits the capacitor C_BOOST.

The second difference between this embodiment and the above-described embodiments is that, in this embodiment, the pulse generator 56 generates pulses based on the currents I1 , I2 and the output of the surge detector 48 . In general, pulse generator 56 is triggered by the output of glitch detector 48 . When triggered, the pulse generator generates a pulse whose duration depends on the sum of currents I1 and I2 (I1+I2). This pulse controls an N-type metal-oxide-semiconductor field effect transistor, denoted NCUT, which is connected in series with transistor NATIVE2 and transistor NDIS in a drain-to-gate manner. Using a transistor NCUT, the pulse generator 56 starts a pulse when the output of the glitch detector goes high, and stops the pulse after a desired duration.

The arrangement of the recovery boosting units in FIGS. 2 and 3 is also different from each other in the shape of the discharge pulse. The pulses generated by the recovery boost unit 36 (FIG. 2) typically have monotonically decreasing amplitudes. The pulses generated by the recovery boost unit 40 (FIG. 3) have approximately constant amplitude.

FIG. 4 is a block diagram of a recovery boosting unit 60 according to another embodiment of the present invention. This configuration can also be used to implement the recovery boost unit 36 of FIG. 1 . The example of Figure 4 shows another way of controlling the pulse energy as a function of I1 and I2 (and also as a function of Vout and Vcc).

In this example, current I2 is generated and mirrored to BP2, as shown by recovery boost unit 40 in FIG. 2 . On the other hand, in order to generate the current I1, the recovery boost unit 60 includes a differential current amplifier 64 (usually an operational amplifier, used as an error amplifier). The two differential inputs of amplifier 64 are connected to Vout and VrefA_Filter. The voltage NBIAS1 is derived from the current branch output of amplifier 64 . NBIAS1 depends on the depth of the voltage drop in Vout. NMOS transistor N1B uses voltage NBIAS1 to mirror currents I1 to BP2.

FIG. 5 is a circuit diagram of the amplifier 64 used in the recovery boosting unit 60 of FIG. 4 according to an embodiment of the present invention. Amplifier 64 is used to generate current I1 with high gain and to track the real-time waveform of the voltage drop of Vout. Amplifier 64 is a differential amplifier with a payload.

The right branch has high impedance, while the left branch (the drain of the left differential device, equivalent to NBIAS1) has low impedance. The left branch has a low voltage gain (because it is a diode), but a high current gain that depends on the differential gain (Vout-VrefA_Filter).

Therefore, the voltage NBIAS1 can be effectively obtained, and during the voltage drop of Vout, the transient fluctuation of Vout (or Vout-VrefA_Filter) can be closely followed. Therefore, NBIAS1 is well suited as a current source for current mirror N1B, which changes its current in the same way as I1, but with greater gain.

Simulation performance

6 is a graph of simulated performance of a low dropout voltage regulator with and without improved output dropout recovery according to embodiments of the present invention. In this example, the configuration of Figure 3 (with the pulse generator 56) was used for the simulation. All graphs show voltage versus time.

Starting at the top of the graph, curve 70 represents Vout without improved output drop recovery (which would disable the recovery boost unit). The deep and long voltage drop can be clearly seen. Curve 74 represents Vout with improved output drop recovery (which will restore the boost unit active). It can be seen that the voltage drop is significantly shorter and shallower.

Moving down, curves 78 and 82 show the voltage at VG with and without improved output drop recovery (the midpoint between the two stages of the low drop voltage regulator), respectively. Without the improved output drop recovery (curve 78), the transition at VG becomes very slow (narrow bandwidth feedback). Including improved output drop recovery (curve 82), the transition at VG is significantly faster (high bandwidth feedback) due to the improved current drawn at VG driven by the recovery boost unit.

Further down, curves 86 and 90 represent the two inputs to the surge detector 48 . Curve 86 represents Vout and curve 90 represents VrefA_Filter. Surge detector 48 outputs pulses between time curve 86 below curve 90 until time curve 86 returns above curve 90 .

Finally, at the bottom of the figure, curve 94 represents the pulses output by the surge detector 48 . Curve 98 represents the output of the recovery boost unit, ie the pulse applied to the midpoint VG after the pulse has been terminated by using the pulse generator 56 and transistor NCUT.

7 is a block diagram of an integrated circuit 100 including a low dropout voltage regulator with improved output dropout recovery according to an embodiment of the present invention. In this example, the low dropout voltage regulator 24 is used to provide the regulated voltage Vout that powers the circuitry 104 . As described herein, the recovery boost unit 36 is used to improve the recovery of the low dropout voltage regulator 24 from a drop in Vout. It is worth noting that the recovery boost unit 36 does not in any way affect the performance, stability or operating point of the low dropout voltage regulator 24, and will not be a low dropout voltage The regulator adds any capacitive load.

The circuit configurations shown in Figs. 1 to 5 and Fig. 7 are example configurations selected for conceptual clarity. In alternative embodiments, any other suitable configuration may be used. For example, the disclosed techniques can be used with other types of voltage regulators, not necessarily only two-stage low dropout voltage regulators. The recovery boost unit configurations depicted in Figures 2 to 4 are also described as examples only. In alternate embodiments, any other suitable recovery boost unit configuration may be used.

In various embodiments, the circuits shown in FIGS. 1-5 and 7 may be configured in any suitable manner, such as using individual components or application specific integrated circuits (ASICs). The values given above, such as the Vout value, the range of Vcc, and the input value of the recovery boost unit, are chosen only as examples. The disclosed techniques can be used with any other suitable values.

20: Circuits

24: Low drop voltage regulator

26: load

28: Operational Transconductance Amplifier

32: P-type metal oxide semiconductor field effect transistor

36: Restore boost unit

FB: Feedback voltage

Vref: reference voltage

Vcc: power supply voltage

Vout: output voltage

R1A, R1B, R2: Resistors

Claims (7)

A recovery boost circuit for applying a pulse to a voltage regulator outside of it to help the voltage regulator recover from a voltage drop, comprising: a plurality of hardware circuits electrically connected to each other, configured to: detect the voltage drop occurring in an output voltage of the voltage regulator; generate a first current from the output voltage of the voltage regulator; generate a second current from a power supply of the voltage regulator voltage; generating the pulse with energy related to the first current and the second current; and applying the pulse to the voltage regulator. The recovery boost circuit of claim 1, wherein the voltage regulator includes an output stage having a resistive ladder, and wherein the recovery boost circuit is configured to compare a first step obtained from branches of the resistive ladder A voltage and a second voltage are used to detect the voltage drop, and the hardware circuits of the recovery boost circuit include: a low-pass filter configured to filter the first voltage; and a comparator configured to The voltage drop is detected by comparing the filtered first voltage and the second voltage. The recovery boost circuit of claim 1, wherein the energy of the pulse depends on the sum of the first current and the second current. The recovery boost circuit of claim 1, wherein the hardware circuits of the recovery boost circuit comprise: a cutoff circuit configured to cut off the pulse after a duration dependent on the first current. The recovery boost circuit of claim 1, wherein the hardware circuits of the recovery boost circuit comprise: a native field effect transistor configured to compensate for differences in a supply voltage caused by the voltage regulator changes in the pulse. The recovery boost circuit of claim 1, wherein the hardware circuits of the recovery boost circuit comprise: a series capacitor configured to charge with the pulse and then discharge to apply the pulse to the voltage regulator. The recovery booster circuit of claim 1, wherein the hardware circuits of the recovery booster circuit comprise: a native field effect transistor whose drain is connected to the voltage regulator for applying the pulse.

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