TWI772950B - Meta-structure for semiconductor substrate and method for manufacturing thereof - Google Patents

Abstract

The invention related to a meta-structure for a semiconductor substrate and a method for manufacturing thereof. The substrate meta-structure comprises a substrate with a plurality of first micro structures and second micro structures formed on there. The substrate with the first micro structures and second micro structures is formed from a base material by the etched process. The epitaxy layer on the substrate will be flat by the area difference and symmetry arrangement of the first micro structures and second micro structures.

Description

Semiconductor substrate metastructure and manufacturing method thereof

The present invention relates to a semiconductor structure and a manufacturing method thereof, in particular to a semiconductor substrate metastructure and a manufacturing method thereof.

Light-emitting diodes (LEDs) have gradually replaced traditional light sources such as light bulbs and fluorescent tubes due to their small size, long service life, and fast response. However, when used in the field of lighting, compared with fluorescent tubes, LEDs still have room for improvement in luminous efficiency. Therefore, various manufacturers are committed to improving the luminous efficiency in order to provide people with better light-emitting components. .

In general, commercially available white LEDs use blue LED chips as the excitation source, while blue LED chips mostly use gallium nitride series (such as GaN, GaInN, etc.) as the main luminescent material, and gallium nitride is deposited on the On a sapphire substrate with the same crystal structure (both gallium nitride and sapphire substrate have a hexagonal crystal structure), blue LED chips are formed. In order to effectively improve the luminous efficiency of LEDs, in the prior art, patterning is performed on a sapphire substrate, and regular patterns are used to increase the internal quantum efficiency (Internal Quantum Efficiency) and improve the extraction efficiency (Extraction Efficiency) , effectively increase the brightness of the LED.

Generally speaking, regarding the epitaxial stress, for the epitaxial structure of the light-emitting diode, a super-lattice layer is provided between the N-type semiconductor layer and the light-emitting layer. The lattice layer is used to reduce the residual stress caused by lattice mismatch, which can make the interface of the epitaxial structure The density of dislocation defects is reduced. Since the superlattice layer is composed of two layers of semiconductor materials stacked alternately in pairs. The more commonly used materials are, for example, aluminum gallium nitride/gallium nitride (AlGaN/GaN) or indium gallium nitride/indium gallium nitride (Inx1Ga1-x1N/Inx2Ga1-x2N) with different indium metal ratios. composition. Although the superlattice layer can reduce the stress accumulation to improve the epitaxial quality.

However, the defect problem occurred in the epitaxial process is not only between the N-type semiconductor layer and the light-emitting layer, but starts from the process of forming the buffer layer on the substrate, that is, it is necessary to pay attention to the misalignment defects, which are usually easy to grow. Threading dislocation densities (TDDs), such as flute, helical, or mixed dislocations.

The current technical means for the sapphire substrate is to provide another layer of semiconductor layer on the sapphire substrate to form a layer of metastructure, but in order to form this layer of metastructure, an additional tempering process is required to cure it on the sapphire substrate, resulting in In addition, the residual thermal stress of the sapphire substrate, even if the defect problem caused by epitaxial deposition is solved, the thermal stress problem is also derived. Therefore, it is necessary to lengthen the process time, or supplemented by other technical means to eliminate the thermal stress. This makes the production process of the substrate very complicated.

Based on the above-mentioned problems, the present invention provides a semiconductor structure and a method for manufacturing a substrate thereof, wherein etching is performed according to different etching patterns, so that metastructures with different unit areas are formed on the substrate, and the metastructures with different unit areas are symmetrically arranged, In this way, not only the stress problem can be eliminated, but also the epitaxial layer on the substrate can be made flat.

The main purpose of the present invention is to provide a semiconductor substrate structure and a manufacturing method thereof, which can form metastructures of different unit areas on the substrate by referring to different etching patterns, so as to reduce the misalignment.

The invention discloses a manufacturing method of a semiconductor substrate structure, which firstly provides a base material; then, a photoresist layer is formed on the base material, and then a plurality of first etching patterns and a plurality of second etching patterns are defined on the photoresist layer. on the resist layer, wherein the second etching patterns are located around the first etching patterns and are symmetrical, and the unit area of the first etching patterns is different from the unit area of the second etching patterns; Then, an etching process is performed according to the arrangement of the photoresist layer, the first mask layer and the first etching patterns and the second etching patterns to remove the photoresist layer by dry etching and dry etching or The first mask layer is etched by wet etching to form a substrate, and a plurality of first metastructures are formed on a surface of the substrate in a first epitaxial region, and at the same time, a surface of the substrate is formed on a The second epitaxial region forms a plurality of second metastructures, the unit areas of the first metastructures are larger than the unit areas of the second metastructures, the first metastructures and the first metastructures The second metastructure forms a graded structure corresponding to the area change of the first etching patterns and the second etching patterns. Therefore, when the epitaxial layer is formed on the substrate of the present invention, the epitaxial layer will push out epitaxial defects along the arrangement of the first metastructures and the second metastructures.

The present invention provides an embodiment, which is in the step of performing the etching process according to the photoresist layer and the first mask layer, firstly according to the photoresist layer and the first etching patterns and the second etching patterns The etching pattern is etched, so that the first mask layer forms a plurality of first microstructures and the second microstructures corresponding to the surface of the substrate; then, according to the first microstructures and the first microstructures Two microstructures are etched to form the substrate and to form the first metastructures and the second metastructures on the surface of the substrate according to the first etching patterns and the second etching patterns .

The present invention provides an embodiment of further forming a second mask layer on the photoresist before performing the etching according to the photoresist layer and the first etching patterns and the second etching patterns. layer; and then form a plurality of third patterns and a plurality of fourth patterns corresponding to the second mask layer on the second mask layer according to the first etching patterns and the second etching patterns.

An embodiment of the present invention is that the dry etching uses plasma to etch the first microstructures, the second microstructures and the surface of the substrate.

The present invention provides an embodiment of further performing forming a first epitaxial portion of a gallium nitride epitaxial layer on the first epitaxial region and forming a second epitaxial portion of the gallium nitride epitaxial layer The portion is located on the second epitaxial region, and the height of the first epitaxial portion is different or the same as the height of the second epitaxial portion.

The present invention further discloses a semiconductor substrate structure, which includes a substrate, a surface of which has a first epitaxial region and a second epitaxial region, and the two second epitaxial regions border around the first epitaxial region and symmetrical, the first epitaxial region forms a plurality of first metastructures, the second epitaxial region forms a plurality of second metastructures, and the unit areas of the first metastructures are the same or different from those of the first metastructures The unit area of the second metastructures, the first metastructures and the second metastructures form a gradient structure. Therefore, when the epitaxial layer is formed on the substrate of the present invention, the epitaxial layer will push out epitaxial defects along the arrangement of the first metastructures and the second metastructures.

The present invention provides another embodiment, wherein the height difference between the first metastructures and the second metastructures is 0.05 to 10 microns.

The present invention provides another embodiment, which is that a gallium nitride epitaxial layer is further provided on the substrate, which is formed on the substrate, the first metastructures and the second metastructures, the The gallium nitride epitaxial layer has a first epitaxial portion and a second epitaxial portion, the first epitaxial portion is higher than the second epitaxial portion, and an upper surface of the first epitaxial portion is a flat surface , the tops of the second metastructures penetrate an upper surface of the second epitaxial portion.

10: Substrate

10S: Top surface

102: The first metastructure

104: Second metastructure

10A: Substrate

12: The first mask layer

122: First Microstructure

124: Second Microstructure

14: photoresist layer

142: First etching pattern

142A: First etch pillar

144: Second etching pattern

144A: Second etch pillar

16: Second mask layer

162: Third etching pattern

162A: Third etched pillar

164: Fourth etching pattern

164A: Fourth etched pillar

20: GaN epitaxial layer

202: The first epitaxy department

204: The second epitaxy department

30: Substrate

30A: Substrate

302: The first metastructure

304: Second metastructure

40: GaN epitaxial layer

402: The first epitaxy department

404: Second Epitaxy Department

D1: first interval

A1: The first unit area

A2: The second unit area

A3: The third unit area

D2: Second interval

D3: Third interval

E1: The first epitaxial region

E2: The second epitaxial region

S10-S60: Steps

S52: Step

S54: Step

S110-S155: Steps

S210-S253: Steps

S310-S350: Steps

Figure 1 A: It is a flow chart of manufacturing a substrate according to an embodiment of the present invention.

Figure 1 B: It is a flow chart of an etching process according to an embodiment of the present invention.

Second Figure A to Second Figure F: These are schematic diagrams of part of the flow of an embodiment of the present invention.

Figure 3: It is a flow chart of forming a semiconductor structure according to an embodiment of the present invention.

Figure 4: It is a schematic diagram of the formation of a semiconductor structure according to an embodiment of the present invention.

Figure 5: It is a schematic diagram of the formation of a semiconductor structure according to an embodiment of the present invention.

Sixth Figure A: It is a flow chart of manufacturing a substrate according to another embodiment of the present invention.

Sixth Figure B: It is a flow chart of an etching process according to another embodiment of the present invention.

Fig. 7A to Fig. 7I: they are partial flow diagrams of another embodiment of the present invention.

Eighth Figure A to Eighth Figure B: These are schematic diagrams of the etching pattern of the present invention.

Figure 9A: It is a flow chart of manufacturing a substrate according to another embodiment of the present invention.

Figure 9 B: It is a flow chart of an etching process according to another embodiment of the present invention.

Figures 10A to 10G: they are partial flow diagrams of another embodiment of the present invention.

Figure 11: It is a flow chart of manufacturing a substrate according to another embodiment of the present invention.

The twelfth A to the twelfth D: they are partial flow diagrams of another embodiment of the present invention.

Figures 13A to 13B: These are the top views 1 and 2 of the substrate of the present invention.

In order to make your examiners have a further understanding and understanding of the features of the present invention and the effects achieved, I would like to add examples and explanations, and the explanations are as follows:

Considering that the defects of the semiconductor structure appear in the main epitaxial region, the present invention proposes a semiconductor substrate structure and a manufacturing method thereof to solve the problem of defects in the main epitaxial region caused by the conventional epitaxial technology.

Hereinafter, the characteristics and matching structures of a semiconductor substrate structure disclosed by the present invention will be further described. First, please refer to FIG. 1 A, which is a flowchart of manufacturing a substrate according to an embodiment of the present invention. As shown in the figure, the steps of the manufacturing method of the semiconductor substrate structure of the present invention include: step S10: providing a substrate; step S20: forming a first mask layer on the substrate; step S30: forming a photoresist layer on the first mask on the mask layer; step S40: defining the first etching pattern and the second etching pattern on the photoresist layer; and step S50: performing according to the arrangement of the photoresist layer and the first mask layer and the first etching pattern and the second etching pattern In the etching process, the photoresist layer and the first mask layer are etched to form a substrate.

In step S10, as shown in Figure 2 A, a substrate 10 to be used as a substrate 10A is provided, such as a sapphire substrate, a silicon substrate, and silicon carbide; in step S20, as shown in Figure 2 B , forming a first mask layer 12 on the substrate 10, such as silicon oxide, titanium oxide; in step S30, as shown in the second figure C, generally a resin material is used as a photoresist material to form a The photoresist layer 14 is on the first mask layer 12, and can be cured by ultraviolet light, thermal curing, or electron beam curing; in step S40, as shown in the second diagram D, the photoresist layer 14 is defined A first etching pattern 142 and a second etching pattern 144, and the interval formed by the first etching pattern 142 and the second etching pattern 144 decreases from the center to the outside, that is, a first interval D1, a second interval D2 to a third interval D3 continues to decrease.

In step S50, the photoresist layer 14 and the first mask layer 12 are etched away by an etching process to form a substrate 10A, and please refer to the first figure B, which is an etching process of an embodiment of the present invention The flow chart of the flow chart, wherein step S50 further includes the following steps: step S52: dry etching is performed according to the photoresist layer and its first etching pattern and second etching pattern, so that the first mask layer is formed into a first microstructure and a second microstructure structure and corresponds to the surface of the substrate; and Step S54: Etching is performed according to the first microstructure and the second microstructure to form a substrate, and the surface of the substrate forms a first metastructure and a second metastructure according to the first microstructure and the second microstructure.

In step S52, as shown in the second figure E, the photoresist layer 14 and the photoresist layer 14 are etched together according to the first etching pattern 142, the second etching pattern 144 and the photoresist layer 14 defined in the previous step S40. A mask layer 12 , so that the first mask layer 12 forms a plurality of first microstructures 122 and a plurality of second microstructures 124 . In step S54, as shown in FIG. 2 F, by dry etching or wet etching, the substrate 10 is etched according to the first microstructure 122 and the second microstructure 124 formed in step S52. The substrate 10A, and the upper surface 10S of the substrate 10A respectively form a first metastructure 102 and a second metastructure 104, because the first etching pattern 142 and the second etching pattern 144 form different unit areas and different interval, and the arrangement of the first microstructure 122 and the second microstructure 124 corresponds to the arrangement and unit area of the first etching pattern 142 and the second etching pattern 144, so the first metastructure 102 and the second The two metastructures 104 correspond to the arrangement of the first microstructures 122 and the second microstructures 124 and exhibit a change in arrangement interval or a change in unit area from the center to the outside. In this embodiment, the arrangement interval from large to small constitutes the first The interval D1, the second interval D2, the third interval D3, and the unit areas of the first metastructures 102 are different from the unit areas of the second metastructures 104, and the first metastructures The dimensions of the structures 102 are different from those of the second metastructures 104 , for example, the height difference between the first metastructures 102 and the second metastructures 104 is 0.05 to 10 μm.

Please refer to FIG. 3 and FIG. 4 together, which are flowcharts and schematic diagrams of forming a semiconductor structure according to an embodiment of the present invention. As shown in the third figure, the steps S10 to S50 in the first figure further include the step S60 of forming an epitaxial layer, so the steps S10 to S50 will not be repeated. After the manufacturing method of the semiconductor substrate structure of the present invention is completed, it further comprises: Step S60 : forming a first epitaxial portion of the gallium nitride epitaxial layer on the first epitaxial region and forming a second epitaxial portion of the gallium nitride epitaxial layer on the second epitaxial region.

In step S60 , as shown in FIG. 4 , a first epitaxial region E1 and a second epitaxial region E2 are defined on the upper surface of the substrate 10A, and the first epitaxial region E1 is the first superstructure 102 The second epitaxial region E2 is the setting region of the second superstructure 104, and a first epitaxial portion 202 of a gallium nitride epitaxial layer 20 is formed in the first epitaxial region E1, A second epitaxial portion 204 of the GaN epitaxial layer 20 is formed in the second epitaxial region E2, wherein the upper surface of the first epitaxial portion 202 is a flat surface, and the top of the second metastructure 104 to pass through the upper surface of the second epitaxial portion 204 .

As shown in FIG. 5 , it discloses a substrate 30 , a first metastructure 302 and a second metastructure 304 of another embodiment of the present invention, and a first metastructure 304 of a gallium nitride epitaxial layer 40 . An epitaxial portion 402 is formed in the first epitaxial region E1, and a second epitaxial portion 404 of the gallium nitride epitaxial layer 40 is formed in the second epitaxial region E2, wherein the upper surface of the first epitaxial portion 402 Being a flat surface, the top of the second metastructure 304 passes through the upper surface of the second epitaxial portion 404 , and the first metastructure 302 and the second metastructure 304 are further tapered.

Please refer to FIG. 6A, which is a flowchart of manufacturing a substrate according to an embodiment of the present invention. As shown in the figure, the steps of the manufacturing method of the semiconductor substrate structure of the present invention include: step S110: providing a substrate; step S120: forming a first mask layer on the substrate; step S130: forming a photoresist layer on the first mask on the mask layer; step S140 : defining the first etching pattern and the second etching pattern on the photoresist layer; and step S150 : etching according to the arrangement of the photoresist layer and the first mask layer and the first etching pattern and the second etching pattern The process is used to remove the photoresist layer and the first mask layer to form a substrate.

Steps S110 to S140 are the same as steps S10 to S40 in the previous embodiment, and therefore will not be repeated, and the corresponding schematic diagrams of some steps shown in Figures 7A to 7D are also omitted.

In step S150, as shown in FIG. 6B, which is a flowchart of an etching process according to an embodiment of the present invention, the step S150 further includes: step S151: forming a second mask layer on the photoresist layer; Step S152: Define the third etching pattern and the fourth etching pattern corresponding to the first etching pattern and the second etching pattern on the second mask layer; Step S153: According to the second mask layer, the photoresist layer and the first etching pattern The etching pattern, the second etching pattern and the corresponding third etching pattern and the fourth etching pattern are dry-etched, so that the first mask layer forms the first microstructure and the second microstructure and the second mask layer forms the corresponding third The microstructure and the fourth microstructure correspond to the surface of the substrate; step S154: remove the third microstructure and the fourth microstructure; and step S155: perform etching according to the first microstructure and the second microstructure to form the substrate and make the The surface of the substrate forms a first metastructure and a second metastructure according to the first microstructure, the second microstructure and the corresponding third microstructure and the fourth microstructure.

In step S151, as shown in FIG. 7E, metal chromium is deposited on the photoresist layer 14 by vapor deposition, such as chemical vapor deposition (CVD), to form a second mask layer 16. Continuing in step S152, as shown in FIG. 7F, corresponding to the first etching pattern 142 and the second etching pattern 144 on the photoresist layer 14, a first etching pattern is formed on the second mask layer 16. Three etching patterns 162 and a fourth etching pattern 164 . After that, in step S153, as shown in FIG. 7 G, dry etching is performed to remove the photoresist layer 14 and the second mask layer 16 on the first mask layer 12. Meanwhile, according to the photoresist The first etching pattern 142 and the second etching pattern 144 on the layer 14 form a microstructure, that is, the photoresist layer After 14 is removed, a plurality of first etching pillars 142A, second etching pillars 144A and even third etching pillars 162A and fourth etching pillars 164A corresponding to the third etching pattern 162 and the fourth etching pattern 164 are formed. In step S154, as shown in FIG. 7 H, the first etching column 142A, the second etching column 144A, the third etching column 162A and the fourth etching column 164A are further processed by dry etching in the etching process. It is removed by etching or wet etching to expose the substrate 30 and correspondingly etch the first microstructure 122 and the second microstructure 124 from the first mask layer 12 . In step S155, as shown in FIG. 7 I, etching is performed according to the first microstructure 122 and the second microstructure 124, thereby generating the first metastructure 102 corresponding to the first epitaxial region E1, and simultaneously generating The second metastructure 104 corresponds to the second epitaxial region E2.

As shown in FIG. 8A, in the above embodiment, the photoresist layer 14 is a positive photoresist, or the second mask layer 16 is provided on the photoresist layer 14 as an example to increase the etching resistance. In addition to this, another embodiment of the present invention may further be the disclosure of removing the second mask layer 16 to turn the photoresist layer 14 into a negative photoresist, that is, in step S152, removing the second mask layer 16, and the photoresist layer 14 is converted into a negative photoresist, as shown in Figure B of the eighth.

Please refer to FIG. 9A, which is a flowchart of manufacturing a substrate according to another embodiment of the present invention. The difference between the sixth A and the ninth A is that the ninth A omits the step of forming the first mask layer 12. Therefore, the manufacturing method of the semiconductor substrate structure of the present invention includes the following steps: Step S210: providing a base material; step S230: forming a photoresist layer on the oxide layer; step S240: defining a first etching pattern and a second etching pattern on the photoresist layer; and step S250: according to the photoresist layer and the first etching pattern and the second etching pattern The arrangement is subjected to an etching process to form a substrate.

Step S210 , step S230 and step S240 are equivalent to the above-mentioned steps S110 , step S130 and step S140 , so they will not be described again, and the corresponding diagrams in the tenth A to the tenth C diagram are not the same. Repeat. In step S250, please further refer to the ninth B and the corresponding tenth D to ten G, the steps are as follows: step S251: forming a second mask layer on the photoresist layer; step S252: according to the first etching The pattern and the second etching pattern define the third etching pattern and the fourth etching pattern on the second mask layer; Step S253 : according to the second mask layer, the photoresist layer and the first etching pattern and the second etching pattern and the corresponding third etching pattern and the fourth etching pattern are dry-etched to form a substrate and form the first meta-structure and the second meta-structure on the surface of the substrate. Since steps S251 to S253 are equivalent to the above-mentioned steps S151 to S155, they will not be repeated here. In addition, in this embodiment, since the second mask layer 16 is formed on the photoresist layer 14 , the last positions of the first etching column 142A and the second etching column 144A of the photoresist layer 14 are The positions of the first microstructures 122 and the second microstructures 124 of the first mask layer 12 are displaced or reversed, thereby forming a negative photoresist.

Please refer to FIG. 11, which is a flow chart of manufacturing a substrate according to another embodiment of the present invention. The difference between the ninth diagrams A to ninth B and the eleventh diagram is that the eleventh diagram simplifies the step S250, that is, the eleventh diagram omits the step of the second mask layer. Corresponding to the twelfth A to the twelfth D, the steps are as follows: step S310: providing a substrate; step S330: forming a photoresist layer on the substrate; step S340: defining the first etching pattern and the first etching pattern Two etching patterns are formed on the photoresist layer; and step S350 : performing etching according to the photoresist layer and its first etching pattern and second etching pattern, so that the surface of the substrate forms a first metastructure according to the first etching pattern and the second etching pattern with the second metastructure.

Step S310 , step S330 and step S340 are equivalent to the above-mentioned step S210 , step S230 and step S240 , and thus will not be described again. In step S350, the photoresist layer 14 is directly etched Therefore, the substrate 10A, the first metastructure 102 and the second metastructure 104 are formed as shown in FIG. 12 C before etching and as shown in FIG. 12 D after etching.

In this way, the present invention provides a better substrate structure for a GaN epitaxial layer, and a graded structure is formed by the first metastructure 102 and the second metastructure 104 on the substrate 10A, such as: The interval is reduced from the center to the outside, that is, the first interval D1 to the third interval D3 decreases or increases gradually, so that the defects generated by the gallium nitride epitaxial layer in the first epitaxial region E1 will gradually outward due to epitaxial stress Pressing to the second epitaxial region E2 to flatten the epitaxial layer of the first epitaxial region E1. The gradient structure may further be that the area or the arrangement interval of the first metastructure 102 and the second metastructure 104 continuously changes outward from the first metastructure 102 to the second metastructure 104 . As shown in FIG. 13A, the substrate 10A is the same as the above-mentioned embodiment, and the arrangement interval from the first metastructure 102 outward to the second metastructure 104 decreases from the first interval D1 to the third interval D3 , In addition, as shown in FIG. 13B, the present invention can also decrease the unit area from a first unit area A1 to a second unit from a first unit area A1 outward from the first metastructure 102 to the second metastructure 104 The area A2 and then decrease to a third unit area A3, in addition to the decreasing arrangement interval or the decreasing area, the arrangement interval may be increased or the area may be increased.

To sum up, the semiconductor substrate structure and the manufacturing method thereof of the present invention provide a symmetrical and gradient structure arrangement of the etching pattern, so that the corresponding first metastructure is formed on the upper surface of the substrate after the etching process. and the second metastructure, and based on the fact that the second metastructure is outside the first epitaxial region, and the first metastructure is in the first epitaxial region, so that the epitaxial layer can be moved outward after the epitaxial is completed. Defects are pushed to the edge, thereby flattening the epitaxial layer in the first epitaxial region and clearly showing the cutting pattern outside the first epitaxial region.

Therefore, the present invention is indeed novel, progressive and available for industrial use, and it should meet the requirements for patent application in my country's patent law.

However, the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of implementation of the present invention. All changes and modifications made in accordance with the shape, structure, features and spirit described in the scope of the patent application of the present invention are equivalent. , shall be included in the scope of the patent application of the present invention.

10S: Top surface

10A: Substrate

102: The first metastructure

104: Second metastructure

D1: first interval

D2: Second interval

D3: Third interval

Claims (13)

A method for manufacturing a semiconductor substrate metastructure, the steps comprising: provide a substrate; forming a photoresist layer on the substrate; Define a plurality of first etching patterns and a plurality of second etching patterns on the photoresist layer, the second etching patterns are located around the first etching patterns and are symmetrical, and the units of the first etching patterns the area is different from the unit area of the second etching patterns; and An etching process is performed according to the photoresist layer and the arrangement of the first etching patterns and the second etching patterns to remove the photoresist layer and form a substrate through the etching process, and make a surface of the substrate A first epitaxial region on the surface forms a plurality of first metastructures, while a second epitaxial region on the surface forms a plurality of second metastructures, the first etching patterns and the first The arrangement of the two etching patterns makes the first metastructures and the second metastructures correspond to form a graded structure, and the unit area difference between the first etching patterns and the second etching patterns Let the unit areas of the first metastructures be correspondingly different from the unit areas of the second metastructures. The method for manufacturing a semiconductor substrate metastructure as claimed in claim 1, before the step of forming a photoresist layer on the substrate, further comprising: A first mask layer is formed on the substrate. The method for manufacturing a semiconductor substrate metastructure as claimed in claim 2, wherein in the step of performing the etching process according to the photoresist layer and the arrangement of the first etching patterns and the second etching patterns, the method comprises: : Dry etching is performed according to the photoresist layer and the first etching patterns and the second etching patterns, so that the first mask layer forms a plurality of first microstructures and the second microstructures corresponding to each other on the surface; and Dry etching or wet etching is performed according to the first microstructures and the second microstructures to form the substrate and to form the surface according to the first microstructures and the second microstructures some first metastructures and some second metastructures. The method for manufacturing a semiconductor substrate metastructure as claimed in claim 1, further comprising, before the steps of performing the etching process according to the photoresist layer and the arrangement of the first etching patterns and the second etching patterns, further comprising: : A second mask layer is formed on the photoresist layer. The method for manufacturing a semiconductor substrate metastructure as claimed in claim 4, further comprising, before the steps of performing the etching process according to the photoresist layer and the arrangement of the first etching patterns and the second etching patterns, further comprising: : A plurality of third etching patterns and a plurality of fourth etching patterns corresponding to the first etching patterns and the second etching patterns are defined on the second mask layer. The method for manufacturing a semiconductor substrate metastructure as claimed in claim 5, wherein in the step of dry etching the photoresist layer and the first etching patterns and the second etching patterns, further according to the Dry etching is performed on the third etching patterns and the fourth etching patterns, so that the first microstructures are respectively provided with a third microstructure, and the second microstructures are respectively provided with a fourth microstructure. The method for manufacturing a semiconductor substrate metastructure as claimed in claim 3, wherein the dry etching is to use plasma to etch the first microstructures, the second microstructures and the surface. The method for manufacturing a semiconductor substrate metastructure as claimed in claim 1, further comprising: forming a first epitaxial portion of a gallium nitride epitaxial layer on the first epitaxial region and forming a second epitaxial portion of the gallium nitride epitaxial layer on the second epitaxial region, the first epitaxial region The height of an epitaxial portion is different from or the same as the height of the second epitaxial portion. The method for manufacturing a semiconductor substrate metastructure as claimed in claim 1, wherein the graded structure gradually changes the area or the arrangement interval from the first metastructures to the second metastructures. A semiconductor substrate metastructure, comprising: A substrate, a surface of which has a first epitaxial region and a second epitaxial region, the two second epitaxial regions border the periphery of the first epitaxial region and are symmetrical, and the first epitaxial region forms a plurality of a first metastructure, the second epitaxial region forms a plurality of second metastructures, the unit areas of the first metastructures are larger than the unit areas of the second metastructures, the first metastructures The metastructure and the second metastructures form a graded structure. The semiconductor substrate metastructure of claim 10, wherein the difference between the unit area of the first metastructures and the height of the second metastructures is 0.05 to 10 microns. The semiconductor substrate metastructure of claim 10, wherein a gallium nitride epitaxial layer is further provided on the substrate, which is formed on the substrate and the first metastructures and the second metastructures Above, the gallium nitride epitaxial layer has a first epitaxial portion and a second epitaxial portion, the height of the first epitaxial portion is different or the same as the height of the second epitaxial portion, the first epitaxial portion An upper surface of the crystal portion is a flat surface, and tops of the second superstructures penetrate an upper surface of the second epitaxial portion. The semiconductor substrate metastructure of claim 10, wherein the graded structure gradually changes the area or the arrangement interval from the first metastructures to the second metastructures.

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