CN116825903A - Semiconductor substrate element structure and manufacturing method thereof - Google Patents

Abstract

The invention relates to a semiconductor substrate element structure and a manufacturing method thereof, wherein the substrate element structure comprises a substrate, a plurality of first element structures and a plurality of second element structures, the plurality of first element structures and the plurality of second element structures are formed by etching a substrate to form the substrate with the plurality of first element structures and the plurality of second element structures, and the epitaxial layer on the substrate is flattened through unit area difference and symmetrical arrangement of the plurality of first element structures and the plurality of second element structures.

Description

Semiconductor substrate element structure and manufacturing method thereof

Technical Field

The present invention relates to a semiconductor structure and a method for fabricating the same, and more particularly, to a semiconductor substrate structure and a method for fabricating the same.

Background

Because the Light Emitting Diode (LED) has the advantages of small volume, long service life, quick response and the like, the traditional light sources such as the prior bulbs, fluorescent tubes and the like are gradually replaced. However, when applied to the field of illumination, LEDs still have room for improvement in light-emitting efficiency as compared to fluorescent tubes, and thus, manufacturers have not been striving for improvement in light-emitting efficiency in order to provide better light-emitting components.

Generally, commercially available white LEDs use blue LED dies as excitation sources, and the blue LED dies mostly use gallium nitride series (such as GaN, gaInN, etc.) as main luminescent materials, and gallium nitride is deposited on a sapphire substrate with the same crystal structure (both gallium nitride and sapphire substrate are hexagonal crystal structures) to form the blue LED dies. In order to effectively improve the light emitting efficiency of the LED, in the prior art, patterning is further performed on the sapphire substrate, and the internal quantum efficiency (Internal Quantum Efficiency) and the light extraction efficiency (Extraction Efficiency) are increased by the regularly arranged patterns, so that the brightness of the LED is effectively increased.

Generally, regarding an epitaxial stress spacer, a Super-lattice layer (Super-lattice layer) is disposed between an N-type semiconductor layer and a light emitting layer for an epitaxial structure of a light emitting diode, and the Super-lattice layer is used to reduce residual stress generated by lattice mismatch, so that the density of interface dislocation defects of the epitaxial structure can be reduced. Since the superlattice layer is composed of pairs of alternating stacked layers of two semiconductor materials. More commonly used materials are, for example, aluminum gallium nitride/gallium nitride (AlGaN/GaN) or indium gallium nitride/indium gallium nitride (Inx 1Ga1-x 1N/Inx 2Ga1-x 2N) with different doped indium metal ratios. Although the superlattice layer may reduce stress accumulation to enhance epitaxial quality.

However, the defect problem occurring in the epitaxial process does not occur only between the N-type semiconductor layer and the light emitting layer, but also starts from the process of forming the buffer layer on the substrate, i.e., the defect needs to be noticed, and typically, the defect tends to grow into a through dislocation (threading dislocation densities, TDDs), such as a blade dislocation, a spiral dislocation, or a mixed dislocation.

In the prior art, a semiconductor layer is additionally disposed on a sapphire substrate to form a one-layer structure, but in order to form the one-layer structure, an annealing process is additionally required to be used to cure the one-layer structure on the sapphire substrate, so that residual thermal stress of the sapphire substrate is caused, and the thermal stress problem is derived even though the defect problem caused by epitaxy is solved, so that the process time is prolonged, or other technical means are assisted to eliminate the thermal stress. This complicates the substrate manufacturing process.

In view of the above, the present invention provides a semiconductor structure and a method for manufacturing a substrate thereof, which are etched according to different etching patterns to form cell structures with different unit areas on the substrate, and the cell structures with different unit areas are symmetrically arranged, so that the stress problem can be eliminated, and the epitaxial layer on the substrate can be flattened.

Disclosure of Invention

The present invention provides a semiconductor substrate structure and a method for fabricating the same, which can reduce the dislocation by forming the cell structures with different unit areas on the substrate by referring to different etching patterns.

The invention discloses a manufacturing method of a semiconductor substrate structure, which comprises the steps of providing a base material; then, forming a photoresist layer on the substrate, and defining a plurality of first etching patterns and a plurality of second etching patterns on the photoresist layer, wherein the second etching patterns are positioned around the first etching patterns and are symmetrical, and the unit area of the first etching patterns is different from the unit area of the second etching patterns; then, etching is performed according to the arrangement of the photoresist layer, the first shielding layer, the first etching patterns and the second etching patterns, so as to remove the photoresist layer through dry etching, etch the first shielding layer through dry etching or wet etching to form a substrate, form a plurality of first meta structures on a first epitaxial region on one surface of the substrate, and form a plurality of second meta structures on a second epitaxial region on the surface of the substrate, wherein the unit area of the first meta structures is larger than the unit area of the second meta structures, and the first meta structures and the second meta structures are formed gradually in correspondence to the area changes of the first etching patterns and the second etching patterns. Therefore, when the epitaxial layer is formed on the substrate of the present invention, the epitaxial layer pushes out the epitaxial defect along the arrangement of the first meta-structures and the second meta-structures.

The invention provides an embodiment, wherein in the step of etching treatment according to the photoresist layer and the first shielding layer, etching is firstly performed according to the photoresist layer, the first etching patterns and the second etching patterns, so that the first shielding layer forms a plurality of first microstructures and a plurality of second microstructures and corresponds to the surface of the substrate; then, etching is performed according to the first microstructures and the second microstructures to form the substrate, and the surface of the substrate is formed into the first microstructures and the second microstructures according to the first etching patterns and the second etching patterns.

The invention provides an embodiment, which is characterized in that a second shielding layer is further formed on the photoresist layer before the step of etching according to the photoresist layer, the plurality of first etching patterns and the plurality of second etching patterns; and forming a plurality of corresponding third patterns and fourth patterns on the second shielding layer according to the plurality of first etching patterns and the plurality of second etching patterns.

The invention provides an embodiment, wherein the dry etching is to etch the first microstructures, the second microstructures and the surface of the substrate by using plasma.

The present invention provides an embodiment in which a first epitaxial portion forming a gan epitaxial layer is further performed successively on the first epitaxial region and a second epitaxial portion forming the gan epitaxial layer is located on the second epitaxial region, the height of the first epitaxial portion being different from or the same as the height of the second epitaxial portion.

The invention also discloses a semiconductor substrate structure, which comprises a substrate, wherein one surface of the substrate is provided with a first epitaxial region and a second epitaxial region, the second epitaxial region is bordered on the periphery of the first epitaxial region and symmetrical, the first epitaxial region forms a plurality of first meta-structures, the second epitaxial region forms a plurality of second meta-structures, the unit area of the plurality of first meta-structures is the same as or different from the unit area of the plurality of second meta-structures, and the plurality of first meta-structures and the plurality of second meta-structures form a gradual change structure. Therefore, when the epitaxial layer is formed on the substrate of the present invention, the epitaxial layer pushes out the epitaxial defect along the arrangement of the first meta-structures and the second meta-structures.

The present invention provides another embodiment wherein the first plurality of features and the second plurality of features have a height difference of 0.05 to 10 microns.

The present invention provides another embodiment, wherein a gallium nitride epitaxial layer is further disposed on the substrate and is formed on the substrate, the first meta structures and the second meta structures, the gallium nitride epitaxial layer has a first epitaxial portion and a second epitaxial portion, the first epitaxial portion is higher than the second epitaxial portion, an upper surface of the first epitaxial portion is a flat surface, and top ends of the second meta structures penetrate an upper surface of the second epitaxial portion.

Drawings

FIG. 1A is a flow chart of a method for fabricating a substrate according to an embodiment of the invention.

FIG. 1B is a flow chart of an etching process according to one embodiment of the invention.

Fig. 2A to 2F are schematic partial flow diagrams of an embodiment of the present invention.

Fig. 3 is a flow chart of a semiconductor structure formation in accordance with an embodiment of the present invention.

Fig. 4 is a schematic diagram of a semiconductor structure formation according to an embodiment of the invention.

Fig. 5 is a schematic diagram of a semiconductor structure formation according to an embodiment of the invention.

FIG. 6A is a flow chart of a method of fabricating a substrate according to another embodiment of the present invention.

FIG. 6B is a flow chart of an etching process according to another embodiment of the present invention.

Fig. 7A to 7I are schematic partial flow diagrams of another embodiment of the present invention.

Fig. 8A to 8B are schematic views of etching patterns according to the present invention.

FIG. 9A is a flow chart of a method of fabricating a substrate according to another embodiment of the present invention.

Fig. 9B is a flow chart of an etching process according to another embodiment of the invention.

Fig. 10A to 10G: which is a partial flow diagram of another embodiment of the present invention.

Fig. 11 is a flow chart of manufacturing a substrate according to another embodiment of the invention.

Fig. 12A to 12D are schematic partial flow diagrams of another embodiment of the present invention.

Fig. 13A to 13B are a first top view and a second top view of the substrate of the present invention.

Symbol description:

10. substrate material

10S upper surface

102. First meta-structure

104. Second element structure

10A substrate

12. First shielding layer

122. First microstructure

124. Second microstructure

14. Photoresist layer

142. First etching pattern

142A first etched column

144. Second etching pattern

144A second etched column

16. Second shielding layer

162. Third etching pattern

162A third etched column

164. Fourth etching pattern

164A fourth etched column

20. Gallium nitride epitaxial layer

202. First epitaxial portion

204. Second epitaxial part

30. Substrate material

30A substrate

302. First meta-structure

304. Second element structure

40. Gallium nitride epitaxial layer

402. First epitaxial portion

404. Second epitaxial part

D1 First interval

A1 First unit area

A2 Second unit area

A3 Third unit area

D2 Second interval

D3 Third interval

E1 First epitaxial region

E2 Second epitaxial region

S10-S60 step

S52 step

S54 step

S110-S155 step

S210-S253 steps

S310-S350.

Detailed Description

So that those skilled in the art can more fully understand and appreciate the features and advantages of the present invention, a detailed description of the preferred embodiments and their associated description is provided below:

in view of the defect of the semiconductor structure appearing in the main epitaxial region, the present invention provides a semiconductor substrate structure and a method for fabricating the same, so as to solve the problem of the defect appearing in the main epitaxial region caused by the conventional epitaxial technique.

The following further illustrates the characteristics and configuration of the semiconductor substrate structure disclosed in the present invention:

first, please refer to fig. 1A, which is a flowchart illustrating a method for manufacturing a substrate according to an embodiment of the present invention. As shown in the drawings, the steps of the method for manufacturing a semiconductor substrate structure of the present invention include:

step S10, providing a substrate;

step S20, forming a first shielding layer on a substrate;

step S30, forming a photoresist layer on the first shielding layer;

step S40, defining a first etching pattern and a second etching pattern on the photoresist layer; and

step S50, etching treatment is carried out according to the arrangement of the photoresist layer, the first shielding layer, the first etching pattern and the second etching pattern so as to etch the photoresist layer and the first shielding layer to form a substrate.

In step S10, as shown in FIG. 2A, a substrate 10, such as a sapphire substrate, a silicon substrate, or silicon carbide, is provided as a substrate 10A; in step S20, as shown in fig. 2B, a first shielding layer 12 is formed on the substrate 10, for example, silicon oxide, titanium oxide; in step S30, as shown in fig. 2C, a photoresist layer 14 is formed on the first shielding layer 12 by using a resin material as a photoresist material, and can be cured by uv light, heat or electron beam; in step S40, as shown in fig. 2D, a first etching pattern 142 and a second etching pattern 144 are defined on the photoresist layer 14, and the space between the first etching pattern 142 and the second etching pattern 144 is reduced from the center to the outside, i.e. a first space D1, a second space D2 to a third space D3 are continuously reduced.

In step S50, the photoresist layer 14 and the first shielding layer 12 are etched away by an etching process to form a substrate 10A, and please further refer to fig. 1B, which is a flowchart illustrating an etching process according to an embodiment of the present invention, wherein step S50 further includes the steps of:

step S52, dry etching is carried out according to the photoresist layer, the first etching pattern and the second etching pattern, so that the first shielding layer forms a first microstructure and a second microstructure and corresponds to the surface of the substrate; and

in step S54, etching is performed according to the first microstructure and the second microstructure to form a substrate, and the surface of the substrate is formed into a first microstructure and a second microstructure according to the first microstructure and the second microstructure.

In step S52, as shown in fig. 2E, the photoresist layer 14 and the first shielding layer 12 are etched together according to the first etching pattern 142, the second etching pattern 144 and the photoresist layer 14 defined in the previous step S40, so that the first shielding layer 12 is formed with a plurality of first microstructures 122 and a plurality of second microstructures 124. In step S54, as shown in fig. 2F, the substrate 10 is etched into the substrate 10A according to the first microstructure 122 and the second microstructure 124 formed in step S52 by dry etching or wet etching, and the upper surface 10S of the substrate 10A correspondingly forms a first meta structure 102 and a second meta structure 104, and since the first etching pattern 142 and the second etching pattern 144 form different unit areas and different spaces, the arrangement of the first microstructure 122 and the second microstructure 124 corresponds to the arrangement and unit areas of the first etching pattern 142 and the second etching pattern 144, the first meta structure 102 and the second meta structure 104 respectively show an arrangement interval change or a unit area change from the center to the outside according to the arrangement of the first microstructure 122 and the second microstructure 124, and in this embodiment, the arrangement interval is formed from large to small as a first interval D1, a second interval D2, a third interval D3, and the unit areas of the first meta structures 102 are different from the first meta structure 104 to the first meta structure 102 and the binary structure 102 is different from the first meta structure 104 to the binary structure 102, and the binary structure 102 is different from the first meta structure 102 to the binary structure 104 is 0.05.

Please refer to fig. 3 and 4 together, which are a flowchart and a schematic diagram illustrating a semiconductor structure according to an embodiment of the present invention. As shown in fig. 3, the steps S10 to S50 in fig. 1 further include a step S60 of forming an epitaxial layer, and thus the steps S10 to S50 are not repeated. After the manufacturing method of the semiconductor substrate structure of the present invention is completed, the manufacturing method further comprises:

step S60, forming a first epitaxial portion of the gallium nitride epitaxial layer on the first epitaxial region and forming a second epitaxial portion of the gallium nitride epitaxial layer on the second epitaxial region.

In step S60, as shown in the fourth drawing, a first epitaxial region E1 and a second epitaxial region E2 are defined on the upper surface of the substrate 10A, wherein the first epitaxial region E1 is the set region of the first meta structure 102, the second epitaxial region E2 is the set region of the second meta structure 104, a first epitaxial portion 202 of a gan epitaxial layer 20 is formed on the first epitaxial region E1, a second epitaxial portion 204 of the gan epitaxial layer 20 is formed on the second epitaxial region E2, the upper surface of the first epitaxial portion 202 is a flat surface, and the top end of the second meta structure 104 is the upper surface passing through the second epitaxial portion 204.

As shown in fig. 5, another embodiment of the substrate 30, a first meta structure 302 and a second meta structure 304 of the present invention are disclosed, a first epitaxial portion 402 of a gan epitaxial layer 40 is formed in a first epitaxial region E1, a second epitaxial portion 404 of the gan epitaxial layer 40 is formed in a second epitaxial region E2, wherein an upper surface of the first epitaxial portion 402 is a flat surface, a top end of the second meta structure 304 passes through an upper surface of the second epitaxial portion 404, and the first meta structure 302 and the second meta structure 304 further have a tapered shape.

Referring to fig. 6A, a flow chart of a method for manufacturing a substrate according to an embodiment of the invention is shown. As shown in the drawings, the steps of the method for manufacturing a semiconductor substrate structure of the present invention include:

step S110, providing a substrate;

step S120, forming a first shielding layer on a substrate;

step S130, forming a photoresist layer on the first shielding layer;

step S140, defining a first etching pattern and a second etching pattern on the photoresist layer; and

step S150, etching treatment is carried out according to the arrangement of the photoresist layer, the first shielding layer, the first etching pattern and the second etching pattern so as to remove the photoresist layer and the first shielding layer and form a substrate.

The steps S110 to S140 are the same as the steps S10 to S40 in the previous embodiment, and therefore, the description thereof is omitted, and the corresponding partial step schematic diagrams shown in fig. 7A to 7D are omitted.

In step S150, as shown in fig. 6B, a flowchart of an etching process according to an embodiment of the invention is shown, wherein step S150 further includes:

step S151, forming a second shielding layer on the photoresist layer;

step S152, defining a third etching pattern and a fourth etching pattern corresponding to the first etching pattern and the second etching pattern on the second shielding layer;

step 153, dry etching is carried out according to the second shielding layer, the photoresist layer, the first etching pattern and the second etching pattern thereof and the corresponding third etching pattern and fourth etching pattern, so that the first shielding layer forms a first microstructure, a second microstructure and the second shielding layer forms a corresponding third microstructure and fourth microstructure and corresponds to the surface of the substrate;

step S154, removing the third microstructure and the fourth microstructure; and

step S155, etching is performed according to the first microstructure and the second microstructure to form a substrate, and the surface of the substrate forms a first microstructure and a second microstructure according to the first microstructure and the second microstructure and the corresponding third microstructure and fourth microstructure.

In step S151, as shown in fig. 7E, a second shielding layer 16 is formed by depositing metal chromium on the photoresist layer 14 by vapor deposition, such as Chemical Vapor Deposition (CVD), and in step S152, a third etching pattern 162 and a fourth etching pattern 164 are formed on the second shielding layer 16 corresponding to the first etching pattern 142 and the second etching pattern 144 on the photoresist layer 14, as shown in fig. 7F. Then, in step S153, as shown in fig. 7G, the photoresist layer 14 and the second shielding layer 16 on the first shielding layer 12 are removed, and a microstructure is formed according to the first etching pattern 142 and the second etching pattern 144 on the photoresist layer 14, i.e. after the photoresist layer 14 is removed, a plurality of first etching pillars 142A, second etching pillars 144A, and even third etching pillars 162A and fourth etching pillars 164A corresponding to the third etching pattern 162 and the fourth etching pattern 164 are formed. In step S154, as shown in fig. 7H, the first etching pillar 142A, the second etching pillar 144A, the third etching pillar 162A and the fourth etching pillar 164A are further removed by dry etching or wet etching in the etching process to expose the substrate 30 and etch the first shielding layer 12 to form the first microstructure 122 and the second microstructure 124. In step S155, as shown in fig. 7I, etching is performed according to the first microstructure 122 and the second microstructure 124, thereby generating a first meta-structure 102 corresponding to the first epitaxial region E1, and generating a second meta-structure 104 corresponding to the second epitaxial region E2.

As shown in fig. 8A, the above embodiment is that the photoresist layer 14 belongs to a positive photoresist, or the second shielding layer 16 is disposed on the photoresist layer 14 as an example to increase the etching resistance. In addition, another embodiment of the present invention further provides for removing the second shielding layer 16 to convert the photoresist layer 14 into negative photoresist, i.e. in step S152, the second shielding layer 16 is removed to convert the photoresist layer 14 into negative photoresist, as shown in fig. 8B.

Referring to fig. 9A, a flow chart of a method for manufacturing a substrate according to another embodiment of the invention is shown. The difference between fig. 6A and fig. 9A is that fig. 9A omits the step of forming the first shielding layer 12, and thus, the method for manufacturing a semiconductor substrate structure of the present invention includes the steps of:

step S210, providing a substrate;

step S230, forming a photoresist layer on the oxide layer;

step S240, defining a first etching pattern and a second etching pattern on the photoresist layer; and

step S250, etching treatment is carried out according to the photoresist layer and the arrangement of the first etching pattern and the second etching pattern so as to form a substrate.

Step S210, step S230 and step S240 correspond to step S110, step S130 and step S140, and thus are not described in detail, and the corresponding fig. 10A to 10C of the drawings are not described in detail. In step S250, please further refer to fig. 9B and corresponding fig. 10D to fig. 10G, which steps are as follows:

step S251, forming a second shielding layer on the photoresist layer;

step S252, defining a third etching pattern and a fourth etching pattern corresponding to the first etching pattern and the second etching pattern on the second shielding layer;

step 253, performing dry etching according to the second shielding layer, the photoresist layer, the first etching pattern and the second etching pattern thereof, and the corresponding third etching pattern and fourth etching pattern to form a substrate and a first meta structure and a second meta structure on the surface of the substrate. Since steps S251 to S253 correspond to steps S151 to S155, the description thereof will not be repeated. In addition, in the present embodiment, since the second shielding layer 16 is formed on the photoresist layer 14, the positions of the last first etching pillars 142A and the second etching pillars 144A of the photoresist layer 14 are offset from the positions of the first microstructures 122 and the second microstructures 124 of the first shielding layer 12, or are inverted, so that the second shielding layer is formed as a negative photoresist.

Referring to fig. 11, a flow chart of manufacturing a substrate according to another embodiment of the invention is shown. The difference between fig. 9A to 9B and fig. 11 is that fig. 11 simplifies step S250, that is, fig. 11 omits the step of the second shielding layer. The steps corresponding to those shown in fig. 12A to 12D are as follows:

step S310, providing a substrate;

step S330, forming a photoresist layer on the substrate;

step S340, defining a first etching pattern and a second etching pattern on the photoresist layer; and

step 350, etching is performed according to the photoresist layer and the first etching pattern and the second etching pattern, so that the surface of the substrate forms a first meta structure and a second meta structure according to the first etching pattern and the second etching pattern.

Step S310, step S330 and step S340 correspond to step S210, step S230 and step S240, and thus are not described in detail. In step S350, the photoresist layer 14 is directly etched, so that the substrate 10A, the first meta-structure 102 and the second meta-structure 104 are formed as shown in fig. 12C before etching and as shown in fig. 12D after etching.

Thus, in accordance with the present invention, a preferred substrate structure is provided for the gan epitaxial layer, and a graded structure is formed by the first meta structure 102 and the second meta structure 104 on the substrate 10A, for example, the first interval D1 to the third interval D3 are reduced from the center to the outside, or increased gradually, and the defect generated by the gan epitaxial layer in the first epitaxial region E1 is gradually pressed outwards to the second epitaxial region E2 due to the epitaxial stress, so as to planarize the epitaxial layer in the first epitaxial region E1. The graded structure may further be a structure in which the area of the first meta structure 102 and the second meta structure 104 is changed from the first meta structure 102 to the second meta structure 104. As shown in fig. 13A, the arrangement interval from the first meta structure 102 to the second meta structure 104 decreases from the first interval D1 to the third interval D3, and as shown in fig. 13B, the arrangement interval may be increased or the area may be increased for the unit area from the first meta structure 102 to the second meta structure 104 decreases from the first unit area A1 to the second unit area A2 and then decreases to the third unit area A3.

In summary, the semiconductor substrate structure and the method for manufacturing the same according to the present invention provide an arrangement in which the etching pattern is symmetrical and has a graded structure, so that after the substrate is etched, a corresponding first meta structure and a second meta structure are formed on the upper surface of the substrate, and based on the second meta structure being outside the first epitaxial region and the first meta structure being inside the first epitaxial region, the epitaxial layer can push out the defect to the edge after the epitaxy is completed, so that the epitaxial layer in the first epitaxial region is planarized, and the cutting pattern is clearly shown outside the first epitaxial region.

However, the above-mentioned embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention, but all equivalent changes and modifications in shape, construction, characteristics and spirit according to the present invention as defined in the appended claims are intended to be included in the scope of the present invention.

Claims (13)

1. A method for manufacturing a semiconductor substrate element structure comprises the following steps:

providing a substrate;

forming a photoresist layer on the substrate;

defining a plurality of first etching patterns and a plurality of second etching patterns on the photoresist layer, wherein the plurality of second etching patterns are positioned around the plurality of first etching patterns and are symmetrical, and the unit area of the plurality of first etching patterns is different from the unit area of the plurality of second etching patterns; and

and performing an etching process according to the photoresist layer and the arrangement of the first etching patterns and the second etching patterns to remove the photoresist layer, forming a substrate through the etching process, forming a plurality of first meta-structures in a first epitaxial region on a surface of the substrate, forming a plurality of second meta-structures in a second epitaxial region on the surface, wherein the arrangement of the first etching patterns and the second etching patterns enables the first meta-structures and the second meta-structures to form a gradual change structure, and the difference of unit areas of the first etching patterns and the second etching patterns enables the unit area of the first meta-structures to be correspondingly different from the unit area of the second meta-structures.

2. The method of claim 1, further comprising, prior to the step of forming a photoresist layer over the substrate:

a first shielding layer is formed on the substrate.

3. The method according to claim 2, wherein the etching according to the arrangement of the photoresist layer and the first etching patterns and the second etching patterns comprises performing a dry etching according to the photoresist layer and the first etching patterns and the second etching patterns to form a plurality of first microstructures and a plurality of second microstructures on the first shielding layer and corresponding to the surface; and

and performing dry etching or wet etching according to the first microstructures and the second microstructures to form the substrate and enable the surface to form the first microstructures and the second microstructures according to the first microstructures and the second microstructures.

4. The method of claim 1, further comprising, prior to the step of etching according to the photoresist layer and the arrangement of the plurality of first etching patterns and the plurality of second etching patterns:

a second shielding layer is formed on the photoresist layer.

5. The method according to claim 4, further comprising, before the step of etching according to the arrangement of the photoresist layer and the plurality of first etching patterns and the plurality of second etching patterns:

and defining a plurality of third etching patterns and a plurality of fourth etching patterns corresponding to the first etching patterns and the second etching patterns on the second shielding layer.

6. The method of claim 5, wherein the step of dry etching according to the photoresist layer and the first and second etching patterns further comprises dry etching according to the third and fourth etching patterns to form a third microstructure on the first microstructures and a fourth microstructure on the second microstructures.

7. The method of claim 3, wherein the dry etching etches the first microstructures, the second microstructures, and the surface using plasma.

8. The method of manufacturing a semiconductor substrate cell structure of claim 1, further comprising:

a first epitaxial portion of a gallium nitride epitaxial layer is formed on the first epitaxial region, and a second epitaxial portion of the gallium nitride epitaxial layer is formed on the second epitaxial region, wherein the height of the first epitaxial portion is different from or the same as that of the second epitaxial portion.

9. The method of claim 1, wherein the graded structures are formed by gradually changing areas or arrangement intervals from the first plurality of structures to the second plurality of structures.

10. A semiconductor substrate cell structure, comprising:

the substrate comprises a first epitaxial region and a second epitaxial region on one surface of the substrate, wherein the second epitaxial region is adjacent to the periphery of the first epitaxial region and symmetrical, the first epitaxial region forms a plurality of first meta-structures, the second epitaxial region forms a plurality of second meta-structures, the unit area of the plurality of first meta-structures is larger than the unit area of the plurality of second meta-structures, and the plurality of first meta-structures and the plurality of second meta-structures form a gradual change structure.

11. The semiconductor substrate cell structure of claim 10, wherein the difference in height between the unit area of the plurality of first cell structures and the plurality of second cell structures is between 0.05 microns and 10 microns.

12. The semiconductor substrate of claim 10, further comprising a gan epitaxial layer formed on the substrate and the first and second meta structures, the gan epitaxial layer having a first and second epitaxial portions, the first epitaxial portion having a height different from or equal to a height of the second epitaxial portion, an upper surface of the first epitaxial portion having a planar surface, and a top of the second meta structure penetrating an upper surface of the second epitaxial portion.

13. The semiconductor substrate cell structure of claim 10, wherein the graded structure is a gradual change in area or arrangement spacing from the plurality of first microstructures to the plurality of second microstructures.