TWI771774B - Bias voltage compensation circuit, OLED display device and information processing device - Google Patents

Abstract

The present invention mainly discloses a bias voltage compensation circuit, which is applied in an OLED display, and is used for adjusting the RC path impedance existing between the M×N sub-pixel units of the OLED display panel and the bias voltage providing unit. The at least one bias voltage (ELV _DD /ELV _SS ) performs a voltage compensation process, so that (M/K)×(N/L) of the at least one bias voltage having completed the voltage compensation process is transferred in partitions to K ×L (M/K)×(N/L) display areas of the sub-pixel units, thereby eliminating the bias voltage and transmission to the display area farthest from the bias voltage providing unit The voltage difference between the bias voltage and the bias voltage of the display area closest to the bias voltage supply unit enables all display areas to display uniform luminous brightness.

Description

Bias voltage compensation circuit, OLED display device and information processing device

The present invention relates to the technical field of OLED displays, and more particularly, to a voltage compensation circuit for compensating the bias voltage ELV _DD /ELV _SS according to the RC path impedance of the transmission line of the OLED panel.

It is known that Organic Light-Emitting Diode (OLED) has the advantages of self-luminescence, high brightness, high contrast, wide viewing angle, power consumption, high reaction rate, etc., so it has been widely used in self-luminescence. The production of display panels includes active OLED (ie, AMOLED) display panels and passive OLED (ie, PMOLED) display panels.

FIG. 1 shows a block diagram of a conventional OLED display. At present, the OLED display 1a has been widely used in smart phones, tablet PCs and smart watches. As shown in FIG. 1, the OLED display 1a mainly includes: an OLED display panel 11a, a gate (column) driving circuit 12a, a source (row) driving circuit 13a, a timing controller 14a, and a bias voltage Unit 15a is provided. The gate driver circuit 12a and the source driver circuit 13a are usually integrated into a single display driver IC (DDIC). Moreover, the OLED display panel 11a includes M×N sub-pixel units 111a, and each sub-pixel unit 111a includes a pixel circuit and an OLED sub-pixel. When the OLED display 1a is in normal operation, the bias voltage supply unit 15a transmits a first bias voltage ELV _DD and a second bias voltage ELV _SS to each sub-pixel unit 111a, and each pixel circuit according to A scan signal Scan and a brightness control signal EM transmitted from the gate driving circuit 12a and a data signal V _DATA transmitted from the source driving circuit 13a drive the selected OLED sub-pixels to emit light.

FIG. 2 shows a connection structure diagram of a conventional display driver chip and an OLED display panel. It is worth noting that the display screen of the current smart phone has been developed towards a full-screen design, so that the display driver chip 16a including the gate driver circuit 12a and the source driver circuit 13a must be integrated with the OLED display panel 11a by COF technology. COF is Chip On Film, which is used to integrate a display driving chip 16a and a flexible substrate 17a into a COF circuit board. As shown in FIG. 2 and FIG. 1 , based on the partition driving technology, one OLED display panel 11a is connected to a plurality of COF circuit boards at the same time, so that the timing controller 14a (known as Tcon in the industry) and the bias voltage are mounted. A main substrate 18a of the unit 15a is connected to a plurality of the flexible substrates 17, and then the main substrate 18a is coupled to an application processor 19a through an electrical connection interface.

As shown in FIG. 2 , for the M×N sub-pixel units 111 a included in the OLED display panel 11 a , the m sub-pixel units 111 a arranged along the first row include the 11th, 12th, . . . , and th 1m sub-pixel units 111a, and m sub-pixel units 111a arranged along the nth row include n1th, n2th, . . . , and nth subpixel units 111a. It can be known that, for the first row, the 11th sub-pixel unit 111a and the bias voltage providing unit 15a have the shortest signal transmission distance, while the 1m-th sub-pixel unit 111a has the shortest signal transmission distance. It has the longest signal transmission distance from the bias voltage supply unit 15a. Practical experience points out that the impedance of the RC path increases as the signal transmission distance increases, resulting in a bias voltage difference between any two of the m sub-pixel units 111a along the same row, and the bias voltage The voltage difference will increase with the increase of the RC path impedance, thereby causing the problem of uneven luminous brightness of the OLED display panel 11a.

It can be seen from the above description that there is an urgent need in the art for a bias voltage compensation circuit applied to an OLED display.

The main purpose of the present invention is to provide a bias voltage compensation circuit, which is applied in an OLED display, and is used in accordance with the RC path existing between the M×N sub-pixel units of the OLED display panel and the bias voltage providing unit impedance, perform a voltage compensation process on at least one bias voltage (ELV _DD /ELV _SS ), so that (M/K)×(N/L) at least one bias voltage (ELV _DD / ELV _SS ) is transmitted in partitions to (M/K)×(N/L) display areas each including K×L of the sub-pixel units, thereby eliminating the transmission to the farthest distance from the bias voltage supply unit. The voltage difference between the bias voltage of the far display area and the bias voltage transmitted to the display area closest to the bias voltage supply unit enables all display areas to display uniform luminance.

In order to achieve the above object, the present invention proposes an embodiment of the bias voltage compensation circuit, which is applied in an OLED display including at least one display driver chip, a bias voltage providing unit and an OLED display panel; wherein, The OLED display panel includes M×N sub-pixel units, and there is a signal transmission distance between the M sub-pixel units arranged along the same row and the bias voltage providing unit, which is positive and positive with the signal transmission distance. A related RC path impedance; the bias voltage compensation circuit is coupled between the bias voltage supply unit and the OLED display panel, and includes:

N/L voltage compensation units coupled to at least one reference bias voltage transmitted from the bias voltage providing unit, for performing a voltage compensation process on at least one of the reference bias voltages according to the RC path impedance, Thereby, (M/K)×(N/L) at least one bias voltage partitions are generated and transmitted to (M/K)×(N/L) display areas each including K×L sub-pixel units ;

Among them, M, N, K, L are all positive integers.

In one embodiment, each of the voltage adjustment units includes:

M/K first voltage compensation processing units, wherein each of the first voltage compensation processing units includes a first operational amplifier, a first operational amplifier coupled between a negative input terminal and an output terminal of the first operational amplifier a first resistor, and a second resistor coupled between the output end of the first operational amplifier and the display area; and

M/K second voltage compensation processing units, wherein each of the second voltage compensation processing units includes a second operational amplifier, a second operational amplifier coupled between a negative input terminal and an output terminal of the second operational amplifier A third resistor, a fourth resistor coupled between the output terminal of the second operational amplifier and the display area, and a first resistor coupled to the negative input terminal of the second operational amplifier and the third resistor at the same time five resistors, and a sixth resistor coupled to a positive input end of the second operational amplifier;

The bias voltage providing unit transmits a first reference bias voltage to a positive input terminal of the first operational amplifier, and the bias voltage providing unit transmits a second reference bias through the fifth resistor voltage to the negative input terminal of the second operational amplifier.

In a possible embodiment, the output terminal of the first operational amplifier, the first resistor and the negative input terminal of the first operational amplifier form a negative feedback path, so that each of the first voltage compensation processing units can A voltage compensation effect of the first reference bias voltage is determined by the output impedance of the first operational amplifier and/or the resistance value of the first resistor.

In another possible embodiment, each of the first voltage compensation processing units further includes: an input resistor simultaneously coupled to the negative input terminal of the first operational amplifier and the first resistor, so that each of the first voltages A voltage compensation effect of the compensation processing unit for the first reference bias voltage is determined by the output impedance of the first operational amplifier, the resistance value of the first resistor, and/or the resistance value of the input resistor.

In one embodiment, the output terminal of the second operational amplifier, the third resistor and the negative input terminal of the second operational amplifier form a negative feedback path, so that each of the second voltage compensation processing units can respond to the A voltage compensation effect of the second reference bias voltage is determined by the output impedance of the second operational amplifier, the resistance value of the third resistor, and/or the resistance value of the fifth resistor.

Moreover, the present invention also provides an information processing device, which has an OLED display including at least one display driver chip, a bias voltage supply unit and an OLED display panel; wherein, the OLED display panel includes M×N sub-pixel units , and there is a signal transmission distance and an RC path impedance positively correlated with the signal transmission distance between the M sub-pixel units arranged in the same row and the bias voltage supply unit; The information processing device includes a bias voltage compensation circuit coupled between the bias voltage supply unit and the OLED display panel, and the bias voltage compensation circuit includes:

N/L voltage compensation units coupled to at least one reference bias voltage transmitted from the bias voltage providing unit, for performing a voltage compensation process on at least one of the reference bias voltages according to the RC path impedance, Thereby, (M/K)×(N/L) at least one bias voltage partitions are generated and transmitted to (M/K)×(N/L) display areas each including K×L sub-pixel units ;

Among them, M, N, K, L are all positive integers.

In one embodiment, each of the voltage adjustment units includes:

M/K first voltage compensation processing units, wherein each of the first voltage compensation processing units includes a first operational amplifier, a first operational amplifier coupled between a negative input terminal and an output terminal of the first operational amplifier a first resistor, and a second resistor coupled between the output end of the first operational amplifier and the display area; and

M/K second voltage compensation processing units, wherein each of the second voltage compensation processing units includes a second operational amplifier, a second operational amplifier coupled between a negative input terminal and an output terminal of the second operational amplifier A third resistor, a fourth resistor coupled between the output terminal of the second operational amplifier and the display area, and a first resistor coupled to the negative input terminal of the second operational amplifier and the third resistor at the same time five resistors, and a sixth resistor coupled to a positive input end of the second operational amplifier;

The bias voltage providing unit transmits a first reference bias voltage to a positive input terminal of the first operational amplifier, and the bias voltage providing unit transmits a second reference bias through the fifth resistor voltage to the negative input terminal of the second operational amplifier.

In a possible embodiment, the output terminal of the first operational amplifier, the first resistor and the negative input terminal of the first operational amplifier form a negative feedback path, so that each of the first voltage compensation processing units can A voltage compensation effect of the first reference bias voltage is determined by the output impedance of the first operational amplifier and/or the resistance value of the first resistor.

In another possible embodiment, each of the first voltage compensation processing units further includes: an input resistor simultaneously coupled to the negative input terminal of the first operational amplifier and the first resistor, so that each of the first voltages A voltage compensation effect of the compensation processing unit for the first reference bias voltage is determined by the output impedance of the first operational amplifier, the resistance value of the first resistor, and/or the resistance value of the input resistor.

In one embodiment, the output terminal of the second operational amplifier, the third resistor and the negative input terminal of the second operational amplifier form a negative feedback path, so that each of the second voltage compensation processing units can respond to the A voltage compensation effect of the second reference bias voltage is determined by the output impedance of the second operational amplifier, the resistance value of the third resistor, and/or the resistance value of the fifth resistor.

In a feasible embodiment, the aforementioned information processing device is selected from the group consisting of smart phones, smart watches, smart bracelets, smart TVs, tablet computers, notebook computers, all-in-one computers, and access control devices An electronic device in a group.

The present invention also provides an OLED display device, which includes at least one display driver chip, a bias voltage providing unit and an OLED display panel, characterized in that, the OLED display device further includes the bias voltage of the present invention as described above. compensation circuit.

In order to enable your examiners to further understand the structure, characteristics, purpose, and advantages of the present invention, drawings and detailed descriptions of preferred embodiments are attached as follows.

FIG. 3 shows a block diagram of an OLED display including a bias voltage compensation circuit of the present invention. As shown in FIG. 1, an OLED display 1 mainly includes: an OLED display panel 11, a gate (column) driving circuit 12, a source (row) driving circuit 13, a timing controller 14, and a bias voltage supply Unit 15, and a bias voltage compensation circuit 2 of the present invention. Electronic engineers familiar with the design and fabrication of display driver chips for flat panel displays must know that the gate driver circuit 12 and the source driver circuit 13 can be integrated into a single display driver chip (DDIC) in the prior art. Moreover, the OLED display panel 11 includes M×N sub-pixel units 111 , and each sub-pixel unit 111 includes a pixel circuit and an OLED sub-pixel.

FIG. 4 shows a connection structure diagram of a display driver chip and an OLED display panel of an OLED display device including the bias voltage compensation circuit of the present invention. It is worth noting that the display screen of the current smart phone has been developed towards a full-screen design, so that the display driver chip 16 including the gate driver circuit 12 and the source driver circuit 13 must be integrated with the OLED display panel 11 by COF technology. As shown in FIG. 4 , the display driving chip 16 and a flexible substrate 17 are integrated into a COF circuit board. As shown in FIG. 4 and FIG. 3 , based on the partition driving technology, the OLED display panel 11 is divided into (M/K)×(N/L) display regions 11DR, so that each display region 11DR includes K×L all display regions 11DR. Describe the sub-pixel unit 111, wherein M, N, K, and L are all positive integers. In the case of using the partitioned display driving technology, one OLED display panel 11 is connected to a plurality of COF circuit boards at the same time, and a main substrate 18 carrying the timing controller 14 and the bias voltage supply unit 15 is connected to a plurality of Then, the main substrate 18 is coupled to an application processor 19 through an electrical connection interface.

As shown in FIG. 3, in the OLED display panel 11, the m sub-pixel units 111 arranged along the first row include the 11th, 12th, . The m sub-pixel units 111a of the n-row arrangement include the n1-th, n2-th, . . . , and n-th sub-pixel units 111 . It can be known that for the first row, the 11th sub-pixel unit 111 and the bias voltage providing unit 15a have the shortest signal transmission distance, while the 1m-th sub-pixel unit 111 has the shortest signal transmission distance. It has the longest signal transmission distance from the bias voltage supply unit 15 . It should be understood that the impedance of the RC path increases as the signal transmission distance increases, resulting in a bias voltage difference between any two of the m sub-pixel units 111 along the same row, and the bias voltage The voltage difference will increase with the increase of the RC path impedance, thereby causing the problem of uneven luminous brightness of the OLED display panel 11 .

Therefore, the bias voltage compensation circuit 2 of the present invention is used for at least one bias compensation according to the RC path impedance existing between the M×N sub-pixel units 111 of the OLED display panel 11 and the bias voltage providing unit 15 . The voltages (ELV _DD / ELV _SS ) perform a voltage compensation process, so that (M/K)×(N/L) bias voltages that have completed the voltage compensation process are transferred to each of the K×L pieces of the (M/K)×(N/L) display regions 11DR of the sub-pixel unit, thereby eliminating the bias voltage transmitted to the display region 11DR farthest from the bias voltage providing unit and the transmission to the distance The bias voltage provides a voltage difference between the bias voltages of the display region 11DR closest to the cell, so that all the display regions 11DR show uniform luminance.

Continue to refer to FIG. 3 and FIG. 4 , and also refer to FIG. 5 , which shows a schematic diagram of the electrical connection between the bias voltage compensation circuit of the present invention and the OLED display panel. As shown in FIG. 3 , FIG. 4 and FIG. 5 , the bias voltage compensation circuit 2 of the present invention is coupled between the bias voltage supply unit 15 and the OLED display panel 11 , and mainly includes: N/L voltage compensations unit 21. According to the design of the present invention, the N/L voltage compensation units 21 are coupled to at least one reference bias voltage (ELV _DDR /ELV _SSR ) transmitted from the bias voltage providing unit 15 to be used according to the RC path impedance to perform a voltage compensation process on at least one of the reference bias voltages, thereby generating (M/K)×(N/L) at least one bias voltage (ELV _DD /ELV _SS ) to transmit to each of the reference bias voltages including K× (M/K)×(N/L) of the display regions 11DR of the L sub-pixel units 111 . In other words, each of the voltage compensation units 21 is coupled to at least one reference bias voltage (ELV _DDR /ELV _SSR ) transmitted from the bias voltage supply unit 15 for adjusting the reference according to the RC path impedance The bias voltage is subjected to a voltage compensation process, and then M/K at least one bias voltage (ELV _DD /ELV _SS ) is generated and transmitted to the M/K display regions 11DR arranged along the same row.

FIG. 6 shows an internal circuit structure diagram of a voltage compensation unit of the bias voltage compensation circuit of the present invention. In one embodiment, each of the voltage compensation units 21 includes M/K first voltage compensation processing units and M/K second voltage compensation processing units. As shown in FIG. 6 , each of the first voltage compensation processing units is composed of a first operational amplifier 211 , a first resistor R1 and a second resistor R2 . The first resistor R1 is coupled between a negative input terminal and an output terminal of the first operational amplifier 211, and the second resistor R2 is coupled between the output terminal of the first operational amplifier 211 and the between the display areas 11DR. On the other hand, each of the second voltage compensation processing units is composed of a second operational amplifier 212, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The third resistor R3 is coupled between a negative input terminal and an output terminal of the second operational amplifier 212, and the fourth resistor R4 is coupled between the output terminal of the second operational amplifier 212 and the display Between regions 11DR, the fifth resistor R5 is simultaneously coupled to the negative input terminal of the second operational amplifier 212 and the third resistor R3 , and the sixth resistor R6 is coupled to a positive input terminal of the second operational amplifier 212 .

According to the design of the present invention, the bias voltage providing unit 15 transmits a first reference bias voltage ELV _DDR to a positive input terminal of the first operational amplifier 211 . As shown in FIG. 6 , the first voltage compensation processing unit composed of the first operational amplifier 211 , the first resistor R1 and the second resistor R2 is a non-inverting buffer, and the first operational amplifier The output end of 211 , the first resistor R1 and the negative input end of the first operational amplifier 211 form a negative feedback path. Therefore, the first resistor R1 is used to compensate the variation of the input voltage (ELV _DDR ) caused by the impedance of the RC path and the input bias current of the first operational amplifier 211 . It can be understood that, a voltage compensation effect of each of the first voltage compensation processing units for the first reference bias voltage ELV _DDR is determined by the resistance value of the first resistor R1 . Of course, when the resistance value of the first resistor R1 is fixed, the voltage compensation effect of the first voltage compensation processing unit for the first reference bias voltage ELV _DDR can also be determined by the output impedance of the first operational amplifier 211 ( Ro) decided.

FIG. 7 shows a circuit diagram of a first voltage compensation processing unit of the voltage compensation unit of FIG. 6 . In a possible embodiment, as shown in FIG. 7 , the first voltage compensation processing unit may further include: an input resistor simultaneously coupled to the negative input terminal of the first operational amplifier 211 and the first resistor R1 Ri. After the input resistor Ri is added, the first voltage compensation processing unit becomes a non-inverting amplifier, so that the voltage compensation effect of each of the first voltage compensation processing units for the first reference bias voltage ELV _DDR is determined by the It is determined by the output impedance of the first operational amplifier 211, the resistance value of the first resistor R1, and/or the resistance value of the input resistor Ri.

On the other hand, the second voltage compensation processing unit composed of the second operational amplifier 212, the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 is an inverting buffer, and The bias voltage providing unit 15 transmits a second reference bias voltage ELV _SSR to the negative input terminal of the second operational amplifier 212 via the fifth resistor R5 . Therefore, as shown in FIG. 6 , the output terminal of the second operational amplifier 212 , the third resistor R3 and the negative input terminal of the second operational amplifier 212 form a negative feedback path, so that each of the second voltage compensation A voltage compensation effect of the processing unit for the second reference bias voltage ELV _SSR is determined by the output impedance of the second operational amplifier 212, the resistance value of the third resistor R3, and/or the resistance value of the fifth resistor R5. Decide.

In this way, the above has completely and clearly described a bias voltage compensation circuit of the present invention; and, through the above, it can be known that the present invention has the following advantages:

(1) The present invention discloses a bias voltage compensation circuit, which is applied in an OLED display device, and is used for the RC path existing between M×N sub-pixel units of the OLED display panel and the bias voltage providing unit. impedance, performing a voltage compensation process on at least one bias voltage (ELV _DD /ELV _SS ), so that (M/K)×(N/L) at least one bias voltage after the voltage compensation process is completed is transmitted to the respective (M/K)×(N/L) display areas including K×L sub-pixel units, thereby eliminating the bias transmitted to the display area farthest from the bias voltage supplying unit The voltage difference between the voltage and the bias voltage transmitted to the display area closest to the bias voltage supply unit, so that all display areas show uniform luminous brightness.

(2) The present invention also provides an OLED display device, which includes at least one display driver chip, a bias voltage providing unit and an OLED display panel, characterized in that, the OLED display device further comprises the aforementioned OLED display device of the present invention. Bias voltage compensation circuit.

(3) The present invention also provides an information processing device, which has an OLED display including at least one display driver chip, a bias voltage supply unit and an OLED display panel, characterized in that, the information processing device further includes the above The bias voltage compensation circuit of the present invention. Moreover, the aforementioned information processing device is selected from the group consisting of smart phones, smart watches, smart bracelets, smart TVs, tablet computers, notebook computers, all-in-one computers, and access control devices. An electronic device.

It must be emphasized that the above-mentioned disclosure in this case is a preferred embodiment, and any partial changes or modifications originating from the technical ideas of this case and easily inferred by those who are familiar with the art are within the scope of the patent of this case. category of rights.

To sum up, regardless of the purpose, means and effect of this case, it shows that it is completely different from the conventional technology, and its first invention is practical, and it does meet the patent requirements of the invention. Society is to pray for the best.

1a: OLED display 11a: OLED display panel 111a: Sub-pixel unit 12a: Gate drive circuit 13a: Source driver circuit 14a: Timing Controller 15a: Bias voltage supply unit 16a: Display driver chip 17a: Flexible substrate 18a: Main substrate 19a: Application Processor 1: OLED display 11: OLED display panel 111: Sub-pixel unit 11DR: Display area 12: Gate drive circuit 13: Source driver circuit 14: Timing Controller 15: Bias voltage supply unit 16: Display driver chip 17: Flexible substrate 18: Main substrate 19: Application Processor 2: Bias voltage compensation circuit 21: Voltage compensation unit 211: first operational amplifier 212: Second op-amp R1: first resistor R2: Second resistor R3: the third resistor R4: Fourth resistor R5: Fifth resistor R6: sixth resistor Ri: input resistance

1 is a block diagram of a conventional OLED display; FIG. 2 is a connection diagram of a conventional display driver chip and an OLED display panel; 3 is a block diagram of an OLED display device including a bias voltage compensation circuit of the present invention; 4 is a schematic diagram of a connection structure of a display driver chip and an OLED display panel of an OLED display device including the bias voltage compensation circuit of the present invention; FIG. 5 is a schematic diagram of the electrical connection between the bias voltage compensation circuit of the present invention and the OLED display panel; 6 is an internal circuit structure diagram of a voltage compensation unit of the bias voltage compensation circuit of the present invention; and FIG. 7 is a circuit diagram of a first voltage compensation processing unit of the voltage compensation unit of FIG. 6 .

11: OLED display panel

111: Sub-pixel unit

11DR: Display area

15: Bias voltage supply unit

2: Bias voltage compensation circuit

21: Voltage compensation unit

Claims (15)

An OLED display device has a main substrate, at least one flexible circuit board and an OLED panel, the at least one flexible circuit board connects the main substrate and the OLED panel, the OLED display device is characterized in that: the main substrate is on the A bias voltage compensation circuit is provided, the bias voltage compensation circuit has a plurality of first buffer circuits and/or a plurality of second buffer circuits, and each of the first buffer circuits is used to generate a first buffer circuit according to a first reference voltage a bias voltage, each of the second buffer circuits is used for generating a second bias voltage according to a second reference voltage, and the first bias voltage is higher than the second bias voltage; and the OLED panel has a plurality of partitions, and each of the partitions is coupled to a first bias voltage and/or a second bias voltage through a flexible circuit board. The OLED display device of claim 1, wherein the first buffer circuit and the second buffer circuit are both an operational amplifier circuit. The OLED display device of claim 1, wherein the OLED panel is an active OLED panel or a passive OLED panel. A bias voltage compensation circuit is applied in an OLED display including at least one display driving chip, a bias voltage providing unit and an OLED display panel; wherein, the OLED display panel includes M×N sub-pixel units, And there is a signal transmission distance and an RC path impedance positively correlated with the signal transmission distance between the M sub-pixel units arranged along the same row and the bias voltage supply unit; the bias voltage compensation The circuit is coupled between the bias voltage providing unit and the OLED display panel, and includes: N/L voltage compensation units, coupled to at least one reference bias voltage transmitted from the bias voltage providing unit, for according to The RC path impedance is used to perform a voltage compensation process on at least one of the reference bias voltages, so as to generate (M/K)×(N/L) at least one bias voltages and transmit them to each of the K×L reference bias voltages. Describe (M/K)×(N/L) display areas of the sub-pixel unit; wherein, M, N, K, and L are all positive integers. The bias voltage compensation circuit of claim 4, wherein each of the voltage compensation units comprises: M/K first voltage compensation processing units, wherein each of the first voltage compensation processing units includes a first operational amplifier, a first operational amplifier coupled between a negative input terminal and an output terminal of the first operational amplifier a first resistor, and a second resistor coupled between the output end of the first operational amplifier and the display area; and M/K second voltage compensation processing units, wherein each of the second voltage compensation processing units includes a second operational amplifier, a second operational amplifier coupled between a negative input terminal and an output terminal of the second operational amplifier A third resistor, a fourth resistor coupled between the output terminal of the second operational amplifier and the display area, and a first resistor coupled to the negative input terminal of the second operational amplifier and the third resistor at the same time five resistors, and a sixth resistor coupled to a positive input end of the second operational amplifier; The bias voltage providing unit transmits a first reference bias voltage to a positive input terminal of the first operational amplifier, and the bias voltage providing unit transmits a second reference bias through the fifth resistor voltage to the negative input terminal of the second operational amplifier. The bias voltage compensation circuit of claim 5, wherein the output end of the first operational amplifier, the first resistor and the negative input end of the first operational amplifier form a negative feedback path, so that each A voltage compensation effect of the first voltage compensation processing unit on the first reference bias voltage is determined by the output impedance of the first operational amplifier and/or the resistance value of the first resistor. The bias voltage compensation circuit of claim 6, wherein each of the first voltage compensation processing units further comprises: an input resistor simultaneously coupled to the negative input terminal of the first operational amplifier and the first resistor, A voltage compensation effect of each of the first voltage compensation processing units for the first reference bias voltage is determined by the output impedance of the first operational amplifier, the resistance value of the first resistor, and/or the resistance of the input resistor value determined. The bias voltage compensation circuit of claim 5, wherein the output end of the second operational amplifier, the third resistor and the negative input end of the second operational amplifier form a negative feedback path, so that each A voltage compensation effect of the second voltage compensation processing unit for the second reference bias voltage is determined by the output impedance of the second operational amplifier, the resistance value of the third resistor, and/or the resistance value of the fifth resistor. Decide. An OLED display device having the OLED display according to any one of claims 4 to 8 and a bias voltage compensation circuit. An information processing device has an OLED display including at least one display driver chip, a bias voltage supply unit and an OLED display panel; wherein, the OLED display panel includes M×N sub-pixel units, and arranged in the same row There is a signal transmission distance and an RC path impedance positively correlated with the signal transmission distance between each of the M sub-pixel units and the bias voltage supply unit; it is characterized in that the information processing device includes a coupling A bias voltage compensation circuit between the bias voltage supply unit and the OLED display panel, and the bias voltage compensation circuit includes: N/L voltage compensation units, coupled to the bias voltage supplied from the bias voltage supply unit at least one reference bias voltage for performing a voltage compensation process on the at least one reference bias voltage according to the RC path impedance, so as to generate (M/K)×(N/L) at least one bias voltage The partitions are transmitted to (M/K)×(N/L) display areas each including K×L sub-pixel units; wherein M, N, K, and L are all positive integers. The information processing device of claim 10, wherein each of the voltage compensation units includes: M/K first voltage compensation processing units, wherein each of the first voltage compensation processing units includes a first operational amplifier, a first resistor coupled between a negative input terminal and an output terminal of the first operational amplifier, and a second resistor coupled between the output terminal of the first operational amplifier and the display area and M/K second voltage compensation processing units, wherein each of the second voltage compensation processing units includes a second operational amplifier, coupled between a negative input terminal and an output terminal of the second operational amplifier a third resistor of the a fifth resistor, and a sixth resistor coupled to a positive input end of the second operational amplifier; The bias voltage providing unit transmits a first reference bias voltage to a positive input terminal of the first operational amplifier, and the bias voltage providing unit transmits a second reference bias through the fifth resistor voltage to the negative input terminal of the second operational amplifier. The information processing device of claim 11, wherein the output end of the first operational amplifier, the first resistor and the negative input end of the first operational amplifier form a negative feedback path, so that each of the first A voltage compensation effect of the voltage compensation processing unit on the first reference bias voltage is determined by the output impedance of the first operational amplifier and/or the resistance value of the first resistor. The information processing device of claim 11, wherein each of the first voltage compensation processing units further comprises: an input resistor simultaneously coupled to the negative input terminal of the first operational amplifier and the first resistor, so that each A voltage compensation effect of the first voltage compensation processing unit for the first reference bias voltage is determined by the output impedance of the first operational amplifier, the resistance value of the first resistor, and/or the resistance value of the input resistor. Decide. The information processing device of claim 11, wherein the output terminal of the second operational amplifier, the third resistor and the negative input terminal of the second operational amplifier form a negative feedback path, so that each of the second operational amplifiers forms a negative feedback path. A voltage compensation effect of the voltage compensation processing unit for the second reference bias voltage is determined by the output impedance of the second operational amplifier, the resistance value of the third resistor, and/or the resistance value of the fifth resistor. The information processing device according to any one of claims 10 to 14, comprising a smart phone, smart watch, smart bracelet, smart TV, tablet computer, notebook computer, all-in-one computer, and access control An electronic device selected from the group of devices.

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