TWI767635B - Flyback converter power supply and control method thereof - Google Patents

Abstract

A flyback converter power supply and a control method thereof are provided. The flyback converter power supply includes a synchronous rectification field effect transistor and a synchronous rectification controller for controlling on and off of the synchronous rectification field effect transistor, wherein the synchronous rectification controller is configured to: based on the synchronous rectification field effect The drain voltage of the transistor, the synchronous rectification turn-on threshold, and the synchronous rectification turn-off threshold generate the synchronous rectification switching signal; based on the synchronous rectification switching signal and the predetermined clock signal, the most frequency envelope of each cluster for shielding the synchronous rectification switching signal is generated. a rectification cycle mask signal for the first one or more synchronous rectification cycles; and based on the synchronous rectification switching signal and the rectification cycle mask signal, a gate drive signal for driving the synchronous rectification field effect transistor to be turned on and off is generated.

Description

Flyback converter power supply and control method thereof

The invention relates to the field of circuits, in particular to a flyback converter power supply and a control method thereof.

Flyback converter power supplies are widely used in the conversion between AC/DC (Alternate Current, AC/Direct Current, DC) and DC/DC (DC/DC), usually including power MOS field effect transistors, transformers, diodes , and capacitors, wherein: the Pulse Width Modulation (PWM) signal controls the on and off of the power MOS field effect transistor; when the power MOS field effect transistor is in the on state, the input of the flyback converter power supply The voltage is connected to the primary coil of the transformer, and the secondary coil of the transformer generates a first induced voltage by inducing the voltage across the primary coil of the transformer. The first induced voltage makes the diode in a reverse biased state and cannot be turned on. The stored electrical energy provides voltage and current to the load; when the power MOS field effect transistor is in an off state, the secondary coil of the transformer generates a second induced voltage through the voltage across the primary coil of the induction transformer, and the second induced voltage makes the two The pole body is in a forward biased state and is turned on, at this time, the electrical energy stored in the transformer core is transferred to the capacitor and the load.

A flyback converter power supply according to an embodiment of the present invention includes a synchronous rectification field effect transistor and a synchronous rectification controller for controlling the turn-on and turn-off of the synchronous rectification field effect transistor, wherein the synchronous rectification controller is configured as : Based on the drain voltage of the synchronous rectifier field effect transistor, the synchronous rectification turn-on threshold, and the synchronous rectification turn-off threshold, a synchronous rectification switching signal is generated; based on the synchronous rectification switching signal and a predetermined clock signal, a A rectification cycle mask signal for the first one or more synchronous rectification cycles in the frequency envelope of each cluster; and based on the synchronous rectification switching signal and the rectification cycle mask signal, a gate for driving the synchronous rectification field effect transistor to be turned on and off is generated pole drive signal.

According to a control method for a flyback converter power supply according to an embodiment of the present invention, the flyback converter power supply includes a synchronous rectification field effect transistor, the method includes: based on the drain voltage of the synchronous rectification field effect transistor, the synchronous rectification is turned on The threshold value, and the synchronous rectification turn-off threshold, generate a synchronous rectification switching signal; based on the synchronous rectification switching signal and the predetermined clock signal, generate a threshold for shielding the first one or more synchronous rectification cycles in each cluster of frequency envelopes of the synchronous rectification switching signal. a rectification period shielding signal; and based on the synchronous rectification switching signal and the rectification period shielding signal, a gate driving signal for driving the on and off of the synchronous rectification field effect transistor is generated.

According to the flyback converter power supply and the control method thereof according to the embodiments of the present invention, the first one or more synchronous rectification cycles in each frequency envelope of the synchronous rectification switching signal can be shielded, so that the synchronous rectification field effect transistor is The shielded one or more synchronous rectification cycles are kept in the off state, and the freewheeling is only carried out by the conduction of the parasitic body diode, so as to avoid the simultaneous conduction of the primary side and the secondary side of the transformer in the flyback converter power supply, and then Avoid damage to the synchronous rectifier field effect transistor due to the simultaneous conduction of the primary side and the secondary side of the transformer.

300,700: SR controller chip

AND: and gate

AVDD: chip internal power supply

burst_det: rectification cycle shielding signal

burst_dis: Rectification on forced signal

Cbulk: filter capacitor

Cgk, Csn: Capacitance

Cout: output capacitance

Comp_sron:SR turns on the comparator

Comp_sroff: SR shutdown comparator

Cp: power supply capacitor

clk_60k: 60kHz clock signal

D1, D2, D3, D4: diode rectifier bridge

Dp: Power Diode

Dsn: Diode

dff:D flip-flop

f: working frequency

f_5k: timing output signal

Gate: Gate drive signal output port

GND: chip ground port

gate1,gate2,gate2': gate drive signal

INV: Inverter

Isec: current

iref: reference current

k‧vdsp: a certain proportion of vdsp value

MNH: High Voltage Switch

MP, MN: Transistor

MS1: High Voltage Field Effect Transistor

MS2: SR FET

min_ton,ton_min: minimum on-time control signal

NOR1, NOR2: Inverted OR gate

OR: or gate

on det: Rectification open sensing signal

on ctrl:SR open control signal

off det: rectifier turn-off sensing signal

QN: RS latch inverting output

R: RS latch reset terminal

Rcs: sense resistance

Rds2(on): On resistance

Rst: start-up resistance

S:RS latch set terminal

sr: Synchronous rectification switching signal

T: Three-winding transformer

ts,tval,tgt,tc: time

turn on: SR turn on signal

turn off:SR shutdown signal

U1: Pulse Width Modulation (PWM) Controller Chip

U2: Synchronous Rectification (SR) Controller Chip

Vd: drain voltage

Vds: differential pressure

vdsp: high level amplitude

Vin: output voltage sensing port

vout: output voltage

vref: reference voltage

Vs: source voltage

vt(on): SR on threshold

vt(off): SR shutdown threshold

vt(reg): Adjustment value

The present invention can be better understood from the following description of specific embodiments of the present invention in conjunction with the drawings, wherein:

1 and 2 illustrate exemplary system circuit diagrams of a flyback converter power supply including a synchronous rectifier.

FIG. 3 shows an exemplary internal circuit diagram for the conventional Synchronous Rectifier (SR) controller die shown in FIGS. 1 and 2 .

Fig. 4 shows the operation of the flyback converter power supply shown in Fig. 1 and Fig. 2 in the Distributed Computing Model (DCM) mode with the synchronous rectifier when the SR controller chip shown in Fig. 3 is used. The timing diagram of the turn-on and turn-off related signals.

Fig. 5 shows the turn-on and turn-off of the synchronous rectifier when the flyback converter power supply shown in Fig. 1 and Fig. 2 works normally in the Burst state using the SR controller chip shown in Fig. 3 Timing diagram for multiple signals.

Fig. 6 shows the turn-on and turn-off of the synchronous rectifier when the flyback converter power supply shown in Fig. 1 and Fig. 2 works abnormally in the Burst state when the SR controller chip shown in Fig. 3 is used. Timing diagram for multiple signals.

7 shows an exemplary internal circuit diagram of an SR controller die for the flyback converter power supply shown in FIGS. 1 and 2 according to an embodiment of the present invention.

FIG. 8 shows an exemplary internal circuit diagram of the drive control module shown in FIG. 7 .

FIG. 9 shows a timing diagram of a plurality of signals related to the drive control module shown in FIG. 8 .

Features and exemplary embodiments of various aspects of the invention are described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present invention by illustrating examples of the invention. The present invention is in no way limited to any specific configurations and algorithms set forth below, but covers any modification, substitution and improvement of elements, components and algorithms without departing from the spirit of the invention. In the drawings and the following description, well-known structures and techniques have not been shown in order to avoid unnecessarily obscuring the present invention.

1 and 2 show exemplary system circuit diagrams of a flyback converter power supply with a synchronous rectifier. As shown in Figure 1 and Figure 2, T is a three-winding transformer, D1-D4 constitute a diode rectifier bridge, Cbulk is a filter capacitor, Rst is a starting resistor, Cp is a power supply capacitor, Dp is a power supply diode, Rsn, Csn , Dsn constitute an RCD clamping absorption circuit, U1 is a pulse width modulation (Pulse Width Modulation, PWM) controller chip, MS1 is a high-voltage field effect transistor, Rcs is a sensing resistor, Cout is an output capacitor, and U2 is a synchronous rectifier ( Synchronous Rectification, SR) controller chip, MS2 is SR field effect transistor, U2 and MS2 together constitute a synchronous rectifier that replaces the traditional Schottky rectification diode.

The flyback converter power supply shown in Figures 1 and 2 has lower heat loss, higher power conversion efficiency, and higher current output capability due to the lower on-voltage drop of the SR FET MS2 .

Generally, synchronous rectifiers are widely used in flyback converter power supplies that require a large current output capability, and the flyback converter power supply operates in a discontinuous conduction mode (DCM) according to its input voltage, output voltage, and load. ), critical conduction (Quasi-Resonant, QR) mode, or continuous conduction mode (Continuous Conduction Mode, CCM) work.

FIG. 3 shows an exemplary internal circuit diagram for the conventional SR controller die 300 shown in FIGS. 1 and 2 . As shown in Figure 3, the voltage regulator module generates the internal power supply AVDD of the chip; the voltage/current reference module generates the reference voltage vref and the reference current iref based on the internal power supply AVDD of the chip; the drain voltage Vd of the SR field effect transistor MS2 passes through the high voltage The switch MNH is connected to the input of the SR on comparator Comp_sron and the input of the SR off comparator Comp_sroff; the SR on comparator Comp_sron is based on the drain voltage Vd of the SR field effect transistor MS2, the SR on threshold vt(on), and The reference ground voltage generates the rectification turn-on sensing signal on det; the SR turn-off comparator Comp_sroff generates the rectifier turn-off sensing based on the drain voltage Vd of the SR field effect transistor MS2, the SR turn-off threshold vt(off), and the reference ground voltage Signal off det; SR turn-on control module generates SR turn-on control signal on ctrl based on drain voltage Vd of SR FET MS2; inverse OR gate NOR1 produces SR based on rectification turn-on sensing signal on det and SR turn-on control signal on ctrl The turn-on signal is turned on; the inverse-OR gate NOR2 generates the SR turn-off signal turn off based on the rectification turn-off sensing signal off det and the minimum on-time control signal min_ton; the RS latch is based on the SR turn-on signal turn on and the SR turn-off signal turn off The synchronous rectification switching signal sr is generated; the minimum on-time control module generates the minimum on-time control signal min_ton based on the synchronous rectification switching signal sr; the driver module generates the gate driving signal gate2 based on the synchronous rectification switching signal sr.

Here, the minimum on-time control signal min_ton is used to control the minimum on-time of the SR field effect transistor MS2, and the gate driving signal gate2 is used to drive the SR field effect transistor MS2 to be turned on or off. When the synchronous rectification switching signal sr is at a high level, the minimum on-time control signal min_ton is at a high level and the duration is the minimum on-time (for example, 1.5us) of the SR FET; when the synchronous rectification switching signal sr is at a low level, the minimum The on-time control signal min_ton is at a low level.

Fig. 4 shows that in the case of using the SR controller wafer shown in Fig. 3, Figures 1 and 2 are timing diagrams of various signals related to the turn-on and turn-off of the synchronous rectifier when the flyback converter power supply operates in DCM mode. In Figure 4, gate1 is the gate driving signal for the high voltage field effect transistor MS1; Vds is the voltage difference between the drain voltage Vd and the source voltage Vs of the SR field effect transistor MS2; gate2 is used for SR The gate driving signal of the field effect transistor MS2; Isec is the current flowing through the secondary coil of the transformer T; min_ton is the minimum on-time control signal used to control the minimum on-time of the SR field effect transistor MS2; vdsp is the SR field The high level amplitude of the voltage difference Vds between the drain voltage Vd and the source voltage Vs of the effect transistor MS2; k·vdsp is a certain proportion of vdsp value, for example, k=0.75; vt(on) is the SR turn-on threshold , for example, -200mV; vt(reg) is the adjustment value of the voltage difference Vds between the drain voltage Vd and the source voltage Vs of the SR FET MS2, for example, -30mV; vt(off) is the SR turn-off Threshold, for example, 0mV; vout is the output voltage of the flyback converter power supply, for example, 3V~25V; ts is the voltage difference between the drain voltage Vd and the source voltage Vs of the SR field effect transistor MS2 Vds from k‧ The time when vdsp drops to vt(on); tval is the time when the voltage difference Vds between the drain voltage Vd and the source voltage Vs of the SR field effect transistor MS2 is continuously greater than a predetermined voltage, eg, 1.5V.

It should be noted that, in the flyback converter power supply shown in FIG. 1 and FIG. 2, since the source of the SR field effect transistor MS2 is grounded, the drain voltage Vd of the SR field effect transistor MS2 is the SR field effect The voltage difference Vds between the drain voltage Vd and the source voltage Vs of the transistor.

In the case of using the SR controller chip shown in Figure 3, the turn-on conditions of the synchronous rectifier include: (1) ts<150ns, (2) tval>6us when f>5kHz or tval>12us when f<5kHz, and (3) Vds<vt(on), where f is the operating frequency of the synchronous rectifier. When the flyback converter power supply shown in Fig. 1 and Fig. 2 works in the burst state, the operating frequency f of the synchronous rectifier between each cluster of frequency envelopes of the gate drive signal gate1 is less than 5kHz, as long as the condition (1 ) and (3) or conditions (2) and (3) are satisfied simultaneously, the synchronous rectifier will turn on. Here, the Burst state is a case of the DCM working mode.

In the SR controller chip 300 shown in FIG. 3 , the SR turn-on comparator Comp_sron generates the rectifier turn-on by comparing the superposition result of the drain voltage Vd of the SR field effect transistor MS2 and the SR turn-on threshold vt(on) with the reference ground voltage. Sensing signal on det; SR turn-off ratio The comparator Comp_sroff compares the superposition result of the drain voltage Vd of the SR field effect transistor MS2 and the SR turn-off threshold vt(off) with the reference ground voltage to generate the rectification turn-off sensing signal off det; the SR turn-on control module passes the judgment Whether the drain voltage Vd of the SR field effect transistor MS2 satisfies the condition (1) or (2), the SR turn-on control signal on ctrl is generated, wherein the SR turn-on control signal on ctrl is when the condition (1) or (2) is satisfied. Low level, and high level when both conditions (1) and (2) are not satisfied.

It can be seen from Figure 1 to Figure 4 that during the normal operation of the flyback converter power supply shown in Figure 1 and Figure 2 in the DCM mode, when the gate drive signal gate1 changes from a high level to a low level, the high-voltage field effect The transistor MS1 changes from the on state to the off state, the voltage difference Vds starts to gradually decrease from the platform voltage high level amplitude vdsp, and the current Isec starts to gradually decrease from the maximum current value. At this time, the SR field effect transistor MS2 is not turned on yet, and the current Isec flows through the body diode of the SR field effect transistor MS2 for freewheeling. After the turn-on condition (1) or (2) of the synchronous rectifier is satisfied and Vds<vt(on), the synchronous rectifier switching signal sr changes from low level to high level, and the gate driving signal gate2 starts to increase gradually from low level, so that The SR field effect transistor MS2 changes from the off state to the on state (ie, the synchronous rectifier is on). When the voltage drop generated by the current Isec on the on-resistance Rds2(on) of the SR field effect transistor MS2, that is, the voltage difference Vds is slightly larger than the adjustment value vt(reg), the gate driving signal gate2 gradually decreases, and the SR field effect voltage The on-resistance Rds2(on) of the crystal MS2 gradually increases, so that the voltage difference Vds is stabilized near the adjustment value vt(reg). As the current Isec further decreases, the increase in the on-resistance Rds2(on) of the SR field effect transistor MS2 is not enough to maintain the voltage difference Vds near the adjustment value vt(reg), and the voltage difference Vds begins to increase. When Vd>vt(off), the synchronous rectification switching signal sr changes from a high level to a low level, and the gate driving signal gate2 is quickly pulled low, so that the SR field effect transistor MS2 changes from the on state to the off state (ie, synchronous rectifier off).

Here, since the gate driving signal gate2 drops from a high level to a lower value in advance, the time for the gate driving signal gate2 to change from a high level to a low level is shortened, and the turn-off of the synchronous rectifier is accelerated. In CCM mode of operation, this can reduce the peak voltage of the dropout Vds.

However, for the flyback converter power supply that actually works in the Burst state, the During the charging and discharging of the capacitor Csn on the primary side of the transformer T and the reverse recovery of the diode Dsn and the power supply diode Dp, during the first synchronous rectification cycle of each cluster frequency envelope of the gate drive signal gate1, the SR field The demagnetization waveform of the drain voltage Vd of the effect transistor MS2 and the resonant waveform are distorted, which can lead to mis-turning of the SR field effect transistor MS2. After the SR field effect transistor MS2 is turned on, the SR field effect transistor MS2 cannot be turned off immediately due to the control of the minimum on-time control signal ton_min. If the high voltage field effect transistor MS1 on the primary side of the transformer T happens to be in the SR field effect state When the transistor MS2 is turned on during the minimum on-time, the primary side and the secondary side of the transformer T are turned on at the same time, and the voltage difference Vds will generate a very high peak voltage. The voltage of the rated withstand voltage of the field effect transistor MS2 will cause damage to the SR field effect transistor MS2.

Fig. 5 shows the turn-on and turn-off of the synchronous rectifier when the flyback converter power supply shown in Fig. 1 and Fig. 2 works normally in the Burst state using the SR controller chip shown in Fig. 3 Timing diagram for multiple signals. In FIG. 5, gate1 is the gate driving signal for the high voltage field effect transistor MS1, Vds is the voltage difference between the drain voltage Vd and the source voltage Vs of the SR field effect transistor MS2, and gate2 is used for SR The gate drive signal of the field effect transistor MS2, Isec, is the current flowing through the secondary coil of the transformer T. It can be seen that when the flyback converter power supply shown in Figures 1 and 2 works normally in the Burst state, each cluster of frequency envelopes of the gate drive signal gate1 includes three synchronous rectification cycles.

Fig. 6 shows the turn-on and turn-off of the synchronous rectifier when the flyback converter power supply shown in Fig. 1 and Fig. 2 works abnormally in the Burst state when the SR controller chip shown in Fig. 3 is used. Timing diagram for multiple signals. In FIG. 6, gate1 is the gate driving signal for the high voltage field effect transistor MS1; Vds is the voltage difference between the drain voltage Vd and the source voltage Vs of the SR field effect transistor MS2; gate2 is used for SR The gate driving signal of the field effect transistor MS2; min_ton is the minimum on-time control signal used to control the minimum on-time of the SR field effect transistor MS2; vdsp is the drain voltage Vd and the source voltage of the SR field effect transistor MS2 The high level amplitude of the voltage difference Vds between Vs; k‧vdsp is a certain proportion of vdsp value, for example, k=0.75; vt(on) is the SR turn-on threshold, for example, -200mV; vt(reg) is the SR field The adjustment value of the voltage difference Vds between the drain voltage Vd and the source voltage Vs of the effect transistor MS2, for example For example, -30mV; vt(off) is the SR turn-off threshold, for example, 0mV; vout is the output voltage of the flyback converter power supply, for example, 3V~25V; ts is the drain voltage Vd of the SR field effect transistor MS2 and The time for the voltage difference Vds between the source voltages Vs to drop from k·vdsp to the SR turn-on threshold vt(on); tval is the voltage difference Vds between the drain voltage Vd and the source voltage Vs of the SR field effect transistor MS2 The time that is continuously greater than the predetermined voltage, for example, the time of 1.5V; tgt is the duration time that the primary side and the secondary side of the transformer T are in the conducting state at the same time.

It can be seen from Figure 6 that during the first synchronous rectification cycle in a certain frequency envelope of the gate driving signal gate1, due to the charging and discharging of the capacitor Csn and the reverse recovery time of the diode Dp and the power supply diode Dsn If it is too long, the demagnetization waveform and resonance waveform of the differential pressure Vds will be obviously distorted. Specifically, the time for the voltage difference Vds to drop from the high-level amplitude vdsp to the SR turn-on threshold vt(on) increases to nearly 1us. Although the SR turn-on condition (1) is not satisfied, the SR turn-on condition (2) is satisfied, and wait until the voltage After the difference Vds drops to the SR turn-on threshold vt(on), the SR field effect transistor MS2 will still be turned on. At this time, the residual demagnetization time is short, the demagnetization current quickly drops to zero, and the voltage difference Vds quickly rises to greater than the SR turn-off threshold. vt(off), but due to the control of the minimum on-time control signal ton_min, the SR FET MS2 cannot be turned off and cannot be turned off until the minimum on-time expires.

Further, it can be seen from Fig. 6 that after demagnetization, the SR field effect transistor MS2 continues to conduct, and the output current of the output capacitor Cout flows in the reverse direction through the SR field effect transistor MS2, resulting in a decrease in the resonance waveform of the voltage difference Vds. The edge becomes faster, the amplitude becomes larger, and even the high-level amplitude vdsp is higher. In some cases, the pulse width of the resonant waveform of the voltage difference Vds will also increase, which is why the time tval increases to 12us when f<5kHz in the SR turn-on condition (2). Since the falling edge of the resonant waveform of the voltage difference Vds becomes faster, the SR turn-on condition (1) is satisfied, and when the voltage difference Vds drops to the SR turn-on threshold vt(on), the SR field effect transistor MS2 will be falsely turned on. Similarly, due to the control of the minimum on-time control signal ton_min, the SR field effect transistor MS2 cannot be turned off in time, and the output current of the output capacitor Cout flows in the reverse direction through the SR field effect transistor MS2, and the next resonant waveform of the voltage difference Vds drops. The edge becomes faster, and the SR field effect transistor MS2 is turned on again. After the SR field effect transistor MS2 is turned on during the resonant period of the voltage difference Vds, it cannot be turned off in time due to the control of the minimum on-time control signal ton_min. If it happens to hit the primary side of the transformer T1 The high-voltage field effect transistor MS1 is turned on, then the primary side and the secondary side of the transformer T1 are turned on at the same time (the duration of the simultaneous conduction is tgt), and the voltage difference Vds will generate a large peak voltage, which is superimposed on the high level. A voltage greater than the rated withstand voltage value of the SR field effect transistor MS2 will be generated on the amplitude vdsp, resulting in damage to the SR field effect transistor MS2.

In order to avoid the above situation, the SR controller wafer 700 shown in FIG. 7 for the flyback converter power supply shown in FIG. 1 and FIG. 2 according to an embodiment of the present invention is proposed. As can be seen from FIG. 3 and FIG. 7 , the difference between the SR controller chip 700 and the SR controller chip 300 is that a drive control module is added, and other parts can be the same as the SR controller chip 300 . FIG. 8 shows an exemplary internal circuit diagram of the drive control module shown in FIG. 7 .

As shown in FIGS. 7 and 8 , in some embodiments, the SR controller die 700 may be configured to: based on the drain voltage (eg, Vd) of the SR FET (eg, MS2 ), the SR turn-on threshold ( For example, Vt(on)) and SR turn-off threshold (for example, Vt(off)), generate a synchronous rectification switching signal (for example, sr); based on the synchronous rectification switching signal and a predetermined clock signal (for example, clk_60k), generate a A rectification period mask signal (eg, burst_det) for the first one or more synchronous rectification cycles in each cluster frequency envelope of the masking synchronous rectification switching signal; The gate drive signal (eg, gate2') for the turn-on and turn-off of the FET.

Here, the rectification cycle masking signal can mask out the first one or more synchronous rectification cycles in each frequency envelope of the synchronous rectification switching signal, so that the SR FET is in the masked one or more synchronous rectification cycles. Keep the off state and freewheeling only through the conduction of the parasitic diode, so as to avoid the simultaneous conduction of the primary side and the secondary side of the transformer in the flyback converter power supply, thereby avoiding the SR field effect transistor due to the primary side of the transformer. And the secondary side is turned on at the same time and damaged.

As shown in FIGS. 7 and 8 , in some embodiments, the SR controller chip 700 may be further configured to: generate an SR turn-on signal (eg, turn on) based on the drain voltage of the SR FET and the SR turn-on threshold. ); based on the drain voltage of the SR FET, the SR turn-off threshold, and the minimum on-time control signal (for example, min_ton), generate the SR turn-off signal (for example, turn off); and based on the SR turn-on signal and the SR turn-off signal break the signal, produce the same Step-by-step rectification switching signal (for example, based on the SR turn-on signal and the SR turn-off signal, the RS latch can be used to generate the synchronous rectification switching signal). The minimum on-time control signal is generated based on the synchronous rectification switching signal. Here, under the control of the minimum on-time control signal, the SR FET can be prevented from being turned off by mistake due to the disturbance of the voltage difference between the drain voltage and the source voltage when the SR field effect transistor is just turned on.

As shown in FIG. 7 and FIG. 8 , in some embodiments, when the drain voltage of the SR field effect transistor is less than the SR turn-on threshold, the SR turn-on signal is at a high level; when the drain voltage of the SR field effect transistor is not less than When the SR turn-on threshold is set, the SR turn-on signal is low. When the drain voltage of the SR FET is greater than the SR turn-off threshold and the minimum on-time control signal is at a low level, the SR turn-off signal is at a high level; when the drain voltage of the SR FET is not greater than the SR turn-off threshold or When the minimum on-time control signal is high, the SR turn-off signal is low. When the rectification period shielding signal is high and the rectification turn-on forcing signal is low, or the synchronous rectification switching signal is low, the gate drive signal for the SR FET is low; when the rectification period shielding signal is low Or when the rectification turn-on forcing signal is high and the synchronous rectification switching signal is high, the gate driving signal for the SR FET is high.

As shown in FIGS. 7 and 8 , in some embodiments, the SR controller chip 700 may be further configured to: generate a rectification turn-on force signal (eg, burst_dis based on the drain voltage of the SR FET and the SR turn-on threshold) ); and based on the synchronous rectification switching signal (eg, sr), the rectification period mask signal (eg, burst_det), and the rectification turn-on forcing signal (burst_dis), generate a gate drive signal (eg, gate2) for the SR FET '). Here, under the action of the rectification-on forcing signal, the SR field effect transistor can be forced from the off state to the on state. In addition, in the current synchronous rectification cycle after the shield is released, the turn-off of the SR FET is no longer controlled by the minimum on-time control signal, which not only prevents the power supply of the flyback converter operating in the light-load Burst state from switching to In the CCM working mode, the peak voltage difference between the drain voltage and the source voltage of the SR FET caused by the SR FET has not changed from the off state to the on state, and the system efficiency loss is reduced. The reliability of the flyback converter power supply is greatly improved.

As shown in FIG. 7 and FIG. 8 , when the duration for which the drain voltage of the SR FET is less than the SR turn-on threshold is greater than a predetermined time value (for example, tc, generally 2.5us), the rectification turn-on forcing signal is at a high level; When the duration of the SR FET's drain voltage less than the SR turn-on threshold is not greater than a predetermined time value (for example, tc, generally 2.5us) or the SR FET's drain voltage is not less than the SR turn-on threshold, the rectifier Turn on forcing the signal to be low.

As shown in Figures 7 and 8, when the rectification cycle shielding signal is at a low level or the rectification turn-on forcing signal is at a high level, and the synchronous rectification switching signal is at a high level, the gate drive signal is at a high level; when the rectification cycle shielding signal is at a high level When the commutation turn-on force signal is low level, or the synchronous rectification switch signal is low level, the gate driving signal is low level.

As shown in FIG. 8 , in some embodiments, the drive control module includes: 1) a frequency sensing part of the synchronous rectification switching signal, 2) a rectification cycle counting and shielding part, and 3) a continuation of Vd<vt(on) The time is greater than the sensing portion of tc. In Figure 8, dff is a D flip-flop, OR is an OR gate, AND is an AND gate, INV is an inverter, clk_60k is a 60kHz clock signal, and sr is a synchronous rectification switch signal. Specifically, the 0-shot module generates a low pulse with a pulse width of 150ns on the rising edge of the synchronous rectification switching signal sr; the timing output signal f_5k senses whether the interval between adjacent frequency envelopes of the synchronous rectification switching signal sr is greater than 200us ;When the frequency of the synchronous rectification switching signal sr is lower than 5kHz, the rising edge of the timing output signal f_5k makes the rectification cycle shielding signal burst_det change from a low level to a high level; the synchronous rectification switching signal sr is shielded and starts to count; when the shielded When 3 synchronous rectification cycles are completed, the rectification cycle shielding signal burst_det changes from high level to low level, the shielding is released, and the synchronous rectification switching signal sr is output normally; during the period when the synchronous rectification switching signal sr is shielded, the circuit at the bottom of Figure 8 is used for Sensing whether the duration of Vd<vt(on) is greater than tc; if it is, the rectification turn-on forcing signal burst_dis changes from low level to high level, allowing the synchronous rectification switching signal sr to be output, and the SR field effect transistor MS2 is forced to be turned off. The off state becomes the on state and it is no longer controlled by the minimum on time control signal min_ton from the on state to the off state, and it can be turned off normally when Vd>vt(off). Here, the on det signal is the output of the SR open comparator Comp_sron in Figure 7, the turn off signal is the output of the inverse OR gate NOR2 in Figure 7; Comp is the comparator, and transistors MP, MN, current source iref, capacitor Cgk together form the tc timing circuit.

FIG. 9 shows a timing diagram of a plurality of signals related to the drive control module shown in FIG. 8 . It can be seen that when the flyback converter power supply works in the Burst state, each cluster of frequency envelopes of the synchronous rectification switching signal sr includes 4 synchronous rectification cycles, and the interval between adjacent frequency envelopes is greater than 200us. Due to the addition of the control mechanism proposed in this paper, it can be seen from the waveform of the gate driving signal gate2' that the first three synchronous rectification cycles of each cluster of frequency envelopes of the synchronous rectification switching signal sr are shielded, and the SR field effect transistor MS2 keeps the In the off state, the freewheeling current is only conducted through the parasitic body diode, which avoids the simultaneous conduction of the primary side and the secondary side of the transformer, and the peak voltage problem mentioned above will no longer occur. In Fig. 9, when the demagnetization time becomes longer due to the transition of the flyback converter power supply from the Burst state to the CCM operating mode, due to the addition of a sensing mechanism where the duration of Vd<vt(on) is greater than tc, the shielding signal remains despite the commutation period. It is a high level, but the SR field effect transistor MS2 will be forced from the off state to the on state under the action of the rectification on-force signal, avoiding the reverse recovery of the parasitic diode of the SR field effect transistor MS2. The peak voltage when the flyback converter power supply is in the CCM operating mode, which greatly improves the reliability of the flyback converter power supply including the synchronous rectifier.

The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. For example, the algorithms described in particular embodiments may be modified without departing from the basic spirit of the invention in system architecture. Accordingly, the present embodiments are to be considered in all respects as illustrative and not restrictive, the scope of the present invention is defined by the appended claims rather than the foregoing description, and the meanings and equivalents falling within the claims All changes within the scope of the invention are thus included in the scope of the present invention.

700:SR Controller Chip

AVDD: chip internal power supply

Comp_sron:SR turns on the comparator

Comp_sroff: SR shutdown comparator

Gate: Gate drive signal output port

GND: chip ground port

gate2’: gate drive signal

iref: reference current

MNH: High Voltage Switch

min_ton: minimum on-time control signal

NOR1, NOR2: Inverted OR gate

on det: Rectification open sensing signal

on ctrl:SR open control signal

off det: rectifier turn-off sensing signal

QN: RS latch inverting output

R: RS latch reset terminal

S:RS latch set terminal

sr: Synchronous rectification switching signal

turn on: SR turn on signal

turn off:SR shutdown signal

Vd: drain voltage

Vin: output voltage sensing port

vref: reference voltage

vt(on): SR on threshold

vt(off): SR shutdown threshold

Claims (18)

A flyback converter power supply, comprising a synchronous rectification field effect transistor and a synchronous rectification controller for controlling on and off of the synchronous rectification field effect transistor, wherein the synchronous rectification controller is configured to: based on The drain voltage of the synchronous rectification field effect transistor, the synchronous rectification turn-on threshold, and the synchronous rectification turn-off threshold generate a synchronous rectification switching signal; based on the synchronous rectification switching signal and a predetermined clock signal, generate a synchronous rectification switching signal for shielding the a rectification cycle mask signal of one or more synchronous rectification cycles at the beginning of each cluster of frequency envelopes of the rectification switching signal; based on the synchronous rectification switching signal and the rectification cycle mask signal, a field effect for driving the synchronous rectification is generated The gate driving signal of the transistor is turned on and off; based on the drain voltage of the synchronous rectification field effect transistor and the synchronous rectification turn-on threshold, a synchronous rectification turn-on signal is generated; based on the synchronous rectification field effect transistor The drain voltage, the synchronous rectification turn-off threshold, and the minimum on-time control signal generate a synchronous rectification turn-off signal; and based on the synchronous rectification turn-on signal and the synchronous rectification turn-off signal, the synchronous rectification switch signal is generated , wherein the minimum on-time control signal is generated based on the synchronous rectification switching signal. The flyback converter power supply according to claim 1, wherein: when the drain voltage of the synchronous rectification field effect transistor is less than the synchronous rectification turn-on threshold, the synchronous rectification turn-on signal is at a high level; when the synchronous rectification turn-on signal is at a high level; When the drain voltage of the synchronous rectification field effect transistor is not less than the synchronous rectification turn-on threshold, the synchronous rectification turn-on signal is at a low level. The flyback converter power supply according to claim 1, wherein: when the drain voltage of the synchronous rectification field effect transistor is greater than the synchronous rectification turn-off threshold and the minimum on-time control signal is at a low level, the The synchronous rectification shutdown signal is high level; When the drain voltage of the synchronous rectification field effect transistor is not greater than the synchronous rectification turn-off threshold or the minimum on-time control signal is at a high level, the synchronous rectification turn-off signal is at a low level. The flyback converter power supply of claim 1, wherein the synchronous rectification controller is further configured to: generate a rectification turn-on based on the drain voltage of the synchronous rectification field effect transistor and the synchronous rectification turn-on threshold a forcing signal; and generating the gate driving signal based on the synchronous rectification switching signal, the rectification period shielding signal, and the rectification turn-on forcing signal. The flyback converter power supply of claim 4, wherein: when the duration of the synchronous rectification field effect transistor's drain voltage less than the synchronous rectification turn-on threshold is greater than a predetermined time value, the rectification turn-on forcing signal is a high level; when the duration of the drain voltage of the synchronous rectification field effect transistor is less than the synchronous rectification turn-on threshold value is not greater than the predetermined time value or the drain voltage of the synchronous rectification field effect transistor is not less than all When the synchronous rectification turn-on threshold is reached, the rectification turn-on forcing signal is at a low level. The flyback converter power supply according to claim 4, wherein: when the rectification period shielding signal is at a low level or the rectification turn-on forcing signal is at a high level, and the synchronous rectification switching signal is at a high level, the gate The gate driving signal is at a high level; when the rectification period shielding signal is at a high level and the rectification turn-on forcing signal is at a low level, or the synchronous rectification switching signal is at a low level, the gate driving signal is at a low level. The flyback converter power supply of claim 1, wherein the synchronous rectification controller is further configured to: generate the synchronous rectification using an RS latch based on the synchronous rectification turn-on signal and the synchronous rectification turn-off signal Synchronous rectification switching signal. The flyback converter power supply according to claim 1, wherein: when the rectification period shielding signal is at a high level and the rectification turn-on forcing signal is at a low level, or the synchronous rectification switching signal is at a low level, the gate The pole drive signal is low level; When the rectification period shielding signal is at a low level or the rectification turn-on forcing signal is at a high level, and the synchronous rectification switch signal is at a high level, the gate driving signal is at a high level. The flyback converter power supply according to claim 1, wherein the source of the synchronous rectification field effect transistor is grounded, and the drain voltage of the synchronous rectification field effect transistor is the synchronous rectification field effect transistor The voltage difference between the drain voltage and the source voltage. A control method for a flyback converter power supply, the flyback converter power supply comprising a synchronous rectification field effect transistor, the method comprising: based on a drain voltage of the synchronous rectification field effect transistor, a synchronous rectification turn-on threshold, and a synchronous rectification turn-off threshold to generate a synchronous rectification switching signal; based on the synchronous rectification switching signal and a predetermined clock signal, generate the first one or more synchronous rectifications in each cluster of frequency envelopes for shielding the synchronous rectification switching signal Periodic rectification period shielding signal; based on the synchronous rectification switching signal and the rectification period shielding signal, a gate drive signal for driving the synchronous rectification field effect transistor to be turned on and off is generated; based on the synchronous rectification The drain voltage of the field effect transistor and the synchronous rectification turn-on threshold generate a synchronous rectification turn-on signal; based on the drain voltage of the synchronous rectification field effect transistor, the synchronous rectification turn-off threshold, and the minimum on-time control signal , generate a synchronous rectification turn-off signal; and generate the synchronous rectification switching signal based on the synchronous rectification on signal and the synchronous rectification turn-off signal, wherein the minimum on-time control signal is generated based on the synchronous rectification switching signal of. The control method according to claim 10, wherein: when the drain voltage of the synchronous rectification field effect transistor is less than the synchronous rectification turn-on threshold, the synchronous rectification turn-on signal is at a high level; when the synchronous rectification field effect transistor is at a high level; When the drain voltage of the effect transistor is not less than the synchronous rectification turn-on threshold, the synchronous rectification turn-on signal is at a low level. The control method as claimed in claim 10, wherein: When the drain voltage of the synchronous rectification field effect transistor is greater than the synchronous rectification turn-off threshold and the minimum on-time control signal is at a low level, the synchronous rectification turn-off signal is at a high level; when the synchronous rectification field When the drain voltage of the effect transistor is not greater than the synchronous rectification turn-off threshold or the minimum on-time control signal is at a high level, the synchronous rectification turn-off signal is at a low level. The control method according to claim 10, further comprising: generating a rectification turn-on forcing signal based on the drain voltage of the synchronous rectification field effect transistor and the synchronous rectification turn-on threshold; and based on the synchronous rectification switch signal, the The rectification period shielding signal and the rectification turn-on forcing signal are used to generate the gate driving signal. The control method according to claim 13, wherein: when the duration for which the drain voltage of the synchronous rectification field effect transistor is less than the synchronous rectification turn-on threshold is greater than a predetermined time value, the rectification turn-on forcing signal is at a high level When the drain voltage of the synchronous rectification field effect transistor is less than the synchronous rectification turn-on threshold, the duration is not greater than the predetermined time value or the drain voltage of the synchronous rectification field effect transistor is not less than the synchronous rectification When the threshold is turned on, the rectification turn-on forcing signal is at a low level. The control method of claim 13, wherein: when the rectification period shielding signal is at a low level or the rectification turn-on forcing signal is at a high level, and the synchronous rectification switching signal is at a high level, the gate driving signal is high level; when the rectification period shielding signal is high level and the rectification turn-on forcing signal is low level, or the synchronous rectification switch signal is low level, the gate driving signal is low level. The control method of claim 10, wherein the synchronous rectification switching signal is generated by using an RS latch based on the synchronous rectification turn-on signal and the synchronous rectification turn-off signal. The control method of claim 10, wherein: when the rectification period shielding signal is at a high level and the rectification turn-on forcing signal is at a low level, or the synchronous rectification switching signal is at a low level, the gate driving signal is low level; When the rectification period shielding signal is at a low level or the rectification turn-on forcing signal is at a high level, and the synchronous rectification switch signal is at a high level, the gate driving signal is at a high level. The control method according to claim 10, wherein the source of the synchronous rectification field effect transistor is grounded, and the drain voltage of the synchronous rectification field effect transistor is the drain of the synchronous rectification field effect transistor The voltage difference between the voltage and the source voltage.

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