TWI765771B - Pixel circuit and display panel of self-compensation - Google Patents

Abstract

A pixel circuit of self-compensation is provided, which includes a light emission element, a driving transistor, a first transistor,　a reset circuit and a compensation circuit. The driving transistor is configured to provide a driving current to the light emission element through the first node, and a first terminal of the driving transistor is directly coupled with the light emission element. The first transistor includes a control terminal configured to receive an emission control signal to determine a pulse width of the driving current. A control terminal of the driving transistor is coupled with a first terminal of the first transistor at a second node, and a second terminal of the first transistor is coupled with a third node. The reset circuit is configured to reset voltages of the first node, the second node and the third node. The compensation circuit is coupled with the first node, the second node and the third node. The compensation circuit is configured to store a threshold voltage of the driving transistor detected by the compensation circuit at the first node.

Description

Self-compensating pixel circuit and display panel

The present disclosure relates to a pixel circuit and a display panel, in particular, a pixel circuit and a display panel with self-compensating threshold voltages.

Sub-millimeter light-emitting diodes (mini light-emitting diodes) and micro light-emitting diodes (micro light-emitting diodes) refer to light-emitting diodes with grain sizes above and below 75 microns, respectively. The above two light-emitting diodes can be used to fabricate pixel circuits of flexible displays, and have self-luminous properties, so they are expected to replace organic light-emitting diode (organic light-emitting diode) display technologies with short service life. However, transistors in pixel circuits often have characteristic variations due to the manufacturing process. For example, when an excimer-laser annealing method is used to fabricate a low-temperature polysilicon thin-film transistor, the threshold voltages of the driving transistors of different pixel circuits are not the same due to the inconsistent laser power. In addition, the large driving current of the sub-millimeter light-emitting diode and the micro-light-emitting diode may generate an excessive voltage difference on the current path, so that the driving transistor of the pixel circuit is out of the saturation region during operation. All of the above reasons will affect the high-quality display images provided by the sub-millimeter light-emitting diode and micro-LED displays.

The present disclosure provides a self-compensating pixel circuit, which includes a light-emitting element, a driving transistor, a first transistor, a reset circuit and a compensation circuit. The driving transistor is used for providing the driving current to the light-emitting element through the first node, and the first end of the driving transistor is directly coupled to the light-emitting element. The first transistor includes a control terminal for receiving the light-emitting control signal to determine the pulse width of the driving current. The control terminal of the driving transistor and the first terminal of the first transistor are coupled to the second node, and the second terminal of the first transistor is coupled to the third node. The reset circuit is used to reset the voltages of the first node, the second node and the third node. The compensation circuit is coupled to the first node, the second node and the third node, and is used for storing the threshold voltage of the driving transistor detected by the compensation circuit at the first node.

The present disclosure provides a display panel including a plurality of pixel circuits, a display driving circuit and one or more shift registers. The driving display is used for providing a plurality of data signals to a plurality of pixel circuits. One or more shift registers are used to provide a plurality of control signals to each pixel circuit. Each pixel circuit includes a light-emitting element, a driving transistor, a first transistor, a reset circuit and a compensation circuit. The driving transistor is used for providing the driving current to the light-emitting element through the first node, and the first end of the driving transistor is directly coupled to the light-emitting element. The first transistor includes a control terminal for receiving the light-emitting control signal among the plurality of control signals to determine the pulse width of the driving current. The control terminal of the driving transistor and the first terminal of the first transistor are coupled to the second node, and the second terminal of the first transistor is coupled to the third node. The reset circuit is used to reset the voltages of the first node, the second node and the third node. The compensation circuit is coupled to the first node, the second node and the third node, and is used for storing the threshold voltage of the driving transistor detected by the compensation circuit at the first node.

One of the advantages of the above embodiments is that even if pixel circuits at different positions have different threshold voltages, these pixel circuits still generate the same brightness for the same data voltage, so that the display panel can generate uniform images.

One of the advantages of the above embodiments is that a stable and controllable picture can be provided.

The embodiments of the present disclosure will be described below in conjunction with the relevant drawings. In the drawings, the same reference numbers refer to the same or similar elements or method flows.

FIG. 1 is a functional block diagram of a pixel circuit 100 according to an embodiment of the present disclosure. The pixel circuit 100 includes a first transistor T1 , a driving transistor 110 , a reset circuit 120 , a compensation circuit 130 and a light-emitting element 140 . One end of the reset circuit 120 is coupled to the positive end of the light-emitting element 140 and the first end of the driving transistor 110 through the first node N1, and the other end of the reset circuit 120 is coupled to the driving transistor 110 through the second node N2 and the first end of the first transistor T1, wherein the second end of the first transistor T1 is coupled to the other end of the reset circuit 120 through the third node N3. The second terminal of the driving transistor 110 is used for receiving the first operating voltage VDD, and the negative terminal of the light emitting element 140 is used for receiving the third operating voltage VSS. One end of the compensation circuit 130 is coupled to the first end of the first transistor T1 through the second node N2, and the other end of the compensation circuit 130 is coupled to the second end of the first transistor T1 through the third node N3.

The reset circuit 120 includes a second transistor T2, a third transistor T3 and a fourth transistor T4, wherein the second transistor T2, the third transistor T3 and the fourth transistor T4 respectively include a first terminal and a second terminal and control side. The first end of the second transistor T2 is used for receiving the first working voltage VDD. The second end of the second transistor T2 is coupled to the third node N3. The first end of the third transistor T3 is used for receiving the second operating voltage VSSL, and the second end of the third transistor T3 is coupled to the second node N2. The first end of the fourth transistor T4 is used for receiving the second operating voltage VSSL, and the second end of the fourth transistor T4 is coupled to the first node N1. The control terminals of each transistor T2, T3 and T4 in the reset circuit 120 are used for receiving the reset signal VRST.

The compensation circuit 130 is used for storing the detected threshold voltage of the driving transistor 110 at the first node N1, and includes a fifth transistor T5, a sixth transistor T6 and a first capacitor C1, wherein the fifth transistor T5 and the The sixth transistors T6 each include a first terminal, a second terminal and a control terminal. The first end of the fifth transistor T5 is used for receiving the reference voltage VREF, and the second end of the fifth transistor T5 is coupled to the second node N2. The first end of the sixth transistor T6 is used for receiving the data signal VDATA, and the second end of the sixth transistor T6 is coupled to the third node N3. The first capacitor C1 is coupled between the second node N2 and the third node N3. In some embodiments, the capacitance value of the first capacitor C1 is much larger than the control terminal capacitance of the driving transistor 110 . The control terminals of each transistor T5 and T6 in the compensation circuit 130 are used for connecting the scan signal VSCAN.

The light emitting element 140 includes a positive terminal and a negative terminal. The positive terminal is directly coupled to the driving transistor 110 for receiving the driving current from the driving transistor 110 . The negative terminal is used for receiving the third working voltage VSS. In some embodiments, the light emitting element 140 may be implemented by a sub-millimeter light emitting diode (mini LED) or a micro light emitting diode (micro LED).

In some embodiments, the transistors in the pixel circuit 100 are all N-type transistors, such as N-type indium gallium zinc oxide thin film transistors (IGZO TFTs).

FIG. 2 is a simplified waveform diagram of the scan signal VSCAN, the lighting control signal VEM and the reset signal VRST of the pixel circuit 100 . As shown in FIG. 2, by changing the control signal waveform input to the pixel circuit 100, the pixel circuit 100 can be operated in different stages, such as the reset stage, the compensation and data input stage, and the light-emitting stage. The reset phase, the compensation and data input phase, and the light-emitting phase constitute one operation period of the pixel circuit 100 equal to one frame time.

Please refer to Figure 2 and Figure 3 at the same time, in the reset stage, the reset signal VRST rises to a high logic level, such as a high voltage level VGH enough to turn on the N-type transistor, while the scan signal VSCAN and the light-emitting control signal VEM drops to a low logic level, such as VGL, a low voltage level sufficient to turn off the N-type transistor. At this time, the reset signal VRST of the high logic level turns on the second transistor T2, the third transistor T3 and the fourth transistor T4, and the scan signal VSCAN and the light-emitting control signal VEM of the low logic level make the first transistor T2, the third transistor T3 and the fourth transistor T4 turned on. The crystal T1, the fifth transistor T5, and the sixth transistor T6 are turned off. Therefore, the reset circuit 120 transfers the first operating voltage VDD to the third node N3, and transfers the second operating voltage VSSL to the first node N1 and the second node N2, so that the driving transistor 110 and the light emitting element 140 are turned off .

《公式1》

《公式2》 Please refer to Figures 2 and 4 at the same time. During the compensation and data input stages, the reset signal VRST is switched to a low logic level, the scan signal VSCAN is switched to a high logic level, and the lighting control signal VEM is kept at a logic low level level. At this time, the high logic level scan signal VSCAN turns on the fifth transistor T5 and the sixth transistor T6, and the low logic level reset signal VRST and the lighting control signal VEM turn on the first transistor T1, the second transistor T1 and the second transistor T6. The crystal T2, the third transistor T3 and the fourth transistor T4 are turned off. Therefore, the compensation circuit 130 transfers the reference voltage VREF to the second node N2 and transfers the data signal VDATA to the third node N3. In some embodiments, the following conditions must be satisfied in this stage: the reference voltage VREF minus the threshold voltage of the driving transistor 110 must be less than the third operating voltage VSS plus the threshold voltage of the light-emitting element 140, such as "Equation 1", in order to emit light The element 140 is kept off during the compensation and data input stages, wherein the symbol “VDTH” represents the threshold voltage of the driving transistor 110 , and the symbol “VLEDTH” represents the threshold voltage of the light-emitting element 140 . The driving transistor 110 starts to charge the first node N1 until the voltage value of the first node N1 is the reference voltage VREF minus the threshold voltage of the driving transistor 110 . At this time, the cross voltage of the first capacitor C1 is shown in "Formula 2", wherein the symbol "V31" represents the cross voltage of the first capacitor C1.

"Formula 1"

"Formula 2"

《公式3》 Please refer to FIG. 2 and FIG. 5 at the same time. During the light-emitting phase, the scan signal VSCAN is switched to a low logic level, the light-emitting control signal VEM is switched to a high logic level, and the reset signal VRST is kept at a low logic level. At this time, the light-emitting control signal VEM at a high logic level turns on the first transistor T1, and the reset signal VRST and the scan signal VSCAN at a low logic level enable the second transistor T2, the third transistor T3, and the fourth transistor T1. The crystal T4, the fifth transistor T5 and the sixth transistor T6 are turned off. Therefore, the driving transistor 110 and the light-emitting element 140 are turned on, and the voltage value of the first node N1 is the third operating voltage VSS plus the cross-voltage when the light-emitting element 140 is turned on. At this time, since the first capacitor C1 is in a floating state, its capacitor voltage across the capacitor is still as shown in "Formula 2", so the voltage value of the third node N3 is the voltage across the voltage V31 plus the third operating voltage VSS plus the light-emitting element 140 cross-voltage at turn-on. And, at this time, the voltage value of the second node N2 is equal to the voltage value V3 of the third node N3. At this time, the driving current Id generated by the driving transistor 110 can be represented by "Formula 3".

"Formula 3"

In some embodiments, the symbol "V21" of "Formula 3" is the voltage difference between the control terminal and the first terminal of the driving transistor 110 (that is, the voltage difference between the second node N2 and the first node N1); the symbol "K" ” is the conductance parameter. It can be known from "Formula 3" that the driving current Id is related to the input data signal VDATA and the reference voltage VREF, and is almost independent of the threshold voltage of the driving transistor 110 . Therefore, when the pixel circuit 100 is applied to a display panel 700 (such as the display panel 700 in FIG. 7 described later), even if the driving transistors 110 of different pixel circuits 100 have different threshold voltages, these pixel circuits 100 are The same data signal VDATA still generates the same brightness, so that the display panel 700 can generate a uniform image.

In addition, it can be seen from the above that the on-time of the first transistor T1 determines the on-time of the light-emitting element 140 because the first transistor T1 receives the light-emitting control signal VEM through its control terminal. In some embodiments, the on-time of the light-emitting element 140 can be increased/decreased by increasing/decreasing the pulse width of the light-emitting control signal VEM, thereby increasing/decreasing the maximum value of the display device (such as the display panel 700 in FIG. 7 ). brightness.

In addition, since there are no other transistors except the driving transistor 110 on the current path of the driving current Id, the parasitic resistance on the current path is greatly reduced, so that even if the driving transistor 110 generates a large driving current Id, the driving current The Id also does not cause a voltage drop across the drive transistor 110 that could take the drive transistor 110 out of saturation.

The pixel circuit 600 of FIG. 6A is similar to that of FIG. 1, except that the positive terminal of the light-emitting element 140 of the pixel circuit 600 of FIG. 6A is used to receive the first operating voltage VDD, and the negative terminal is coupled to the first node N1 ; The first end of the second transistor T2 in the reset circuit 120 is used to receive the third working voltage VSS, and the first ends of the third transistor T3 and the fourth transistor T4 are used to receive the fourth working voltage VDDH; and drive The second terminal of the transistor 110 is used for receiving the third working voltage VSS. The operating cycle of the pixel circuit 600 has three stages, namely, a reset stage, a compensation and data input stage, and a light-emitting stage, as shown in FIG. 1 .

FIG. 6B is a simplified waveform diagram of the scan signal VSCAN, the lighting control signal VEM and the reset signal VRST of the pixel circuit 600. By changing the waveform of the control signal input to the pixel circuit 600, the pixel circuit 600 can be operated in different stages , such as Reset Phase, Compensation and Data Entry Phase, and Lighting Phase. The difference between Fig. 2 and Fig. 6B is that the corresponding signals have inverted waveforms. In some embodiments, the transistors in the pixel circuit 600 are all P-type transistors, such as P-type low temperature polysilicon thin film transistors (LTPS TFTs). Therefore, it can be seen from the foregoing that the operation of the pixel circuit 600 is similar to the operation of the pixel circuit 100 described above, and details are not repeated here.

FIG. 7 is a simplified functional block diagram of a display panel 700 according to an embodiment of the present disclosure. The display panel 700 includes a shift register 710 , a display driving circuit 720 and a plurality of pixel circuits 730 , wherein the plurality of pixel circuits 730 can be implemented by the aforementioned pixel circuits 100 or 600 . The display driving circuit 720 is used for providing a plurality of data voltages to a plurality of pixel circuits 730 through a plurality of data lines DSL_1 -DSL_n. For example, each pixel circuit 730 can receive the aforementioned data signal VDATA from the display driving circuit 720 .

In one embodiment, the display driving circuit 720 may be implemented by a display driver IC (DDIC for short), and the display driving circuit 720 is used for providing a plurality of clock signals to the shift register 710 . In another embodiment, the display driving circuit 720 can also be implemented as a combination of different circuit blocks, such as a combination of a timing controller and a source driver.

In some embodiments, the shift register 710 is used to provide a plurality of control signals to a plurality of pixel circuits 730 through a plurality of scan lines SL_1 ˜SL_n. For example, each pixel circuit 730 receives the aforementioned scan signal VSCAN, the lighting control signal VEM and the reset signal VRST from the shift register 710 .

The display panel 700 is not limited to include one shift register 710 . In some embodiments, the display panel 700 may include one or more shift registers 710 according to actual design requirements, and the scan signal VSCAN, the reset signal VRST and the lighting control signal VEM may be derived from one or more shift registers different in scratchpad 710.

Certain terms are used in the specification and claims to refer to particular elements. However, those of ordinary skill in the art should understand that the same elements may be referred to by different nouns. The description and the scope of the patent application do not use the difference in name as a way of distinguishing elements, but use the difference in function of the elements as a basis for distinguishing. The "comprising" mentioned in the description and the scope of the patent application is an open-ended term, so it should be interpreted as "including but not limited to". In addition, "coupled" herein includes any direct and indirect means of connection. Therefore, if it is described in the text that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection such as wireless transmission or optical transmission, or through other elements or connections. The means are indirectly electrically or signally connected to the second element.

As used herein, the description "and/or" includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any term in the singular also includes the meaning in the plural.

The above are only preferred embodiments of the present disclosure, and all equivalent changes and modifications made according to the claims of the present disclosure shall fall within the scope of the present disclosure.

100,600: pixel circuit 110: drive transistor 120: reset circuit 130: Compensation circuit 140: Light-emitting element C1: first capacitor T1: first transistor T2: Second transistor T3: The third transistor T4: Fourth transistor T5: Fifth transistor T6: sixth transistor VDD: the first working voltage VSSL: Second working voltage VSS: the third working voltage VDDH: Fourth working voltage VREF: reference voltage VDATA: data signal VRST: reset signal VSCAN: scan signal VEM: Luminous control signal VGH: high voltage level VGL: low voltage level N1: the first node N2: second node N3: The third node 700: Display panel 710: Shift register 720: Display driver circuit 730: Pixel circuit SL_1~SL_n: scan lines DSL_1~DSL_n: data line

FIG. 1 is a functional block diagram of a pixel circuit according to an embodiment of the present disclosure. FIG. 2 is a simplified waveform diagram of the control signal voltage of the pixel circuit of FIG. 1 . FIG. 3 is a schematic diagram of an equivalent circuit operation of the pixel circuit of FIG. 1 in a reset stage. FIG. 4 is a schematic diagram of the equivalent circuit operation of the pixel circuit of FIG. 1 in the compensation and writing stages. FIG. 5 is a schematic diagram of the equivalent circuit operation of the pixel circuit of FIG. 1 in the light-emitting stage. FIG. 6A is a functional block diagram of a pixel circuit according to an embodiment of the present disclosure. FIG. 6B is a simplified waveform diagram of the control signal voltage of the pixel circuit of FIG. 6A. FIG. 7 is a simplified functional block diagram of a display according to an embodiment of the present disclosure.

100: pixel circuit

110: drive transistor

120: reset circuit

130: Compensation circuit

140: Light-emitting element

C1: first capacitor

T1: first transistor

T2: Second transistor

T3: The third transistor

T4: Fourth transistor

T5: Fifth transistor

T6: sixth transistor

VDD: the first working voltage

VSSL: Second working voltage

VSS: the third working voltage

VREF: reference voltage

VDATA: data signal

VRST: reset signal

VSCAN: scan signal

VEM: Luminous control signal

N1: the first node

N2: second node

N3: The third node

Claims (10)

A self-compensating pixel circuit, including: a light-emitting element; a driving transistor for providing a driving current to the light-emitting element through a first node, wherein a first end of the driving transistor is directly coupled to the light-emitting element; a first transistor including a control terminal for receiving a light-emitting control signal to determine a turn-on time of the light-emitting element, wherein a control terminal of the driving transistor is coupled to a first terminal of the first transistor at a second node, a second end of the first transistor is coupled to a third node; a reset circuit for resetting the voltages of the first node, the second node and the third node; and A compensation circuit, coupled to the first node, the second node and the third node, is used for storing a threshold voltage of the driving transistor detected by the compensation circuit in the first node. The pixel circuit of claim 1, wherein the reset circuit comprises: a second transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor is used for receiving a first operating voltage, the second terminal of the second transistor The terminal is coupled to the third node, and the control terminal of the second transistor is used for receiving a reset signal; a third transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is used to receive a second operating voltage, the second terminal of the third transistor The terminal is coupled to the second node, and the control terminal of the third transistor is used for receiving the reset signal; and a fourth transistor including a first end, a second end and a control end, wherein the first end of the fourth transistor is used to receive the second working voltage, the second end of the fourth transistor The terminal is coupled to the first node, and the control terminal of the fourth transistor is used for receiving the reset signal. The pixel circuit of claim 2, wherein the compensation circuit comprises: A fifth transistor includes a first end, a second end and a control end, wherein the first end of the fifth transistor is used to receive a reference voltage, and the second end of the fifth transistor is coupled to connected to the second node, the control end of the fifth transistor is used for receiving a scanning signal; A sixth transistor includes a first end, a second end and a control end, wherein the first end of the sixth transistor is used for receiving a data signal, and the second end of the sixth transistor is coupled to connected to the third node, the control end of the sixth transistor is used for receiving the scan signal; and A first capacitor is coupled between the second node and the third node. The pixel circuit of claim 1, wherein the light-emitting element comprises: a positive terminal, directly coupled to the driving transistor, for receiving the driving current from the driving transistor; a negative terminal for receiving a third working voltage. The pixel circuit of claim 1, wherein the light-emitting element comprises: a positive terminal for receiving a first working voltage; A negative terminal is directly coupled to the driving transistor for receiving the driving current from the driving transistor. A display panel comprising: Multiple pixel circuits; a display driving circuit for providing a plurality of data signals to the plurality of pixel circuits; and One or more shift registers for providing a plurality of control signals to each pixel circuit, wherein each pixel circuit includes: a light-emitting element; a driving transistor for providing a driving current to the light-emitting element through a first node, wherein a first end of the driving transistor is directly coupled to the light-emitting element; a first transistor including a control terminal for receiving a light-emitting control signal among the plurality of control signals to determine an on-time of the light-emitting element, wherein a control terminal of the driving transistor and the first transistor A first end of the first transistor is coupled to a second node, and a second end of the first transistor is coupled to a third node; a reset circuit for resetting the voltages of the first node, the second node and the third node; and A compensation circuit, coupled to the first node, the second node and the third node, is used for storing a threshold voltage of the driving transistor detected by the compensation circuit in the first node. The display panel of claim 6, wherein the reset circuit comprises: a second transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor is used for receiving a first operating voltage, the second terminal of the second transistor The terminal is coupled to the third node, and the control terminal of the second transistor is used for receiving a reset signal among the plurality of control signals; a third transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is used to receive a second operating voltage, the second terminal of the third transistor The terminal is coupled to the second node, and the control terminal of the third transistor is used for receiving the reset signal; and a fourth transistor including a first end, a second end and a control end, wherein the first end of the fourth transistor is used to receive the second working voltage, the second end of the fourth transistor The terminal is coupled to the first node, and the control terminal of the fourth transistor is used for receiving the reset signal. The display panel of claim 7, wherein the compensation circuit comprises: A fifth transistor includes a first end, a second end and a control end, wherein the first end of the fifth transistor is used to receive a reference voltage, and the second end of the fifth transistor is coupled to connected to the second node, the control end of the fifth transistor is used for receiving a scan signal among the plurality of control signals; a sixth transistor including a first end, a second end and a control end, wherein the first end of the sixth transistor is used for receiving one of the plurality of data signals, the sixth transistor The second end of the transistor is coupled to the third node, and the control end of the sixth transistor is used to receive the scan signal; and A first capacitor is coupled between the second node and the third node. The display panel according to claim 6, wherein the light-emitting element comprises: a positive terminal, directly coupled to the driving transistor, for receiving the driving current from the driving transistor; a negative terminal for receiving a third working voltage. The display panel according to claim 6, wherein the light-emitting element comprises: a positive terminal for receiving a first working voltage; A negative terminal is directly coupled to the driving transistor for receiving the driving current from the driving transistor.

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