TWI765238B - Design method for printed circuit board - Google Patents

Abstract

A design method for printed circuit board includes: receiving a plurality of circuitry information, analyzing the plurality of circuitry information to respectively generate a plurality of layout information; analyzing the plurality of layout information a universal layout footprint which is compatible to all of the plurality of layout information; based on the universal layout footprint, generating a plurality of stencils according to the plurality of layout information; disposing at least one electronic component on the universal layout footprint according to any one of the plurality of stencils.

Description

Design method of printed circuit board

The present invention relates to a design method of a printed circuit board, and in particular, to a layout design method of a multifunctional printed circuit board.

In today's electronic products, in order to realize multiple functions on a printed circuit board, different footprint layouts are often required for circuits with different functions, so a certain size of circuit board area needs to be consumed.

With the size requirements of electronic devices, it has become an important issue for engineers to design a printed circuit board so that the electronic device can provide multiple functions without adding electronic components in a limited space.

The invention provides a design method of a printed circuit board, which can complete the design of a circuit board that can provide multi-functions without increasing the size of the circuit and the number of parts.

The design method of the printed circuit board of the present invention includes: receiving a plurality of circuit information, analyzing the circuit information and generating a plurality of layout information respectively; analyzing the layout information to generate a general layout footprint compatible with the layout information; based on the general layout footprint, according to the layout information A plurality of stencils are generated respectively; at least one electronic component is arranged on the general layout footprint according to any one of the stencils.

In an embodiment of the present invention, each of the above-mentioned steel meshes includes a plurality of welding pad openings.

In an embodiment of the present invention, the above-mentioned pad openings respectively correspond to at least partial regions of the plurality of pads on the general layout footprint.

In an embodiment of the present invention, the above-mentioned circuit information corresponds to a plurality of circuit blocks respectively, and the circuit blocks are arranged on the same circuit board or different circuit boards.

In an embodiment of the present invention, the above-mentioned at least one electronic element is at least one of a resistor, a capacitor, and an inductor.

In an embodiment of the present invention, the above-mentioned step of analyzing the layout information to generate a general layout footprint consistent with the layout information includes: analyzing at least one common connection point and at least one non-common connection point of the layout information; and, for at least one common connection point and at least one non-common connection point. A common connection point and at least one non-common connection point are respectively provided with a plurality of pads to generate a common layout footprint.

In an embodiment of the present invention, the above-mentioned step of respectively generating stencils according to the layout information based on the general layout footprint includes: analyzing the first layout information to obtain at least one common connection point and at least one first common connection point of the first layout information a plurality of first solder pads corresponding to non-common connection points; and generating a first stencil corresponding to the first layout information according to the position and size of the first solder pads.

In an embodiment of the present invention, the step of analyzing the layout information to generate the general layout footprint of the compatible layout information includes: analyzing at least one common electronic component and at least one non-sharing electronic component in the layout information; according to at least one Common electronic components and at least one non-shared electronic component are used to generate integrated layout information; and a plurality of pads are respectively set for a plurality of connection points of the integrated layout information to generate a common layout footprint.

In an embodiment of the present invention, the method for designing a printed circuit board further includes: short-circuiting two ends of a resistor in a corresponding circuit through at least one electronic component.

In an embodiment of the present invention, the above-mentioned at least one electronic component is disposed on the general layout footprint through surface mount soldering technology.

Based on the above, the present invention enables a plurality of different circuits to be laid out through the same general layout footprint, and then performs the configuration of electronic components through different stencils generated corresponding to different circuit information. In this way, the layout complexity of various circuits with different functions can be simplified, and the layout of the multi-function circuits can be completed without increasing the size of the circuit board.

Please refer to FIG. 1 . FIG. 1 is a flowchart illustrating a method for designing a printed circuit board according to an embodiment of the present invention. Wherein, in step S110, a plurality of circuit information is received, and the received circuit information is analyzed to generate a plurality of layout information respectively. Next, in step S120, the layout information generated in step S110 is analyzed to generate a general layout footprint compatible with the above-mentioned multiple layout information. And, in step S130, based on the general layout footprint, a plurality of stencils are respectively generated according to the plurality of layout information. Finally, in step S140, at least one electronic component is arranged on the general layout footprint according to any one of the above-mentioned plurality of stencils, so as to realize the circuit of the body.

Incidentally, the above steps in this embodiment can be implemented by executing an application program through a processor with computing capability.

For the implementation details of the above steps, please refer to FIG. 1 and FIG. 2A to FIG. 2E synchronously below, wherein FIG. 2A to FIG. In FIG. 2A , circuits 210 and 220 are coupled to control circuit 230 . The circuits 210 and 220 and the control circuit 230 may be co-located on the same circuit board. The circuit 210 includes a resistor R1 and a capacitor C1, wherein the capacitor C1 is coupled between the voltage terminal V1 and the ground terminal G. The resistor R1 is coupled between the voltage terminal V3 and the voltage terminal V1. In addition, the circuit 220 includes a resistor R2 and a capacitor C2, wherein the capacitor C2 is coupled between the voltage terminal V2 and the ground terminal G. The resistor R2 is coupled between the voltage terminal V3 and the voltage terminal V2.

In step S110, the circuit information of the circuits 210 and 220 can be analyzed, and the layout information 210A and 220A as shown in FIG. 2B are generated. The layout information 210A and 220A correspond to the circuits 210 and 220, respectively. Next, step 120 analyzes the layout information 210A and 220A. First, the ground terminal G and the voltage terminal V3 included in the layout information 210A also appear in the layout information 220A. Therefore, it can be recognized that the ground terminal G and the voltage terminal V3 are the common connection points of the layout information 210A and 220A. In addition, another voltage terminal V1 in the layout information 210A does not exist in the layout information 220A, and another voltage terminal V2 in the layout information 220A does not exist in the layout information 210A. Therefore, the voltage terminals V1, V2 can be identified as non-common connection points.

When generating a general layout footprint, multiple pads can be set for the above-mentioned common connection points (the ground terminal G and the voltage terminal V3) and the non-common connection points (the voltage terminal V1 and the voltage terminal V2). 2C's Universal Layout Footprint 200. The general layout footprint 200 has four pads PD1 ˜ PD4 , and the pads PD1 ˜ PD4 correspond to the voltage terminal V1 , the voltage terminal V2 , the voltage terminal V3 and the ground terminal G respectively.

Next, in step S130 , based on the general layout footprint 200 and according to the layout information 210A of the circuit 210 , a stencil ST1 corresponding to the circuit 210 can be generated. Wherein, the distribution range of the steel mesh ST1 can cover the pads PD1, PD3 and PD4. The steel mesh ST1 has a plurality of pad openings PO11-PO13. The pad openings PO11-PO13 correspond to the pads PD1, PD3, and PD4, respectively, and are used to expose part or all of the pads PD1, PD3, and PD4. In addition, in step S130 , the stencil ST2 corresponding to the circuit 220 may be generated based on the general layout footprint 200 and according to the layout information 220A of the circuit 220 . Wherein, the distribution range of the steel mesh ST2 can cover the pads PD1, PD3 and PD4. The stencil ST2 has a plurality of pad openings PO11-PO13, the pad openings PO21-PO23 correspond to the pads PD3, PD2 and PD4 respectively, and are used to expose part or all of the pads PD3, PD2 and PD4.

Next, step S140 is used to generate a physical circuit on the circuit board. Corresponding to the circuit 210 , according to the stencil ST1 , solder paste may be provided on the exposed pads PD1 , PD3 and PD4 , and a capacitive element may be provided between the pads PD1 , PD3 and PD4 . The first end of the capacitive element is coupled to the pads PD1 and PD3 at the same time, and the second end of the capacitive element is coupled to the pad PD4. After the capacitive elements are arranged on the pads PD1 , PD3 and PD4 , the pads PD1 and PD3 can be short-circuited with each other to form a resistor R1 with a zero resistance value in the circuit 210 , and the capacitive element acts as a capacitor in the circuit 210 C1.

Corresponding to the circuit 220, according to the stencil ST2, solder paste may be provided on the exposed pads PD3, PD2 and PD4, and a capacitive element may be provided between the pads PD3, PD2 and PD4. Wherein, the first end of the capacitive element is coupled to the pads PD3 and PD2 at the same time, and the second end of the capacitive element is coupled to the pad PD4. After the capacitive elements are arranged on the pads PD3, PD2 and PD4, the pads PD3 and PD2 can be short-circuited with each other, and a resistor R2 with a zero resistance value in the circuit 220 is formed, and the capacitive element acts as a capacitor in the circuit 210. C2.

In this embodiment, the capacitive element can be configured on the general layout footprint 200 through Surface Mount Technology (SMT).

Please refer to FIGS. 3A to 3D below. FIGS. 3A to 3D are schematic diagrams illustrating another implementation manner of a method for designing a printed circuit board according to an embodiment of the invention. In FIG. 3A , the circuits 310 and 320 may be respectively arranged on different circuit boards, or may also be arranged on the same circuit board. The circuits 310 and 320 are respectively coupled to the linear voltage regulator 311 and the PWM signal generator 321 . The linear voltage regulator 311 may be a low dropout (low dropout, LDO) voltage regulator (voltage regulator).

Through the analysis circuits 310 and 320, the capacitor C1 in the circuit 310 is coupled between the output terminal O1 and the ground terminal G1. In the circuit 320, the inductor L1 is coupled between the terminal L and the output terminal O2, the resistor R1 is coupled between the terminal F and the output terminal O2, and the capacitor C2 is coupled between the output terminal O2 and the ground terminal G2.

By analyzing the layout information of the circuits 310 and 320 , the output terminals O1 and 320 in the circuit 310 can be set as the common connection point (output terminal O), and the ground terminal G1 in the circuit 310 and the ground terminal G1 in the circuit 320 can be set. The ground terminal G2 is another common connection point (the ground terminal G). The circuit 320 also has a non-common connection point of the terminals L and F. Next, in FIG. 3B , the pads PD1 and PD2 are respectively set for the common connection point (the output terminal O and the ground terminal G), and the pads PD3 and PD4 are respectively set for the terminals L and F that are not the common connection point. And thereby generate the general layout footprint 300 .

In FIG. 3B , corresponding to the circuit 310 , the present embodiment can generate a stencil ST1 that can cover the pads PD1 , PD2 and PD3 . The stencil ST1 may have pad openings to expose PD1 , PD2 and PD3 respectively. When generating an actual hardware circuit, the capacitive element can be attached to the pads PD1 , PD2 and PD3 to realize the capacitor C1 in the circuit 310 . It is worth mentioning that the terminal L1 does not appear in the circuit 310, but when the size of the capacitor element is too large, the bonding pad PD3 can be covered by the steel mesh ST1 to increase the stability of the capacitor element when it is attached.

Corresponding to the circuit 320, the present embodiment can generate a stencil ST2 including two partial stencils ST21, ST22. Part of the stencil ST21 can cover part of the pad PD1, part of the pad PD3 and all the pads PD4, and part of the stencil ST22 can cover part of the pad PD1 and part of the pad PD2. Here, the dimensions of some of the steel meshes ST21 and ST22 can be designed according to the corresponding electronic components to be attached, and there is no certain limitation. Based on the set sizes of the partial stencils ST21 and ST22, each part of the stencils ST21 and ST22 can choose to cover part of the pads or all of the pads for each pad to be covered, and there is no fixed limit. .

When generating an actual hardware circuit, through part of the steel mesh ST21, the first end of the inductance element can be attached to the pad PD4 and pad PD1, and the second end of the inductance element can be attached to the pad PD3, and the circuit can be realized Inductor L1 in 320 (coupled between terminal L and output terminal O2). It is worth mentioning that the first end of the inductance element can be attached to the pad PD4 and the pad PD1, so that the pad PD4 and the pad PD1 can be short-circuited to each other, and a resistor R1 (coupled) with a zero resistance value in the circuit 320 is generated. connected between terminal F and output terminal O2).

In addition, through part of the steel mesh ST22 , the first end of the capacitive element can be attached to the pad PD4 and the pad PD1 , and the second end of the capacitive element can be attached to the pad PD2 to realize the capacitor C2 in the circuit 320 .

Please refer to FIGS. 4A to 4E below. FIGS. 4A to 4E are schematic diagrams illustrating still another implementation manner of a method for designing a printed circuit board according to an embodiment of the present invention. In FIG. 4A , the circuit 410 is connected between the amplifiers OP1 ˜ OP2 , and has a resistor R1 and a capacitor C1 , wherein the resistor R1 is connected in series between the amplifiers OP1 ˜ OP2 , and the capacitor C1 is coupled to the phase coupling end of the resistor R1 and the amplifier OP2 between the point and the ground terminal G. The circuit 420 is connected between the amplifiers OP3-OP4, and has a resistor R2 and a capacitor C1, wherein the resistor R2 is connected in series between the amplifiers OP3-OP4, and the capacitor C1 is coupled to the phase-coupling terminal of the resistor R1 and the amplifier OP1 and the ground terminal G between. The circuit 430 is coupled between the amplifiers OP5-OP6. The circuit 430 only has a resistor R3 connected in series between the amplifiers OP5 ˜ OP6 .

Here, by analyzing the circuits 410 to 430 , it can be known that the circuits 410 to 430 have a common circuit element (capacitor C1 ) and non-common circuit elements (resistors R1 , R2 ). The resistor R3 can be equivalent to the series connection of the resistors R1 and R2. According to the analyzed common circuit elements (capacitor C1 ) and non-common circuit elements (resistors R1 , R2 ), an integrated circuit layout can be generated for the circuits 410 to 430 , and the integrated layout information 400 shown in FIG. 4B is generated.

By analyzing the integrated layout information 400, a plurality of connection points such as the voltage terminals V1, V2, the ground terminal G, and the output terminal O can be obtained. Then, solder pads are respectively arranged for the above-mentioned multiple connection points, so that a general layout footprint can be generated. 4C , the pads PD1 to PD4 correspond to the voltage terminal V1 , the output terminal O, the voltage terminal V2 and the ground terminal G, respectively.

In FIG. 4C , corresponding to the circuit 410 , partial stencils ST11 and ST12 can be generated. Among them, part of the stencil ST11 covers part of the pads PD2, part of the pads PD4, and all of the pads PD1. Part of the stencil ST12 covers part of the pads PD2, part of the pads PD4, and all of the pads PD3. Part of the steel mesh ST11 is used to correspond to the sticking action of the capacitive element, and realize the capacitor C1 in the circuit 410 . Part of the steel mesh ST12 is used to correspond to the bonding action of the resistance element, and realize the resistance R1 in the circuit 410 .

In FIG. 4D, corresponding to the circuit 420, part of the stencils ST21 and ST22 can be generated. Among them, part of the stencil ST21 covers part of the pads PD2, part of the pads PD4, and all of the pads PD1. Part of the stencil ST22 covers part of the pads PD2, part of the pads PD4, and all of the pads PD3. Part of the steel mesh ST21 is used to correspond to the bonding action of the resistance element, and realize the resistance R2 in the circuit 420 . Part of the steel mesh ST22 is used to correspond to the sticking action of the capacitive element, and realize the capacitor C1 in the circuit 420 .

In FIG. 4E, corresponding to the circuit 430, the steel mesh ST3 can be generated. The steel mesh ST3 covers part of the pads PD1, part of the pads PD3, and all the pads PD2. The stencil ST3 can be used to correspond to the bonding action of the bypass element, and short-circuit the pads PD1 , PD2 , and PD3 to each other, thereby forming the resistor R3 in the circuit 430 . The resistor R3 is a zero-resistance resistor, or can also be a non-zero-resistance resistor.

Please refer to FIG. 5 . FIG. 5 is a flowchart illustrating the design and production of a printed circuit board according to an embodiment of the present invention. In FIG. 5, the basic requirements of the product are received in step S510, and based on the basic requirements of the product, in step S520, the multiple functions of the product are taken into consideration in the design as much as possible. In step S530, various requirements are analyzed, and in step S540 various basic component circuits corresponding to various requirements are generated.

In step S550, analysis is performed according to various basic component circuits, and a general layout footprint compatible with various basic component circuits is drawn. Steps S561 to S56N can be performed in parallel, and the solder paste layer 1 to the solder paste layer N corresponding to different basic component circuits are drawn respectively; the steps S571 to S57N are respectively produced from the stencil 1 to the stencil N; the steps S581 to S58N are respectively Product 1 to Product N are produced.

In summary, the present invention generates a common layout footprint that is compatible with all circuits by integrating multiple circuits. A variety of stencils are generated corresponding to multiple circuits. In this way, the design of the printed double circuit board with the multi-function circuit can be completed without increasing the layout area, and the work efficiency of the circuit board can be improved.

200: Universal Layout Footprint 210, 220, 310, 320, 410, 420, 430: Circuits 210A, 220A: Layout information 230: Control circuit 311: Linear Voltage Regulator 321: PWM signal generator OP1~OP6: Amplifier C1, C2: Capacitor G, G1, G2: ground terminal L, F: endpoints L1: Inductance O, O1, O2: output terminal PD1~PD4: pads PO11~PO13: Pad opening R1~R3: Resistance S110~S140, S510~S58N: Steps ST1~ST3: Steel mesh ST11, ST12, ST21, ST22: Partial steel mesh V1, V2, V3: voltage terminals

FIG. 1 is a flowchart illustrating a method for designing a printed circuit board according to an embodiment of the present invention. 2A to 2E are schematic diagrams illustrating an embodiment of a method for designing a printed circuit board according to an embodiment of the invention. FIGS. 3A to 3D are schematic diagrams illustrating another implementation manner of a method for designing a printed circuit board according to an embodiment of the invention. 4A to 4E are schematic diagrams illustrating still another implementation manner of a method for designing a printed circuit board according to an embodiment of the present invention. FIG. 5 is a flow chart illustrating the design and production of a printed circuit board according to an embodiment of the present invention.

S110~S140: Steps

Claims (10)

A method for designing a printed circuit board, comprising: receiving a plurality of circuit information, analyzing the circuit information and generating a plurality of layout information respectively; analyzing common information and non-shared information of the layout information to generate compatible layout information a general layout footprint of the generating a plurality of stencils respectively from the layout information; and disposing at least one electronic component on the general layout footprint according to any one of the stencils. The design method of a printed circuit board according to claim 1, wherein each of the stencils includes a plurality of solder pad openings. The method for designing a printed circuit board according to claim 2, wherein the solder pad openings respectively correspond to at least partial regions of the plurality of solder pads on the general layout footprint. The design method of a printed circuit board as claimed in claim 1, wherein the circuit information corresponds to a plurality of circuit blocks respectively, and the circuit blocks are arranged on the same circuit board or different circuit boards. The method for designing a printed circuit board according to claim 1, wherein the at least one electronic component is at least one of a resistor, a capacitor, and an inductor. The design method of a printed circuit board as claimed in claim 1, wherein the step of analyzing the layout information to generate the general layout footprint compatible with the layout information comprises: analyzing the at least one common connection point of the layout information and the at least one non-common connection point; and respectively disposing a plurality of pads for the at least one common connection point and the at least one non-common connection point to generate the general layout footprint. The method for designing a printed circuit board according to claim 6, wherein based on the general layout footprint, the step of respectively generating the stencils according to the layout information comprises: analyzing a first layout information to obtain the first layout information having a plurality of first pads corresponding to the at least one common connection point and the at least one non-common connection point; and a first stencil corresponding to the first layout information is generated according to the position and size of the first solder pads . The design method of a printed circuit board as claimed in claim 1, wherein the step of analyzing the layout information to generate the general layout footprint compatible with the layout information comprises: analyzing the at least one common electronic component in the layout information and the at least one non-shared electronic component; generating an integrated layout information according to the at least one shared electronic component and the at least one non-shared electronic component; and A plurality of pads are respectively set for the plurality of connection points of the integrated layout information to generate the general layout footprint. The method for designing a printed circuit board as claimed in claim 1, further comprising: short-circuiting two ends of a resistor in a corresponding circuit through the at least one electronic component. The design method of a printed circuit board as claimed in claim 1, wherein the at least one electronic component is disposed on the general layout footprint through surface mount soldering technology.

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