TWI763353B - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure includes a substrate, a gate, a bit line, a capping layer, a first spacer, an insulated layer, a second spacer and a spin-coating dielectric layer. The gate and the bit line is located on the substrate. The gate is located between the substrate and the bit line. The capping layer is located on the bit line. The first spacer is located on a sidewall of the gate, a sidewall of the bit line and a sidewall of the capping layer. The insulated layer is located on an upper portion of the first spacer. The second spacer is located under a bottom surface of the insulated layer and extends downwardly. The insulated layer, the first spacer and the second spacer defines an air gap. The spin-coating dielectric layer is among the first spacer, the air gap and the second spacer. The spin-coating dielectric layer is lower than a bottom surface of the bit line.

Description

Semiconductor structure and method of forming the same

The present disclosure relates to a semiconductor structure and a method for forming the semiconductor structure.

Generally speaking, air gaps are usually applied in the process of bit lines to reduce the parasitic capacitance between the two bit lines. In the conventional air gap process, the air gap is formed by removing the sacrificial layer between the first spacer and the second spacer by a wet etching or plasma cleaning process. In the conventional air gap process, the opening of the air gap is formed in the upper half of the air gap, and after the opening is formed, the opening of the air gap is closed with nitride (eg, silicon nitride). However, the structure in which the opening of the air gap is formed in the upper half of the air gap may allow nitrides closing the opening to flow into the interior of the air gap, resulting in nitrides in the air gap, resulting in a reduced effect of the air gap in reducing parasitic capacitance.

One technical aspect of the present disclosure is a semiconductor structure.

According to an embodiment of the present disclosure, a semiconductor structure includes a substrate, a gate electrode, a bit line, a capping layer, a first spacer, an insulating layer, a second spacer, and a spin-on dielectric layer. Gates and bit lines are located on the substrate. The gate is located between the substrate and the bit line. The upper cover layer is on the bit line. The first spacer is located on the gate electrode, the bit line and the sidewall of the upper capping layer. An insulating layer is on the upper portion of the first spacer. The second spacer is located on the bottom surface of the insulating layer and extends downward. The insulating layer, the first spacer and the second spacer define an air gap. A spin-on dielectric layer is located between the first spacer, the air gap, and the second spacer. The spin-on dielectric layer is below the bottom surface of the bit line.

In an embodiment of the present disclosure, the top of the air gap is higher than the top surface of the bit line.

In an embodiment of the present disclosure, the first spacer, the air gap, and the second spacer are parallel to each other in the vertical direction.

In an embodiment of the present disclosure, the substrate has an active region isolated from a shallow trench beside the active region. The active region is located under the gate electrode and the first spacer.

In an embodiment of the present disclosure, the above-mentioned semiconductor structure further includes a semiconductor layer. The semiconductor layer is on the spin-on dielectric layer, the shallow trench isolation and the active region. The semiconductor layer extends to the sidewall of the insulating layer.

One technical aspect of the present disclosure is a method for forming a semiconductor structure.

According to an embodiment of the present disclosure, a method for forming a semiconductor structure includes: forming a photoresist on a first spacer on a substrate, wherein the first spacer is located on a gate electrode, a bit line and sidewalls of an upper capping layer, and the bit The line is located between the gate and the upper cap layer; an insulating layer is formed on the top surface of the photoresist and the sidewall of the first spacer; the bottom of the insulating layer and the photoresist are etched, so that the remaining insulating layer and the photoresist are along the first spacer disposing; forming a second spacer on the photoresist; etching the bottom of the second spacer and the bottom of the photoresist to expose the bottom of the first spacer; removing the photoresist between the first spacer and the second spacer to form an air gap, wherein there is an opening between the bottom of the first spacer and the second spacer, and the opening is located under the bit line; and a spin-on dielectric layer is formed on the bottom of the first spacer, so that the spin-on dielectric The layer is located in the opening.

In one embodiment of the present disclosure, the above method further includes etching a spin-on dielectric layer outside the opening and on the bottom of the first spacer.

In an embodiment of the present disclosure, the substrate has an active region isolated from a shallow trench beside the active region. The above method further includes etching the bottom of the first spacer and its underlying shallow trench isolation and active region.

In an embodiment of the present disclosure, the above method further includes forming a semiconductor layer on the STI and the active region, wherein the semiconductor layer is on the spin-on dielectric layer.

In one embodiment of the present disclosure, the method further includes anisotropically etching the photoresist after etching the bottom of the insulating layer and the photoresist, so that the sidewalls of the photoresist are closer to the first spacers than the sidewalls of the insulating layer.

In the above-mentioned embodiments of the present disclosure, there is an air gap between the first spacer and the second spacer of the semiconductor structure, and the opening of the air gap is located below the bit line and between the bottom of the first spacer and the second spacer between. In addition, a spin-on dielectric layer of the semiconductor structure can be formed on the bottom of the first spacer such that the spin-on dielectric layer can be located in the opening under the bit line. That is to say, the design that the opening of the air gap is located under the bit line allows the spin-on dielectric layer to flow into the opening of the air gap from the bottom of the first spacer to achieve the effect of closing the opening. Compared with the conventional technology, the air gap of the semiconductor structure has no backfilled nitride, so the air gap can effectively reduce the parasitic capacitance.

The embodiments disclosed below provide many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present case. Of course, these examples are merely examples and are not intended to be limiting. In addition, reference numerals and/or letters may be repeated in various instances herein. This repetition is for brevity and clarity, and does not in itself specify the relationship between the various embodiments and/or configurations discussed.

Spatially relative terms such as "below," "below," "lower," "above," "above," and the like may be used herein for convenience of description to describe The relationship of one element or feature to another element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 is a cross-sectional view of a semiconductor structure 100 according to an embodiment of the present disclosure. Referring to FIG. 1 , the semiconductor structure 100 includes a substrate 110 , a gate electrode 120 , a bit line 130 , a capping layer 140 , a first spacer 150 a , an insulating layer 160 , a second spacer 150 b and a spin-on dielectric layer 180 . The gate electrode 120 and the bit line 130 of the semiconductor structure 100 are located on the substrate 110 . Also, the gate electrode 120 of the semiconductor structure 100 is located between the substrate 110 and the bit line 130 . In this embodiment, the gate electrode 120 of the semiconductor structure 100 may include doped polysilicon, metal, conductive metal nitride, and combinations thereof, but the disclosure is not intended to be limited. The upper capping layer 140 of the semiconductor structure 100 is located on the bit line 130 . The material of the upper capping layer 140 of the semiconductor structure 100 may include nitride (eg, silicon nitride), but is not intended to limit the present disclosure.

The first spacer 150 a of the semiconductor structure 100 is located on the sidewall 122 of the gate electrode 120 , the sidewall 132 of the bit line 130 and the sidewall 142 of the upper capping layer 140 . The insulating layer 160 of the semiconductor structure 100 is located on the upper portion of the first spacer 150a. The second spacer 150b of the semiconductor structure 100 is located on the bottom surface 162 of the insulating layer 160 and extends downward from the bottom surface 162 of the insulating layer 160 along the vertical direction D1. The bottom surface 162 of the insulating layer 160 of the semiconductor structure 100 , the first spacer 150 a and the second spacer 150 b define an air gap 170 . The spin-on dielectric layer 180 of the semiconductor structure 100 is located between the first spacer 150a, the air gap 170 and the second spacer 150b. The spin-on dielectric layer 180 of the semiconductor structure 100 is below the bottom surface 134 of the bit line 130 .

In this embodiment, the top 172 of the air gap 170 of the semiconductor structure 100 is higher than the top surface 136 of the bit line 130 of the semiconductor structure 100 , and the bottom 174 of the air gap 170 is lower than the bottom surface 134 of the bit line 130 . That is to say, the overall height of the air gap 170 of the semiconductor structure 100 is greater than the overall height of the bit line 130 of the semiconductor structure 100 , so the air gap 170 of the semiconductor structure 100 can provide a sufficient spacing effect, so that the adjacent bits of the semiconductor structure 100 Undesirable parasitic capacitances between the element lines 130 can be reduced.

Specifically, there is an air gap 170 between the first spacer 150 a and the second spacer 150 b of the semiconductor structure 100 , and the bottom 174 of the air gap 170 is located below the bottom surface 134 of the bit line 130 . In addition, the spin-on dielectric layer 180 of the semiconductor structure 100 may be formed on the bottom 152a of the first spacer 150a such that the spin-on dielectric layer 180 may be located under the bit line 130 and at the bottom end of the second spacer 150b and the bottom 152a of the first spacer 150a. That is, the design where the bottom 174 of the air gap 170 is located below the bottom surface 134 of the bit line 130 allows the spin-on dielectric layer 180 to be formed on the bottom 152a of the first spacer 150a and on the bottom 174 of the air gap 170 below, so as to achieve the effect of closing the air gap 170 . Compared with the conventional technology, the air gap 170 of the semiconductor structure 100 has no nitride backfilled therein, so the air gap 170 of the semiconductor structure 100 can effectively provide the effect of reducing parasitic capacitance.

In this embodiment, the first spacer 150a, the air gap 170 and the second spacer 150b of the semiconductor structure 100 are parallel to each other in the vertical direction D1. The substrate 110 of the semiconductor structure 100 has an active region 112 and a shallow trench isolation 114 beside the active region 112 . The active region 112 of the substrate 110 is located below the gate 120 of the semiconductor structure 100 and the first spacer 150a. The shallow trench isolation 114 of the substrate 110 may provide an insulating effect. In addition, the semiconductor structure 100 further includes a semiconductor layer 190 . The material of the semiconductor layer 190 of the semiconductor structure 100 may include polysilicon, which is not intended to limit the present disclosure. The semiconductor layer 190 of the semiconductor structure 100 is located on the spin-on dielectric layer 180 , the shallow trench isolation 114 of the substrate 110 and the active region 112 . Also, the semiconductor layer 190 of the semiconductor structure 100 extends to the sidewall 164 of the insulating layer 160 .

In the following description, a method of forming the semiconductor structure 100 will be described. The connection relationships and materials of the components already described will not be repeated, but will be described first.

FIG. 2 is a flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the present disclosure. A method of forming a semiconductor structure includes the following steps. First, in step S1, a photoresist is formed on the first spacer on the substrate, wherein the first spacer is located on the gate electrode, the bit line and the sidewall of the upper cap layer, and the bit line is located between the gate electrode and the upper cap layer . Next, in step S2, an insulating layer is formed on the top surface of the photoresist and the sidewalls of the first spacer. Then in step S3, the bottom of the insulating layer and the photoresist are etched, so that the remaining insulating layer and the photoresist are arranged along the first spacer. Subsequently in step S4, a second spacer is formed on the photoresist. Next, in step S5, the bottom of the second spacer and the bottom of the photoresist are etched to expose the bottom of the first spacer. Next, in step S6, the photoresist between the first spacer and the second spacer is removed to form an air gap, wherein there is an opening between the bottom of the first spacer and the second spacer, and the opening is located below the bit line . Then in step S7, a spin-on dielectric layer is formed on the bottom of the first spacer so that the spin-on dielectric layer is located in the opening. In the following description, each of the above steps will be explained in detail.

3 to 11 are cross-sectional views at different stages of the method of forming the semiconductor structure 100 . Referring to FIG. 3, a photoresist 200 is formed on the first spacer 150a on the substrate 110 of the semiconductor structure 100, wherein the first spacer 150a is located on the sidewall 122 of the gate electrode 120, the sidewall 132 of the bit line 130 and the upper capping layer 140 on the side wall 142. Moreover, the bit line 130 of the semiconductor structure 100 is located between the gate electrode 120 and the upper capping layer 140 . Next, an insulating layer 160 is formed on the top surface 202 of the photoresist 200 and the sidewalls 154a of the first spacers 150a. In detail, an insulating layer 160 is formed on the upper portion of the sidewall 154a of the first spacer 150a and on the top surface 202 of the photoresist 200, and the insulating layer 160 may be U-shaped.

Referring to FIG. 3 and FIG. 4 at the same time, then, the bottom of the insulating layer 160 of the semiconductor structure 100 and the photoresist 200 are etched, so that the remaining insulating layer 160 and the photoresist 200 are disposed along the first spacer 150a, and the remaining photoresist 200 A U-shape may be formed on the first spacer 150a. Please refer to FIG. 5 , the method for forming the semiconductor structure 100 further includes etching the photoresist 200 anisotropically after etching the bottom of the insulating layer 160 and the photoresist 200 so that the sidewalls 204 of the photoresist 200 are smaller than the sidewalls 164 of the insulating layer 160 close to the first spacer 150a. That is, after the anisotropic etching, the thickness of the photoresist 200 on the sidewalls 154a of the first spacers 150a is smaller than the thickness of the insulating layer 160 on the sidewalls 154a of the first spacers 150a.

Referring to FIG. 6 , next, a second spacer 150 b is formed on the photoresist 200 . The second spacers 150b are disposed along the photoresist 200, and the sidewalls 152b of the second spacers 150b and the sidewalls 164 of the insulating layer 160 are aligned with each other in the vertical direction D1. Referring to FIG. 6 and FIG. 7 simultaneously, the bottom of the second spacer 150b of the semiconductor structure 100 and the bottom of the photoresist 200 are etched to expose the bottom 152a of the first spacer 150a. In detail, when the bottom of the second spacer 150b of the semiconductor structure 100 and the bottom of the photoresist 200 are etched, the bottom 152a of the first spacer 150a can serve as an etch stop layer, so that the etching stops at the bottom of the first spacer 150a 152a.

Referring to FIGS. 7 and 8 simultaneously, then, the photoresist 200 between the first spacer 150 a of the semiconductor structure 100 and the second spacer 150 b of the semiconductor structure 100 is removed to form the air gap 170 . In addition, the semiconductor structure 100 has an opening O between the bottom 152a of the first spacer 150a and the bottom end 154b of the second spacer 150b. Opening O is located below bottom surface 134 of bit line 130 .

Referring to FIGS. 8 and 9 at the same time, next, a spin-on dielectric layer 180 is formed on the bottom 152 a of the first spacer 150 a of the semiconductor structure 100 so that the spin-on dielectric layer 180 is located in the opening O. The opening O of the air gap 170 is located below the bottom surface 134 of the bit line 130 so that the spin-on dielectric layer 180 flows from the bottom 152a of the first spacer 150a into the bottom 152a of the first spacer 150a and the second spacer 150b In the opening O between the bottom ends 154b of the air gaps 154b, the effect of closing the air gap 170 is achieved. The material of the spin-on dielectric layer 180 of the semiconductor structure 100 may include a spin-on dielectric material, but is not intended to limit the present disclosure.

Please refer to FIG. 10. Next, the method for forming the semiconductor structure 100 further includes after forming the spin-on dielectric layer 180 on the bottom 152a of the first spacer 150a, etching the spin-on dielectric layer outside the bottom 174 of the air gap 170 180, and the spin-on dielectric layer 180 on the bottom 152a of the first spacer 150a is etched. Referring to FIG. 11 , the substrate 110 of the semiconductor structure 100 has an active region 112 and a shallow trench isolation 114 beside the active region 112 . The method for forming the semiconductor structure 100 further includes etching the bottom portion 152a of the first spacer 150a and the active region 112 and the shallow trench isolation 114 thereunder.

Returning to FIG. 1 , then, the method for forming the semiconductor structure 100 further includes, after etching the bottom 152 a of the first spacer 150 a and the active region 112 and the shallow trench isolation 114 therebelow, forming the active region 112 and the shallow trench in the substrate 110 . A semiconductor layer 190 is formed on the trench isolation 114 , wherein the semiconductor layer 190 of the semiconductor structure 100 is on the sidewalls of the spin-on dielectric layer 180 , and the semiconductor layer 190 extends to the sidewalls 164 of the insulating layer 160 . In this way, the structure shown in FIG. 1 can be obtained.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

100: Semiconductor Structure 110: Substrate 112: Active Zone 114: Shallow Trench Isolation 120: Gate 122: Sidewall 130: bit line 132: Sidewall 134: Underside 136: Top surface 140: upper cover layer 142: Sidewall 150a: first spacer 152a: Bottom 154a: Sidewall 150b: Second spacer 152b: Sidewall 154b: Bottom 160: Insulation layer 162: Underside 164: Sidewall 170: Air Gap 172: top 174: Bottom 180: Spin-on dielectric layer 190: Semiconductor layer 200: Photoresist 202: Top Surface 204: Sidewall D1: vertical direction O: open

An embodiment of the present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure. FIG. 2 is a flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the present disclosure. 3 to 11 are cross-sectional views at different stages of a method of forming a semiconductor structure.

Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none

100: Semiconductor Structure

110: Substrate

112: Active Zone

114: Shallow Trench Isolation

120: Gate

122: Sidewall

130: bit line

132: Sidewall

134: Underside

136: Top surface

140: upper cover layer

142: Sidewall

150a: first spacer

152a: Bottom

154a: Sidewall

150b: Second spacer

152b: Sidewall

160: Insulation layer

162: Underside

164: Sidewall

170: Air Gap

172: top

174: Bottom

180: Spin-on dielectric layer

190: Semiconductor layer

D1: vertical direction

Claims (10)

A semiconductor structure, comprising: a substrate; a gate electrode and a bit line on the substrate, wherein the gate electrode is located between the substrate and the bit line; an upper cap layer on the bit line; a first a spacer on the sidewall of the gate electrode, the bit line and the upper capping layer; an insulating layer on the upper part of the first spacer; a second spacer on the bottom surface of the insulating layer and extending downward, wherein the insulating layer, the first spacer and the second spacer define an air gap, wherein a top surface of the second spacer is aligned with a top of the air gap; and a spin coating The electric layer is located between the first spacer, the air gap and the second spacer, and is lower than the bottom surface of the bit line. The semiconductor structure of claim 1, wherein the top of the air gap is higher than the top surface of the bit line. The semiconductor structure of claim 1, wherein the first spacer, the air gap, and the second spacer are parallel to each other in a vertical direction. The semiconductor structure of claim 1, wherein the substrate An active region is isolated from a shallow trench beside the active region, and the active region is located below the gate and the first spacer. The semiconductor structure of claim 4, further comprising: a semiconductor layer located on the spin-on dielectric layer, the shallow trench isolation and the active region, and extending to the sidewall of the insulating layer. A method for forming a semiconductor structure, comprising: forming a photoresist on a first spacer on a substrate, wherein the first spacer is located on a gate electrode, a bit line and a sidewall of an upper capping layer, and the The bit line is located between the gate and the upper cap layer; an insulating layer is formed on a top surface of the photoresist and the sidewall of the first spacer; a bottom of the insulating layer and the photoresist are etched so that the remaining The insulating layer and the photoresist are arranged along the first spacer; a second spacer is formed on the photoresist; the bottom of the second spacer and the photoresist are etched to expose the first spacer a bottom of the first spacer; remove the photoresist between the first spacer and the second spacer to form an air gap, wherein there is an opening between the bottom of the first spacer and the second spacer, the The opening is located under the bit line, and a top surface of the second spacer is aligned with a top of the air gap; and a spin-on dielectric layer is formed on the bottom of the first spacer, so that the spin-coating A dielectric layer is located in the opening. The method of claim 6, further comprising: etching the spin-on dielectric layer outside the opening and on the bottom of the first spacer. The method of claim 7, wherein the substrate has an active region isolated from a shallow trench beside the active region, the method further comprising: etching the bottom of the first spacer and the shallow trench therebelow isolation and the active zone. The method of claim 8, further comprising: forming a semiconductor layer on the shallow trench isolation and the active region, wherein the semiconductor layer is on the spin-on dielectric layer. The method of claim 6, further comprising: after etching the bottom of the insulating layer and the photoresist, anisotropically etching the photoresist so that the sidewall of the photoresist is closer to the first photoresist than the sidewall of the insulating layer a spacer.

Images