TWI892929B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a substrate, a metal layer, a semiconductor layer, an insulating layer and a buffer layer. The substrate has a recess. The metal layer is located in the recess of the substrate. The semiconductor layer is located in the recess of the substrate and on the metal layer, in which the bottom of the semiconductor layer directly contacts the metal layer. The insulating layer is located in the recess of the substrate and on the semiconductor layer. The buffer layer extends from the position between the semiconductor layer and the metal layer, through the sidewall of the semiconductor layer, to the sidewall of the insulating layer, such that the buffer layer has an L-shaped cross section.

Description

Semiconductor device and manufacturing method thereof

The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

In dynamic random access memory (DRAM), gate-induced drain leakage (GIDL) is a serious and difficult-to-eliminate problem. Optimizing transistor saturation current (I _D,SAT ) can lead to GIDL, which can severely impact memory writeback. As the source/drain doping density increases, the contact between the wordline gate conductor and the drain increases, increasing the electric field between them and leading to greater GIDL.

The traditional solution is to reduce the drain doping density and then overlap the gate with the drain, but this affects the memory drive current and leads to poor write-back performance. Another traditional approach is to use a dual work function array (DFA) structure in the word line. However, the different resistivities of the DFA structure due to different materials cause time differences in signal transmission. Therefore, as the word line length increases and the operating frequency of the gate voltage switch increases, the DFA structure is prone to resistance-capacitance delay (RC delay).

One technical aspect of the present disclosure is a semiconductor device.

According to one embodiment of the present disclosure, a semiconductor device includes a substrate, a metal layer, a semiconductor layer, an insulating layer, an isolation layer, and a buffer layer. The substrate has a recess, and the metal layer is located within the recess. The semiconductor layer is located within the recess and on the metal layer, with the bottom of the semiconductor layer in direct contact with the metal layer. The insulating layer is located within the recess. The isolation layer is located within the recess and on the semiconductor layer. The buffer layer has a horizontal portion and a vertical portion adjacent to the horizontal portion, the horizontal portion is located between the semiconductor layer and the metal layer, a portion of the vertical portion is located between the semiconductor layer and the insulating layer, and another portion of the vertical portion is located between the isolation layer and the insulating layer.

In one embodiment of the present disclosure, the bottom of the semiconductor layer is located within the horizontal portion of the buffer layer, and the vertical portion contacts the sidewalls of the semiconductor layer and the sidewalls of the isolation layer.

In one embodiment of the present disclosure, the bottom of the semiconductor layer is located in the opening of the buffer layer.

In one embodiment of the present disclosure, the material of the metal layer includes tungsten.

In one embodiment of the present disclosure, the material of the semiconductor layer includes polysilicon.

In one embodiment of the present disclosure, the material of the isolation layer includes silicon nitride.

In one embodiment of the present disclosure, an insulating layer is located between the substrate and the metal layer and between the substrate and the buffer layer.

Another technical aspect of the present disclosure is a method for manufacturing a semiconductor device.

According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device includes forming an insulating layer in a groove of a substrate; forming a metal layer in the groove of the substrate; forming a buffer layer in the groove of the substrate and on the metal layer; etching the buffer layer to form an opening so that the buffer layer has a horizontal portion and a vertical portion adjacent to the horizontal portion; and A semiconductor layer is formed on the metal layer so that a bottom of the semiconductor layer is located in the opening and in direct contact with the metal layer, the horizontal portion is between the semiconductor layer and the metal layer, and a portion of the vertical portion is located between the semiconductor layer and the insulating layer; and an isolation layer is formed on the semiconductor layer so that another portion of the vertical portion is located between the isolation layer and the insulating layer.

In one embodiment of the present disclosure, etching the buffer layer to form the opening includes forming two spacers facing each other in the groove and on the buffer layer; etching the buffer layer using the two spacers as masks to form the opening; and removing the two spacers.

In one embodiment of the present disclosure, etching the buffer layer to form the opening is performed using a dry etching method.

In the disclosed embodiment, the buffer layer has an opening, allowing the bottom of the semiconductor layer to directly contact the underlying metal layer, effectively short-circuiting the two layers. This configuration, despite the different resistivities of the semiconductor and metal layers, allows them to be electrically connected and conductive, minimizing signal transmission time differences between the two layers. This, in turn, prevents resistance and capacitance delays in the dual-function array structure during high-frequency operation.

The following disclosed embodiments provide numerous different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. However, these examples are merely examples and are not intended to be limiting. Furthermore, the present disclosure may repeat component symbols and/or letters throughout the various examples. This repetition is for simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and/or configurations discussed.

Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for descriptive purposes to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG1 illustrates a cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure. Referring to FIG1 , semiconductor device 100 includes a substrate 110, a metal layer 120, a semiconductor layer 130, an isolation layer 140, and a buffer layer 150. Substrate 110 has a recess 112, and metal layer 120 is located within recess 112 of substrate 110. Semiconductor layer 130 is located within recess 112 of substrate 110 and on metal layer 120, with a bottom portion 132 of semiconductor layer 130 in direct contact with metal layer 120. Isolation layer 140 is located within recess 112 of substrate 110 and on semiconductor layer 130.

Buffer layer 150 extends from a position between semiconductor layer 130 and metal layer 120, through sidewall 134 of semiconductor layer 130, to sidewall 142 of isolation layer 140, giving buffer layer 150 an L-shaped cross-section. Buffer layer 150 has a horizontal portion 152 and a vertical portion 154 adjacent to horizontal portion 152. Bottom portion 132 of semiconductor layer 130 is located within horizontal portion 152 of buffer layer 150, while vertical portion 154 contacts sidewall 134 of semiconductor layer 130 and sidewall 142 of isolation layer 140. The horizontal portion 152 of the buffer layer 150 has an opening 156, and the bottom 132 of the semiconductor layer 130 is located in the opening 156 of the horizontal portion 152. The semiconductor device 100 further includes an insulating layer 160 located in the groove 112 of the substrate 110 and between the substrate 110 and the metal layer 120 and between the substrate 110 and the buffer layer 150.

That is, in this embodiment, a portion of the vertical portion 154 of the buffer layer 150 is located between the semiconductor layer 130 and the insulating layer 160, while the remaining portion of the vertical portion 154 is located between the isolation layer 140 and the insulating layer 160. Furthermore, the vertical portion 154 of the buffer layer 150 directly contacts the insulating layer 160. The horizontal portion 152 of the buffer layer 150 is located on the top surface of the metal layer 120 and directly contacts the top surface of the metal layer 120. The bottom 132 of the semiconductor layer passes through the opening 156 to directly contact and electrically connect with the metal layer 120, and the remaining portion of the semiconductor layer 130 is located above the horizontal portion 152 of the buffer layer 150. Therefore, as shown in FIG. 1 , the buffer layer 150 presents two L-shaped cross-sections, one on each side of the groove 112.

In this embodiment, the substrate 110 is made of silicon (Si), and the metal layer 120 is made of tungsten (W) or titanium nitride (TiN). The semiconductor layer 130 is made of polysilicon. The isolation layer 140 is made of silicon nitride (SiN). The buffer layer 150 may be made of silicon dioxide ( _SiO2 ). However, in some embodiments, the buffer layer 150 may also be made of a high-k dielectric (e.g., silicon nitride), but this is not intended to limit the present disclosure. The "high-k" dielectric used herein is based on silicon dioxide (κ = 3.9), while silicon nitride has a κ of 7 to 8. The use of a high dielectric constant material for the buffer layer 150 can reduce the excessive drop in saturation current. At the same time, such a dual work function array structure can reduce the electric field on the drain side to avoid gate-induced drain leakage current.

Specifically, because the buffer layer 150 of the semiconductor device 100 has the opening 156, the bottom 132 of the semiconductor layer 130 is located in the opening 156 and the bottom 132 of the semiconductor layer 130 is in direct contact with the metal layer 120. As a result, a short circuit occurs between the semiconductor layer 130 and the metal layer 120. Because the bottom 132 of the semiconductor layer 130 is in direct contact with the metal layer 120, the two are electrically connected and conductive, thus avoiding the time difference in signal transmission between the metal layer 120 and the semiconductor layer 130. This, in turn, avoids the resistance and capacitance delay caused by the traditional buffer layer separating the two layers of conductors with different resistivities during high-frequency operation of the dual-function array structure.

It should be understood that the previously described component connection relationships, materials, and functions will not be repeated and are therefore described first. In the following description, a method for manufacturing the semiconductor device 100 will be described.

FIG2 illustrates a flow chart of a method for fabricating a semiconductor device according to one embodiment of the present disclosure. First, in step S1, the method includes forming an insulating layer within a recess in a substrate. Next, in step S2, a metal layer is formed within the recess in the substrate. Then, in step S3, a buffer layer is formed within the recess in the substrate and on the metal layer, wherein the buffer layer is formed along the top surfaces of the insulating layer and the metal layer. Subsequently, in step S4, the buffer layer is etched to form an opening having an L-shaped cross-section. Next, in step S5, a semiconductor layer is formed on the buffer layer and the metal layer, with the bottom of the semiconductor layer located in the opening and in direct contact with the metal layer. In step S6, an isolation layer is formed on the semiconductor layer.

In some embodiments, the method for manufacturing a semiconductor device is not limited to the above-mentioned steps S1 to S6. For example, in some embodiments, other steps may be further included between two successive steps, or other steps may be further included before step S1 and after step S5.

In the following description, each step of the method for manufacturing the semiconductor device will be described in detail.

Figures 3 through 10 illustrate cross-sectional views of intermediate steps in the manufacturing method of semiconductor device 100 shown in Figure 1. Referring to Figures 3 and 4, a recess 112 may be formed in substrate 110. Next, an insulating layer 160 may be formed within recess 112 of substrate 110. While not limited to this method, insulating layer 160 may be formed by oxidizing the silicon in silicon substrate 110 using a high-temperature oxidation process.

5 , after the insulating layer 160 is formed, the metal layer 120 may be formed in the recess 112 of the substrate 110. The metal layer 120 is located on the insulating layer 160. The metal layer 120 may be formed by physical vapor deposition (PVD), but is not limited to this method.

Referring to FIG. 6 , after the metal layer 120 is formed, a buffer layer 150 is formed within the recess 112 of the substrate 110 and on the metal layer 120. The buffer layer 150 is formed along the insulating layer 160 and the top surface of the metal layer 120. The buffer layer 150 formed at this time is a continuous coating layer and is also formed on the top surface of the substrate 110.

Referring to FIG. 7 , two opposing spacers 170 are then formed within the recess 112 and on the buffer layer 150. The spacers 170 can be made of, but are not limited to, silicon dioxide. For example, the spacers 170 can also be made of a patterned photoresist or other material. The two spacers 170 can be formed through a patterning process to create a gap between them. The two spacers 170 can then serve as masks in the subsequent etching step.

Referring to FIG. 8 , after the spacers 170 are formed, the buffer layer 150 is etched using the two spacers 170 as a mask to form an opening 156. The opening between the two spacers 170 allows a portion of the buffer layer 150 to be exposed, allowing the exposed portion of the buffer layer 150 not covered by the two spacers 170 to be etched to form the opening 156. Furthermore, the buffer layer 150 above the substrate 110 outside the recess 112 can be removed by etching. In this embodiment, the buffer layer 150 is etched to form the opening 156 using dry etching, but the present invention is not limited to this method.

9 , after the opening 156 is formed, the two spacers 170 are removed. After the spacers 170 are removed, the buffer layer 150 having an L-shaped cross-section is left, and the horizontal portion 152 thereof has the opening 156. After the opening 156 of the buffer layer 150 is formed, a portion of the metal layer 120 is exposed.

Referring to FIG. 10 , after spacers 170 (see FIG. 7 ) are removed, semiconductor layer 130 is formed on buffer layer 150 and metal layer 120 in FIG. 8 , with bottom 132 of semiconductor layer 130 positioned within opening 156 and in direct contact with metal layer 120. Because opening 156 was etched into buffer layer 150 in the previous step, semiconductor layer 130 can directly contact metal layer 120 through opening 156 during the formation of semiconductor layer 130. This design allows direct electrical connection between the semiconductor layer 130 and the metal layer 120, made of two different materials. This eliminates the resistive and capacitive delays that occur at high operating frequencies due to the different resistivities between the two layers. By directly contacting the bottom 132 of the semiconductor layer 130 with the metal layer 120, the time difference in signal transmission between the metal layer 120 and the semiconductor layer 130 is reduced. This, in turn, avoids the resistive and capacitive delays that occur when the dual-function array structure operates at high frequencies due to the traditional buffer layer separating the two layers of conductors with different resistivities. The dual-function array structure of this embodiment can reduce the electric field on the drain side to prevent the gate from inducing drain leakage current.

Referring to FIG. 10 and FIG. 1 , after semiconductor layer 130 is formed, isolation layer 140 is formed on semiconductor layer 130. After this step is completed, semiconductor device 100 of FIG. 1 is fabricated. Buffer layer 150 is etched to form opening 156, allowing bottom 132 of semiconductor layer 130 to directly contact metal layer 120 through opening 156. This minimizes the time difference between signal transmission between metal layer 120 and semiconductor layer 130, thereby avoiding the resistive and capacitive delays that occur in conventional dual-function array structures during high-frequency operation due to the traditional buffer layer separating two layers of conductors with different resistivities.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

100: Semiconductor device 110: Substrate 112: Recess 120: Metal layer 130: Semiconductor layer 132: Bottom layer 134: Sidewalls 140: Isolation layer 142: Sidewalls 150: Buffer layer 152: Horizontal portion 154: Vertical portion 156: Opening 160: Insulating layer 170: Spacer S1, S2, S3, S4, S5, S6: Steps

The present disclosure is best understood from the following embodiments when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of presentation. Figure 1 illustrates a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Figure 2 illustrates a flow chart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure. Figures 3 through 10 illustrate cross-sectional views of intermediate stages of the method for fabricating the semiconductor device of Figure 1.

Domestic Storage Information (Please enter in order by institution, date, and number) None International Storage Information (Please enter in order by country, institution, date, and number) None

100: Semiconductor devices

110:Substrate

112: Groove

120: Metal layer

130: Semiconductor layer

132: Bottom

134: Sidewall

140: Isolation layer

142: Sidewall

150: Buffer layer

152: Horizontal section

154: Vertical part

156: Opening

160: Insulating layer

Claims (10)

A semiconductor device includes: a substrate having a recess; an insulating layer conformally formed in the recess of the substrate; a metal layer located on the insulating layer in the recess of the substrate; and a semiconductor layer located in the recess of the substrate and on the metal layer, wherein a bottom portion of the semiconductor layer is in direct contact with the metal layer. An isolation layer is located in the groove of the substrate and on the semiconductor layer; and a buffer layer has a horizontal portion and a vertical portion adjacent to the horizontal portion, the horizontal portion is located between the semiconductor layer and the metal layer, a portion of the vertical portion is located between the semiconductor layer and the insulating layer, and another portion of the vertical portion is located between the isolation layer and the insulating layer. The semiconductor device of claim 1, wherein the bottom of the semiconductor layer is located within the horizontal portion of the buffer layer, and the vertical portion contacts a sidewall of the semiconductor layer and a sidewall of the isolation layer. The semiconductor device of claim 2, wherein the bottom of the semiconductor layer is located in an opening of the buffer layer. The semiconductor device of claim 1, wherein the material of the metal layer includes tungsten. The semiconductor device as claimed in claim 1, wherein the material of the semiconductor layer includes polysilicon. The semiconductor device as claimed in claim 1, wherein the material of the isolation layer includes silicon nitride. The semiconductor device of claim 1, wherein the insulating layer is located between the substrate and the metal layer and between the substrate and the buffer layer. A method for manufacturing a semiconductor device includes: forming an insulating layer in a groove of a substrate in a conformal manner; forming a metal layer on the insulating layer in the groove of the substrate; forming a buffer layer in the groove of the substrate and on the metal layer; etching the buffer layer to form an opening so that the buffer layer has a horizontal portion and a vertical portion adjacent to the horizontal portion; and forming a vertical portion on the buffer layer. A semiconductor layer is formed on the metal layer so that a bottom portion of the semiconductor layer is located in the opening and in direct contact with the metal layer, the horizontal portion is located between the semiconductor layer and the metal layer, and a portion of the vertical portion is located between the semiconductor layer and the insulating layer; and an isolation layer is formed on the semiconductor layer so that another portion of the vertical portion is located between the isolation layer and the insulating layer. The method for manufacturing a semiconductor device as described in claim 8, wherein etching the buffer layer to form the opening comprises: forming two opposing spacers in the groove and on the buffer layer; etching the buffer layer using the two spacers as masks to form the opening; and removing the two spacers. The method for manufacturing a semiconductor device as described in claim 8, wherein etching the buffer layer to form the opening is performed using a dry etching method.