TWI762310B - Circuit board structure and manufacturing method thereof - Google Patents

Abstract

A circuit board structure includes a redistribution structure layer, a build-up circuit structure layer and a connection structure layer. The redistribution structure layer includes a plurality of first connecting pads. The build-up circuit structure layer is disposed on one side of the redistribution structure layer and includes a plurality of second connecting pads. A line width and a line spacing of the redistribution structure layer are smaller than a line width and the line spacing of the build-up circuit structure layer. The connection structure layer is disposed between the redistribution structure layer and the build-up circuit structure layer, and includes a substrate and a plurality of conductive paste pillars penetrating the substrate. The first connecting pads are electrically connected to the second connecting pads through the conductive paste pillars, respectively. The first connecting pads and the second connecting pads are respectively embedded in two opposite surface of the substrate.

Description

Circuit board structure and method of making the same

The present invention relates to a substrate structure and a manufacturing method thereof, and in particular, to a circuit board structure and a manufacturing method thereof.

Generally speaking, two circuit boards with lines or conductive structures are to be combined with each other, and they are connected through solder joints, and are filled between the two substrates through underfill to seal the solder joints. However, in the process of high-temperature reflow of the solder, the circuit board with a larger area size cannot be relieved of the stress, and a large warpage is likely to occur, thereby reducing the assembly yield between the two circuit boards.

The invention provides a circuit board structure without using solder and primer, which can reduce the cost and has better structural reliability.

The present invention also provides a manufacturing method of a circuit board structure, which is used to manufacture the above-mentioned circuit board structure.

The circuit board structure of the present invention includes a reconfigured circuit structure layer, a build-up circuit structure layer and a connection structure layer. The reconfiguration line structure layer includes a plurality of first connection pads. The build-up circuit structure layer is disposed on one side of the reconfigured circuit structure layer and includes a plurality of second connection pads. The line width and line spacing of the reconfigured circuit structure layer are smaller than those of the build-up circuit structure layer. The connection structure layer is disposed between the reconfigured circuit structure layer and the build-up circuit structure layer, and includes a base material and a plurality of conductive glue columns penetrating the base material. The first connection pads are electrically connected to the second connection pads through the conductive glue columns respectively. The first connection pad and the second connection pad are respectively embedded in two opposite surfaces of the substrate.

In an embodiment of the present invention, the above-mentioned reconfiguration circuit structure layer further includes a plurality of dielectric layers, at least one reconfiguration circuit, a plurality of conductive vias, and a plurality of die pads. The dielectric layers are alternately arranged with at least one reconfiguration line. The first connection pads, the reconfiguration lines and the chip pads are electrically connected through the conductive vias. The outermost dielectric layers are a first dielectric layer and a second dielectric layer. The chip pads are buried in the first dielectric layer, the first connection pads are located on the second dielectric layer, and the second dielectric layer directly contacts the base material of the connection structure layer.

In an embodiment of the present invention, the material of the above-mentioned dielectric layer includes a photosensitive dielectric material or an Ajinomoto Build-up Film (ABF).

In an embodiment of the present invention, the above-mentioned circuit board structure further includes a surface treatment layer disposed on the chip pads of the reconfigured circuit structure layer. The material of the surface treatment layer includes nickel palladium immersion gold (ENEPIG), organic solderability preservatives (OSP) or electroless nickel immersion gold (ENIG).

In an embodiment of the present invention, the above-mentioned circuit board structure further includes a solder mask layer, which is disposed on a surface of the build-up circuit structure layer relatively far from the connection structure layer, and covers part of the build-up circuit structure layer to define a plurality of layers. solder ball pads.

The manufacturing method of the circuit board structure of the present invention includes the following steps. A reconfigured line structure layer including a plurality of first connection pads is provided. A connection structure layer including a base material and a plurality of conductive glue columns penetrating the base material is provided, wherein the connection structure layer is in a B-stage state. A build-up line structure layer including a plurality of second connection pads is provided, wherein the line width and line spacing of the reconfigured line structure layer are smaller than those of the build-up line structure layer. The reconfiguration line structure layer, the connection structure layer and the build-up line structure layer are pressed together, so that the connection structure layer is located between the reconfiguration line structure layer and the build-up line structure layer. The first connection pads are electrically connected to the second connection pads respectively through the conductive glue posts, and the first connection pads and the second connection pads are respectively embedded in two opposite surfaces of the base material, and the connection structure layer formed by the base material and the conductive glue posts From a B-stage state to a C-stage state.

In an embodiment of the present invention, the above-mentioned step of providing the reconfigured circuit structure layer including the first connection pad includes the following steps. A temporary substrate and a release film on the temporary substrate are provided. An insulating layer is formed on the release film. A core substrate is provided on the insulating layer. The core substrate includes a core layer, a first copper foil layer and a second copper foil layer on opposite sides of the core layer. The second copper foil layer is located between the core layer and the insulating layer. A plurality of chip pads are formed on the first copper foil layer. A first dielectric layer is formed on the first copper foil layer. The first dielectric layer covers the die pads and has a plurality of first openings, and the first openings expose part of the die pads. At least one reconfiguration line and a plurality of first conductive vias are formed. The redistribution lines are disposed on the first dielectric layer, and the first conductive vias are respectively located in the first openings and electrically connect the redistribution lines and the chip pads. A second dielectric layer is formed on the reconfiguration line. The second dielectric layer has a plurality of second openings, and the second openings expose part of the reconfiguration lines. A first connection pad and a plurality of second conductive vias are formed. The first connection pads are disposed on the second dielectric layer, and the second conductive vias are respectively located in the second openings and electrically connect the redistribution lines and the first connection pads. The temporary substrate and release film are removed to expose the insulating layer.

In an embodiment of the present invention, the material of the first dielectric layer and the material of the second dielectric layer include a photosensitive dielectric material or an Ajinomoto deposition film.

In an embodiment of the present invention, after laminating the reconfiguration circuit structure layer, the connection structure layer and the build-up circuit structure layer, the method further includes: removing the insulating layer and the core substrate to expose the reconfiguration circuit structure layer the first dielectric layer. A surface treatment layer is formed on the chip pads of the reconfigured circuit structure layer. The material of the surface treatment layer includes nickel palladium immersion gold, organic solder resist or electroless nickel immersion gold.

In an embodiment of the present invention, before laminating the reconfigured circuit structure layer, the connection structure layer, and the build-up circuit structure layer, it further includes forming a solder mask layer on the build-up circuit structure layer that is relatively far from the connection structure layer. on the surface. The solder mask covers part of the build-up circuit structure layer to define a plurality of solder ball pads.

Based on the above, in the manufacturing method of the circuit board structure of the present invention, the circuit board structure is formed by pressing the reconfigured circuit structure layer, the connection structure layer and the build-up circuit structure layer, wherein the first layer of the reconfigured circuit structure layer is formed. A connection pad is electrically connected to the second connection pad of the build-up circuit structure layer through the conductive glue column of the connection structure layer respectively, and the first connection pad and the second connection pad are respectively embedded in two opposite surfaces of the base material of the connection structure layer. Therefore, the method for fabricating the circuit board structure of the present invention does not need to use solder and primer, which can effectively reduce the fabrication cost of the circuit board structure. In addition, because no solder is used, the bonding yield between the reconfigured circuit structure layer, the connection structure layer and the build-up circuit structure layer can be effectively improved, thereby improving the structural reliability of the circuit board structure of the present invention.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

1A to 1P are schematic cross-sectional views of a method for fabricating a circuit board structure according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the circuit board structure of FIG. 1P where a wafer is placed. Regarding the fabrication method of the circuit board structure of the present embodiment, first, referring to FIG. 1A , a temporary substrate 10 and a release film 12 on the temporary substrate 10 are provided. Here, the material of the temporary substrate 10 is, for example, glass or plastic, which is a substrate without lines.

Next, referring to FIG. 1B , an insulating layer 20 is formed on the release film 12 , wherein the material of the insulating layer 20 is, for example, Ajinomoto Buildup Film (ABF), but not limited thereto.

Next, referring to FIG. 1B again, a core substrate 30 is provided on the insulating layer 20 , wherein the core substrate 30 includes a core layer 32 and a first copper foil layer 34 and a second copper foil layer 36 on opposite sides of the core layer 32 . In one embodiment, a chemical-mechanical polishing process may be performed on the surface of the first copper foil layer 34 to planarize the surface. Here, the second copper foil layer 36 is located between the core layer 32 and the insulating layer 20 .

Next, referring to FIG. 1C , a patterned photoresist layer P1 is formed on the first copper foil layer 34 , wherein part of the first copper foil layer 34 is exposed from the patterned photoresist layer P1 .

Next, referring to FIG. 1D , a plurality of chip pads 112 are formed on the first copper foil layer 34 , wherein the chip pads 112 are located on the first copper foil layer 34 exposed by the patterned photoresist layer P1 . Here, the method of forming the die pads 112 is, for example, electroplating.

Next, referring to FIG. 1D and FIG. 1E at the same time, the patterned photoresist layer P1 is removed to expose the first copper foil layer 34 .

Next, referring to FIG. 1F, a first dielectric layer 114 is formed on the first copper foil layer 34, wherein the first dielectric layer 114 covers the chip pads 112 and has a plurality of first openings H1, and the first openings H1 are exposed Part of the die pads 112 are removed. Here, the material of the first dielectric layer 114 is, for example, a photosensitive dielectric material or an Ajinomoto build-up film (ABF).

Next, referring to FIG. 1G , a seed layer S is formed on the first dielectric layer 114 , wherein the seed layer S covers the first dielectric layer 114 and the inner wall of the first opening H1 and is connected to the chip pad 112 .

Next, referring to FIG. 1H , a patterned photoresist layer P2 is formed on the seed layer S, wherein part of the seed layer S is exposed from the patterned photoresist layer P2 .

Next, referring to FIG. 1I, a metal layer M is formed on the seed layer S exposed by the patterned photoresist layer P2, wherein the method of forming the metal layer M is, for example, electroplating.

Next, referring to FIG. 1J , the patterned photoresist layer P2 and the seed layer S located under the patterned photoresist layer P2 are removed to form the reconfiguration line 116 and the first conductive via T1 . Here, the relocation lines 116 are located on the first dielectric layer 114 , and the first conductive vias T1 are respectively located in the first openings H1 and electrically connect the relocation lines 116 and the die pads 112 .

Next, the steps of FIG. 1F to FIG. 1J can be repeated to form the required number of layers of the reconfiguration lines 116 and the first conductive vias T1 , and the number of repetitions can be based on user requirements.

Next, referring to FIG. 1K , a second dielectric layer 118 is formed on the reconfiguration circuit 116 , wherein the second dielectric layer 118 has a plurality of second openings H2 , and the second openings H2 expose part of the reconfiguration circuit 116 . Here, the material of the second dielectric layer 118 is, for example, a photosensitive dielectric material or an Ajinomoto build-up film (ABF).

Next, referring to FIG. 1K again, the same steps as in FIGS. 1G to 1J are used to form the first connection pads 119 and a plurality of second conductive vias T2 . Here, the first connection pads 119 are disposed on the second dielectric layer 118 , and the second conductive vias T2 are respectively located in the second openings H2 and electrically connect the redistribution lines 116 and the first connection pads 119 . So far, the fabrication of the reconfigured circuit structure layer 110 including the first connection pads 119 has been completed. Here, the reconfiguration line structure layer 110 is embodied as a reconfiguration line structure layer with thin lines.

Next, referring to FIG. 1K and FIG. 1L at the same time, the temporary substrate 10 and the release film 12 are removed to expose the insulating layer 20 .

Next, referring to FIG. 1M , a connection structure layer 120 including a substrate 122 and a plurality of conductive glue posts 125 penetrating the substrate 122 is provided, wherein the connection structure layer 120 is in a B-stage state. Here, the material of the base material 122 is, for example, a prepreg (PP), and the material of the conductive glue column 125 is, for example, a conductive metal glue, which is coated and fabricated by a printing method, and can have the effects of electrical conductivity and heat conduction. , and suitable for bonding with any metal material.

Next, referring to FIG. 1M again, a build-up wiring structure layer 130 including a plurality of second connection pads 132 is provided, wherein the line width and line spacing of the reconfigured wiring structure layer 110 are smaller than those of the build-up wiring structure layer 130 . line spacing. At this time, a solder mask layer 150 has been formed on a surface 131 of the build-up circuit structure layer 130 relatively far from the connection structure layer 120 . The solder mask layer 150 covers part of the build-up circuit structure layer 130 to define a plurality of solder ball pads SP. Here, the build-up circuit structure layer 130 is embodied as a multilayer circuit board.

It should be noted that this embodiment does not limit the order in which the reconfiguration circuit structure layer 110 , the connection structure layer 120 and the build-up circuit structure layer 130 are provided.

Next, referring to FIG. 1N , the reconfiguration circuit structure layer 110 , the connection structure layer 120 and the build-up circuit structure layer 130 are pressed together by thermocompression, so that the connection structure layer 120 is located between the reconfiguration circuit structure layer 110 and the build-up circuit structure layer 110 . between the layers 130 of the circuit structure. At this time, the insulating layer 20 and the core substrate 30 are still located on the reconfigured circuit structure layer 110 . In particular, the first connection pads 119 are electrically connected to the second connection pads 132 through the conductive glue posts 125 respectively, and the first connection pads 119 and the second connection pads 132 are respectively embedded in two opposite surfaces of the substrate 122 . During thermocompression bonding, the reconfigured circuit structure layer 110 and the build-up circuit structure layer 130 are in direct contact with the base material 122 of the connection structure layer 120 and the conductive glue posts 125 are pressed to deform. At this time, since the base material 122 and the conductive glue post 125 are not fully cured and have flexibility and adhesion, the reconfiguration circuit structure layer 110 and the build-up circuit structure layer 130 can be bonded together, and the first connection pad 119 and the second connection pad 119 can be bonded together. The connection pads 132 are respectively extruded into the base material 122 and embedded in the base material 122 . After the lamination and curing, the substrate 122 and the conductive glue post 125 of the connection structure layer 120 are transformed from a B-stage state to a C-stage state.

After that, please refer to FIG. 1N and FIG. 1O at the same time, the insulating layer 20 and the core substrate 30 are removed, and the first dielectric layer 112 of the reconfigured circuit structure layer 110 is exposed.

Finally, referring to FIG. 1P , a surface treatment layer 140 is formed on the chip pads 112 of the reconfigured circuit structure layer 110 . Here, the material of the surface treatment layer 140 is, for example, nickel palladium immersion gold (ENEPIG), organic solder resist (OSP) or electroless nickel immersion gold (ENIG). So far, the fabrication of the circuit board structure 100 has been completed.

In terms of structure, please refer to FIG. 1P again. In this embodiment, the circuit board structure 100 includes a reconfiguration circuit structure layer 110 , a build-up circuit structure layer 130 and a connection structure layer 120 . The reconfiguration line structure layer 110 includes first connection pads 119 . The build-up circuit structure layer 130 is disposed on one side of the reconfiguration circuit structure layer 110 and includes a second connection pad 132 . The line width and line spacing of the reconfigured circuit structure layer 110 are smaller than those of the build-up circuit structure layer 130 . The connection structure layer 120 is disposed between the reconfigured circuit structure layer 110 and the build-up circuit structure layer 130 , and includes a base material 122 and a conductive glue column 125 penetrating the base material 122 . The first connection pads 119 are electrically connected to the second connection pads 132 through the conductive glue posts 125 respectively. The first connection pads 119 and the second connection pads 132 are respectively embedded in two opposite surfaces of the substrate 122 .

In detail, the reconfiguration circuit structure layer 110 of this embodiment further includes die pads 112 , a first dielectric layer 114 , a reconfiguration circuit 116 , a second dielectric layer 118 , a first conductive via T1 and a second conductive via Through hole T2. The first dielectric layers 114 , the reconfiguration lines 116 and the second dielectric layers 118 are alternately stacked. The first connection pad 119 , the reconfiguration line 116 and the die pad 112 are electrically connected through the first conductive via T1 and the second conductive via T2 . The die pads 112 are buried in the first dielectric layer 114 , and the first connection pads 119 are located on the second dielectric layer 118 , and the second dielectric layer 118 directly contacts the substrate 122 of the connection structure layer 120 .

In addition, the circuit board structure of this embodiment further includes a surface treatment layer 140 and a solder resist layer 150 . The surface treatment layer 140 is disposed on the chip pads 112 of the reconfigured circuit structure layer 110 , wherein the material of the surface treatment layer 140 is, for example, nickel-palladium immersion gold (ENEPIG), organic solder resist (OSP) or electroless nickel-immersion gold ( ENIG). The solder resist layer 150 is disposed on the surface 131 of the build-up circuit structure layer 130 relatively far from the connection structure layer 120 , and covers a part of the build-up circuit structure layer 130 to define solder ball pads SP.

In short, since the circuit board structure 100 is formed by laminating the re-arranged circuit structure layer 110 , the connection structure layer 120 and the build-up circuit structure layer 130 in this embodiment, there is no need to use solder and primer, which can effectively The manufacturing cost of the circuit board structure 100 is reduced. In addition, since no solder joints are used, the bonding yield between the reconfigured circuit structure layer 110 , the connection structure layer 120 and the build-up circuit structure layer 130 can be effectively improved, thereby improving the circuit board of this embodiment. Structural reliability of the structure 100 .

In application, please refer to FIG. 2 , the chip 200 can be electrically connected to the chip pads 112 of the reconfigured circuit structure layer 110 through the solder 210 to form a chip package structure 300 .

To sum up, in the manufacturing method of the circuit board structure of the present invention, the circuit board structure is formed by laminating the reconfigured circuit structure layer, the connection structure layer and the build-up circuit structure layer, wherein the circuit board structure layer is reconfigured The first connection pads are electrically connected to the second connection pads of the build-up circuit structure layer through the conductive glue posts of the connection structure layer respectively, and the first connection pads and the second connection pads are respectively embedded in the opposite two sides of the base material of the connection structure layer. surface. Thereby, the method for fabricating the circuit board structure of the present invention does not need to use solder joints and primers, which can effectively reduce the fabrication cost of the circuit board structure. In addition, because no solder is used, the bonding yield between the reconfigured circuit structure layer, the connection structure layer and the build-up circuit structure layer can be effectively improved, thereby improving the structural reliability of the circuit board structure of the present invention.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10: Temporary substrate 12: Release film 20: Insulation layer 30: Core substrate 32: Core layer 34: The first copper foil layer 36: Second copper foil layer 110: Reconfigure the circuit structure layer 112: Chip pads 114: first dielectric layer 116: Reconfiguration line 118: Second Dielectric Layer 119: First connection pad 120: Connecting Structural Layers 122: Substrate 125: Conductive glue column 130: Build-up circuit structure layer 131: Surface 132: Second connection pad 140: Surface treatment layer 150: Solder mask 200: Wafer 210: Solder 300: Chip package structure H1: first opening H2: Second opening M: metal layer P1, P2: patterned photoresist layer S: seed layer T1: first conductive via T2: Second conductive via SP: Solder Ball Pad

1A to 1P are schematic cross-sectional views of a method for fabricating a circuit board structure according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the circuit board structure of FIG. 1P where a wafer is placed.

100: Circuit Board Structure

110: Reconfigure the circuit structure layer

112: Chip pads

114: first dielectric layer

116: Reconfiguration line

118: Second Dielectric Layer

119: First connection pad

120: Connecting Structural Layers

122: Substrate

125: Conductive glue column

130: Build-up circuit structure layer

131: Surface

132: Second connection pad

140: Surface treatment layer

150: Solder mask

T1: first conductive via

T2: Second conductive via

SP: Solder Ball Pad

Claims (10)

A circuit board structure, comprising: a reconfigured circuit structure layer, including a plurality of first connection pads; A build-up circuit structure layer is disposed on one side of the re-configuration circuit structure layer and includes a plurality of second connection pads, wherein the line width and line spacing of the re-configuration circuit structure layer are smaller than the lines of the build-up circuit structure layer width and line spacing; and A connection structure layer is disposed between the reconfiguration circuit structure layer and the build-up circuit structure layer, and includes a base material and a plurality of conductive glue columns penetrating the base material, wherein the first connection pads pass through the base material respectively. The conductive glue posts are electrically connected to the second connection pads, and the first connection pads and the second connection pads are respectively embedded in two opposite surfaces of the substrate. The circuit board structure of claim 1, wherein the reconfiguration circuit structure layer further comprises a plurality of dielectric layers, at least one reconfiguration circuit, a plurality of conductive vias and a plurality of chip pads, the dielectric layers and the At least one reconfiguration circuit is alternately arranged, the first connection pads, the at least one reconfiguration circuit and the chip pads are electrically connected through the conductive vias, and the outermost of the dielectric layers is a first dielectric layer electric layer and a second dielectric layer, the chip pads are buried in the first dielectric layer, the first connection pads are located on the second dielectric layer, and the second dielectric layer is directly The substrate in contact with the connection structure layer. The circuit board structure according to claim 2, wherein the materials of the dielectric layers include photosensitive dielectric materials or Ajinomoto build-up films. The circuit board structure according to claim 1, further comprising: A surface treatment layer is disposed on the chip pads of the reconfigured circuit structure layer, wherein the material of the surface treatment layer includes nickel palladium immersion gold, organic solder resist or electroless nickel immersion gold. The circuit board structure according to claim 1, further comprising: A solder resist layer is disposed on a surface of the build-up circuit structure layer relatively far from the connection structure layer, and covers part of the build-up circuit structure layer to define a plurality of solder ball pads. A manufacturing method of a circuit board structure, comprising: providing a reconfigured circuit structure layer including a plurality of first connection pads; providing a connection structure layer including a base material and a plurality of conductive glue pillars penetrating the base material, wherein the connection structure layer is in a B-stage state; providing a build-up wiring structure layer including a plurality of second connection pads, wherein the line width and line spacing of the reconfigured wiring structure layer are smaller than the line width and line spacing of the build-up wiring structure layer; and Pressing the reconfiguration circuit structure layer, the connection structure layer and the build-up circuit structure layer, so that the connection structure layer is located between the reconfiguration circuit structure layer and the build-up circuit structure layer, wherein the first connections The pads are respectively electrically connected to the second connection pads through the conductive glue posts, and the first connection pads and the second connection pads are respectively embedded in two opposite surfaces of the substrate, and the connection structure layer is formed from the The B-stage state is transformed into a C-stage state. The method for fabricating a circuit board structure as claimed in claim 6, wherein the step of providing the reconfigured circuit structure layer including the first connection pads includes: providing a temporary substrate and a release film on the temporary substrate; forming an insulating layer on the release film; A core substrate is provided on the insulating layer, the core substrate includes a core layer and a first copper foil layer and a second copper foil layer located on opposite sides of the core layer, the second copper foil layer is located in the core layer and the insulating layer; forming a plurality of chip pads on the first copper foil layer; A first dielectric layer is formed on the first copper foil layer, the first dielectric layer covers the chip pads and has a plurality of first openings, and the first openings expose part of the chip pads ; At least one reconfiguration circuit and a plurality of first conductive vias are formed, the at least one reconfiguration circuit is disposed on the first dielectric layer, and the first conductive vias are respectively located in the first openings and electrically connected to the at least one reconfiguration circuit and the chip pads; forming a second dielectric layer on the at least one reconfiguration line, the second dielectric layer has a plurality of second openings, and the second openings expose a part of the at least one reconfiguration line; The first connection pads and a plurality of second conductive vias are formed, the first connection pads are disposed on the second dielectric layer, and the second conductive vias are respectively located in the second openings and electrically sexually connecting the at least one reconfiguration line with the first connection pads; and The temporary substrate and the release film are removed to expose the insulating layer. The method for fabricating a circuit board structure as claimed in claim 7, wherein the material of the first dielectric layer and the material of the second dielectric layer include photosensitive dielectric materials or Ajinomoto build-up films. The manufacturing method of a circuit board structure according to claim 7, wherein after pressing the reconfigured circuit structure layer, the connection structure layer and the build-up circuit structure layer, further comprising: removing the insulating layer and the core substrate to expose the first dielectric layer of the reconfiguration circuit structure layer; and A surface treatment layer is formed on the chip pads of the reconfigured circuit structure layer, wherein the material of the surface treatment layer includes nickel palladium immersion gold, organic solder resist or electroless nickel immersion gold. The manufacturing method of the circuit board structure as claimed in claim 6, before pressing the reconfigured circuit structure layer, the connection structure layer and the build-up circuit structure layer, further comprising: A solder resist layer is formed on a surface of the build-up circuit structure layer relatively far from the connection structure layer, wherein the solder resist layer covers part of the build-up circuit structure layer to define a plurality of solder ball pads.

Images