TW201436164A - Substrate for semiconductor package and method of forming same - Google Patents

Abstract

The present invention provides a method of forming a substrate for a semiconductor package and a substrate for a semiconductor package. The method includes providing a carrier and forming a plurality of outer pads on the carrier, the outer pads formed on the carrier defining a first conductive layer. A molding operation is performed to form a first insulating layer on the carrier with a molding compound. The first conductive layer is buried in the first insulating layer. Forming one or more of a plurality of bond pads, a plurality of conductive traces, and a plurality of microvias on the first conductive layer, and forming the bond pads, the conductive traces, and the like on the first conductive layer The one or more of the microvias define a second conductive layer.

Description

Substrate for semiconductor package and method of forming same Field of invention

The present invention relates to semiconductor packages and more particularly to a substrate for a semiconductor package, a method of forming the substrate, a semiconductor package having the substrate formed thereon, and a method of packaging a semiconductor wafer with the substrate.

Background of the invention

Manufacturability is an important consideration in semiconductor packaging because it has a direct impact on the cost of a package. Therefore, in order to reduce packaging costs, it is necessary to have a substrate that contributes to the semiconductor packaging process.

Summary of invention

Thus, in a first aspect, the present invention provides a method of forming a substrate for a semiconductor package. The method includes providing a carrier and forming a plurality of outer pads on the carrier, the outer pads formed on the carrier defining a first conductive layer. A molding operation is performed to form a first insulating layer on the carrier with a molding compound. The first conductive layer is buried in the first insulating layer. Forming one or more of a plurality of bonding pads, a plurality of conductive lines, and a plurality of microvias on the first conductive layer, and forming the first conductive The one or more of the bond pads, the conductive traces, and the microvias on the layer define a second conductive layer.

In a second aspect, the present invention provides a substrate for a semiconductor package. The substrate includes a carrier and a plurality of outer pads formed on the carrier, and the outer pads formed on the carrier define a first conductive layer. A first insulating layer is formed on the carrier as a molding compound. The first conductive layer is buried in the first insulating layer. One or more of a plurality of bond pads, a plurality of conductive traces, and a plurality of microvias are formed on the first conductive layer, and the bond pads formed on the first conductive layer, the conductive traces, and the The one or more of the microvias define a second conductive layer.

In a third aspect, the present invention provides a method of packaging a semiconductor wafer. The method includes providing a substrate for a semiconductor package formed according to the first aspect, attaching the semiconductor wafer to one of the outer pads and a die pad of the substrate, electrically connecting the semiconductor wafer with a plurality of metal wires The bonding pads of the substrate seal the semiconductor wafer, the metal lines and the bonding pads with a sealing material, and remove the carrier to expose the first conductive layer.

In a fourth aspect, the present invention provides a semiconductor package including a plurality of outer pads, and the outer pads define a first conductive layer. The first conductive layer is buried in a first insulating layer, and the first insulating layer is formed of a molding compound. One or more of a die pad, a plurality of bond pads, a plurality of conductive traces, and a plurality of microvias are formed on the first conductive layer, and the die pad is formed on the first conductive layer. One of the bonding pads, the conductive lines, and the microvias More than one defines a second conductive layer. A semiconductor wafer is attached to one of the outer pads and the die pad and a plurality of metal wires electrically connect the semiconductor wafer to the bond pads. A sealing material seals the semiconductor wafer, the metal lines, and the bonding pads.

Other aspects and advantages of the present invention will be apparent from the following detailed description.

10‧‧‧ base

12‧‧‧ Carrier

14‧‧‧Outer mat; first conductive layer

15‧‧‧First or bottom finishing layer

16‧‧‧ photoresist layer

18‧‧‧ openings

20‧‧‧first insulating layer; first dielectric layer

22‧‧‧Molded compounds

24‧‧‧ surface

26‧‧‧ Conductive film layer

28‧‧‧die pad; cushion

30‧‧‧bonding pad; wire layer

32‧‧‧Electrical circuit; wire layer

34‧‧‧Second or top finishing layer

36‧‧‧Semiconductor wafer; semiconductor die

38‧‧‧Adhesive; Epoxy

40‧‧‧Metal wire; electrical connector

42‧‧‧ sealing material; dielectric layer

44‧‧‧Semiconductor package

46‧‧‧Outer die pad

48‧‧‧Second or continuous insulation; shielding

50‧‧‧Second or second insulation

52‧‧‧Second photoresist layer

54‧‧‧micro-through holes; micro-through holes

56‧‧‧micro-through holes; vertical contact columns; vertical columns

58‧‧‧ cavity

60‧‧‧ first part

62‧‧‧Second part

64‧‧‧Filling

66‧‧‧Resin

68‧‧‧ Third photoresist layer

70‧‧‧fourth photoresist layer

72‧‧‧ cavity

74‧‧‧ first part

76‧‧‧The second module

78‧‧‧Protruding pattern

80‧‧‧Micropass holes

82‧‧‧ cavity

84‧‧‧ first part

86‧‧‧Second part

88‧‧‧Second insulation

90‧‧‧ photoresist layer

92‧‧‧Second microvia

94‧‧‧First photoresist layer

96‧‧‧ Third conductive layer

98‧‧‧Second photoresist layer

100‧‧‧fourth conductive layer

102‧‧‧Second micro-through or vertical column

104‧‧‧Second insulation

106‧‧‧Second conductive film layer

108‧‧‧ Third photoresist layer

110‧‧‧ fifth conductive layer

112‧‧‧ cavity

114‧‧‧ first part

116‧‧‧ second part

118‧‧‧metal foil; conductive film layer; first conductive film layer or line; metal layer

120‧‧‧metal layer; conductive film layer

122‧‧‧Support layer

Simple illustration

The following detailed description of the preferred embodiments of the invention will be better understood The invention is illustrated by way of example and not limitation. It should be understood that the drawings are not drawn to scale and

1 to 4 are enlarged cross-sectional views showing a method of forming a substrate for a semiconductor package in accordance with an embodiment of the present invention; and Figs. 5 and 6 show an enlarged cross section of a method of packaging a semiconductor wafer with the substrate of Fig. 4. Figure 7 is an enlarged cross-sectional view showing a substrate for a semiconductor package in accordance with another embodiment of the present invention; Figure 8 is an enlarged cross-sectional view showing a semiconductor package formed by the substrate of Figure 7; 10 is an enlarged cross-sectional view showing another embodiment of a method of forming a substrate for a semiconductor package; FIG. 11 is an enlarged cross-section of a semiconductor package formed by the substrate of FIG. FIG. 12 and FIG. 13 are enlarged cross-sectional views showing still another embodiment of a method of forming a substrate for a semiconductor package; FIG. 14 is an enlarged cross-sectional view showing a semiconductor package formed by the substrate of FIG. 13; 15 to 21 are enlarged cross-sectional views showing a method of forming a substrate for a semiconductor package in accordance with another embodiment of the present invention; and FIG. 22 is an enlarged cross-sectional view showing a semiconductor package formed by the substrate of FIG. 21; 23 to 27 are enlarged cross-sectional views showing a method of forming a substrate for a semiconductor package in accordance with still another embodiment of the present invention; and FIG. 28 is an enlarged cross-sectional view showing a semiconductor package formed by the substrate of FIG. 27; 29 to 31 are enlarged cross-sectional views showing a method of forming a substrate for a semiconductor package in accordance with still another embodiment of the present invention; and FIG. 32 is an enlarged view of a substrate for a semiconductor package in accordance with another embodiment of the present invention. Cross-sectional view; FIG. 33 is an enlarged cross-sectional view showing a semiconductor package formed by the substrate of FIG. 31; FIGS. 34 to 36 are diagrams showing formation of a semiconductor according to still another embodiment of the present invention. An enlarged cross-sectional view of a package method of the base; FIG. 37 to the base line of Figure 36 forms one of a semiconductor package in an enlarged cross-sectional view; FIG. 38 according to one embodiment of the system for a semiconductor package according to another embodiment of the present invention, An enlarged cross-sectional view of one of the outer mats of the base; FIGS. 39 to 42 are enlarged cross-sectional views showing a method of forming a conductive thin film layer on the insulating layer according to an embodiment of the present invention; and FIGS. 43 and 44 show the basis Another embodiment of the invention is an enlarged cross-sectional view of a method of forming a conductive thin film layer on an insulating layer.

Detailed description of the invention

The detailed description of the present invention is intended to be illustrative of the preferred embodiments of the present invention It is to be understood that the same or equivalent functions can be achieved by various embodiments that are intended to be included within the scope of the invention. In the drawings, like elements are used to denote like elements.

1 through 4 are enlarged cross-sectional views showing a method of forming a substrate 10 for a semiconductor package in accordance with an embodiment of the present invention.

Referring now to Figure 1, a carrier 12 is provided and a plurality of outer pads 14 are formed on the carrier 12, and the outer pads 14 formed on the carrier 12 define a first conductive layer. In the illustrated embodiment, a first or bottom finishing layer 15 is formed on the carrier 12 prior to forming the outer pads 14. In another embodiment, the underlying layer 15 can be formed upon completion of the semiconductor packaging process after removal of the carrier 12.

The carrier 12 serves as a support member for one of the other components of the substrate 10 and may be constructed of any suitable material that is relatively hard and electrically conductive. For example, the carrier 12 may be composed of a single metal layer, a multi-clad metal layer or a metal finishing coating layer. For example, the carrier 12 can be a steel or copper (Cu) plate. many A number of grooves (not shown) may be preformed on the carrier 12.

In the illustrated embodiment, a light is formed on the carrier 12. The resist layer 16 and the photoresist layer 16 are patterned to form a plurality 18 in the photoresist layer 16, and the first conductive layer is formed on the carrier 12. One or more metal layers are deposited in the openings 18 formed in the photoresist layer 16 to form the first conductive layer.

In an embodiment, the first conductive layer is used by using the light The resist layer 16 is formed as a mask plating. For example, a single metal layer of copper (Cu) may be deposited in the openings 18. Alternatively, for example, gold (Au) and nickel (Ni), followed by a plurality of metal layers of copper (Cu) may be deposited in the openings 18.

Referring to FIG. 2 below, the photoresist layer 16 is removed and a molding is performed. Operating to form a first insulating layer 20 on the carrier 12 in a molding compound 22. As shown in FIG. 2, the first conductive layer is sealed by the first insulating layer 20 and buried in the first insulating layer 20. A first insulating layer 20 formed on the carrier 12 covers the first conductive layer.

The molding operation can be carried out by an injection, transfer or a compression molding process. The molding compound 22 can be an epoxy resin compound.

Referring to FIG. 3, a portion of the first insulating layer 20 is removed after the molding operation to expose one surface 24 of the underlying conductive layer. A conductive thin film layer 26 is formed on the first insulating layer 20 and the first conductive layer. In this embodiment, the conductive thin film layer 26 is a conductive seed layer.

A portion of the first insulating layer 20 can be removed by a mechanical polishing or a polishing process, leaving a top of the first conductive layer that is completely exposed and substantially flush with the top surface of the first insulating layer 20. surface.

The conductive thin film layer 26 may be composed of copper (Cu) and may be Electrical procedures are formed.

Referring to FIG. 4, a die is formed on the first conductive layer. Pad 28, a plurality of bond pads 30 and a plurality of conductive traces 32, and the die pad 28, the bond pads 30, and the conductive traces 32 formed on the first conductive layer define a second conductive layer. In the illustrated embodiment, a second or top finishing layer 34 is formed on the second conductive layer. The resulting substrate 10 can be used to package a semiconductor wafer.

The second conductive layer is electrically connected to the first conductive layer. in In the illustrated embodiment, the second conductive layer is formed on the first conductive layer and the first insulating layer 20, protruding and overlapping the first insulating layer 20.

The second conductive layer can use an additive or semi-additive method and a subtraction A de-form is formed on the first conductive layer.

In the addition or semi-addition method, a first photoresist layer (not shown) It is formed on the conductive thin film layer 26 and then patterned to expose the conductive thin film layer 26. The second conductive layer is then formed by using the patterned second photoresist layer as a mask plating. The second conductive layer may be formed of a single metal or multiple metal layer. In an embodiment, the second conductive layer is formed of copper (Cu). After forming the second conductive layer, the patterned second photoresist layer is removed. Then, the exposed portion of the conductive thin film layer 26 is removed, for example, by chemical etching.

In the subtractive method, electroplating on the conductive thin film layer 26 A metal layer is formed. The metal layer can be formed from a single metal or multiple metal layer. In an embodiment, the metal layer is formed of copper (Cu). Next one A second photoresist layer (not shown) is formed over the metal layer and patterned to expose the metal layer. The metal layer and the exposed portion of the conductive thin film layer 26 are removed to form the second conductive layer. This can be achieved by chemical etching. Once this is done, the patterned second photoresist layer is removed.

The top finishing layer 34 can be made of nickel (Ni), palladium (Pd) and gold (Au) One or more of them are plated to form on the second conductive layer.

As will be appreciated by those of ordinary skill in the art, 1 through 4 illustrate an embodiment of a method of forming a substrate 10 for a semiconductor package. Other embodiments are described below. As shown in FIG. 4, the substrate 10 thus formed includes a carrier 12. A plurality of outer pads 14 are formed on the carrier 12, and the outer pads 14 formed on the carrier 12 define a first conductive layer. A first insulating layer 20 is formed on the carrier 12 by a molding compound 22. The first conductive layer is buried in the first insulating layer 20. A die pad 28, a plurality of bond pads 30 and a plurality of conductive traces 32 are formed on the first conductive layer and define a second conductive layer. A conductive thin film layer 26 is formed on the first conductive layer and at least partially on the first insulating layer 20. In the illustrated embodiment, the conductive thin film layer 26 is connected between the first and second conductive layers and between portions of the first insulating layer 20 and the second conductive layer. In this embodiment, the substrate 10 also includes a first or bottom finishing layer 15 connected between the carrier 12 and the first conductive layer and a second surface formed on one of the top surfaces of the second conductive layer. Or top finishing layer 34.

After the method for the substrate 10 of the semiconductor package has been described, A method of packaging a semiconductor wafer 36 with the substrate 10 will be described below with reference to FIGS.

Referring to FIG. 5, the base 10 of FIG. 4 is disposed as shown in the drawing. The semiconductor wafer 36 is attached to the die pad 28 of the substrate 10 with an adhesive 38. The semiconductor wafer 36 is then electrically connected to the bond pads 30 of the substrate 10 by a plurality of metal lines 40. Then, the semiconductor wafer 36, the metal wires 40, and the bonding pads 30 of the substrate 10 are sealed with a sealing material 42.

The semiconductor wafer 36 can be any type of circuit, for example, A bit signal processor (DSP) or a special function circuit, and is not limited to a special technology such as a complementary metal oxide semiconductor (CMOS), or generated by any special wafer technology. The semiconductor wafer 36 can have an active surface on one side and an inactive surface on the opposite side. The active surface of the semiconductor wafer 36 is remote from the die pad 28 and includes a plurality of input and output (I/O) pads (not shown). The non-active surface of the semiconductor wafer 36 is attached to the adhesive 38.

In an embodiment, the adhesive 38 can be a die attach ring An oxyresin, and the die attach epoxy resin is dispensed in one of the die attach pad regions of the substrate 10 prior to die placement and hardening.

The metal lines 40 are electrically connected to the semiconductor wafer 36. In and out (I/O) pads and corresponding bond pads 30, thereby bonding the semiconductor wafer 36 and the bond pads 30. The metal lines 40 may be comprised of gold (Au), copper (Cu), or other electrically conductive materials known in the art and commercially available.

The sealing material 42 forms a second insulating layer on the substrate 10 and The pad 28 layer, the wire layers 30 and 32, the semiconductor die 36, the epoxy 38, and the electrical connectors 40 are sealed. The dielectric layer 42 can be compressed, Transfer or injection molding is formed on the substrate 10. The sealing material 42 can comprise a conventional commercially available molding material, such as an epoxy molding compound.

Referring to FIG. 6, the carrier 12 of the substrate 10 is removed for exposure. The first conductive layer. In this embodiment, when the carrier 12 is removed, the wires and the bottom surface of the die attach pad are exposed. The carrier 12 can be removed by an etching process or a wet etching process.

Due to the molding operation for forming the first insulating layer 20, Molding compound 22 fills the sides of the outer pads 14 to prevent leakage of wet chemicals at the interface between the molding compound 22 and the outer pads 14. Advantageously, this helps prevent the edges of the outer pads 14 from being corroded by the wet chemicals and which in turn helps maintain the outer dimensions of the outer pads 14.

As can be seen from FIG. 6, the semiconductor package 44 thus formed includes A plurality of outer pads 14 defining a first conductive layer and a first insulating layer 20 are formed by a molding compound 22. The first conductive layer is buried in the first insulating layer 20. A conductive thin film layer 26 is formed on the first conductive layer and at least partially on the first insulating layer 20. A die pad 28, a plurality of bond pads 30 and a plurality of conductive traces 32 are formed on the first conductive layer and define a second conductive layer. A semiconductor wafer 36 is attached to the die pad 28 and a plurality of metal lines 40 electrically connect the semiconductor die 36 and the bond pads 30. A sealing material 42 seals the semiconductor wafer 36, the metal lines 40, and the bonding pads 30.

The sealing material 42 may be dielectric or used to form the substrate 10 or The insulating layer is composed of the same material or molding compound. Advantageously, this helps to reduce or prevent stress caused by the mismatch of the properties of the material to the semiconductor package 44.

Although a single package unit is shown in Figures 1 to 6, it should be It is explained that the substrate 10 is not limited to a single package process and can be used to simultaneously form a plurality of semiconductor packages 44. In such embodiments, the combined frame can be segmented to form a plurality of individual packages.

Please refer to FIG. 7 for another embodiment of the present invention. An enlarged cross-sectional view of a substrate 10 for one of the semiconductor packages. The substrate 10 includes a carrier 12 and an outer die pad 46 and a plurality of outer pads 14 formed on the carrier 12. The outer die pads 46 and the outer pads 14 formed on the carrier 12 define a first conductive layer. A first insulating layer 20 is formed on the carrier 12 by a molding compound 22. The first conductive layer is buried in the first insulating layer 20. A plurality of bond pads 30 and a plurality of conductive traces 32 are formed on the first conductive layer. The bond pads 30 and the conductive traces 32 formed on the first conductive layer define a second conductive layer.

The base body 10 of FIG. 7 and the base body of the foregoing embodiment are not structurally The base 10 of Fig. 7 is formed by a die pad.

Referring to FIG. 8 below, one of the substrates 10 shown in FIG. 7 is shown. An enlarged cross-sectional view of semiconductor package 44. The semiconductor package 44 includes an outer die pad 46 and a plurality of outer pads 14, and the outer die pads 46 and the outer pads 14 define a first conductive layer. The semiconductor package 44 also includes a first insulating layer 20 formed of a molding compound 22. The first conductive layer is buried in the first insulating layer 20. A plurality of bond pads 30 and a plurality of conductive traces 32 are formed on the first conductive layer, and the bond pads 30 and the conductive traces 32 formed on the first conductive layer define a second conductive layer. A semiconductor wafer 36 is attached to the outer die pad 46 and a plurality of metal wires 40 are electrically connected The semiconductor wafer 36 and the bonding pads 30. A sealing material 42 seals the semiconductor wafer 36, the metal lines 40, and the bonding pads 30.

The sealing material 42 may be dielectric or used to form the substrate 10 or The insulating layer is composed of the same material or molding compound. Advantageously, this helps to reduce or prevent stress caused by the mismatch of the properties of the material to the semiconductor package 44.

Hereinafter, in part, from FIG. 4 and further referring to FIGS. 9 and 10, Another embodiment of a method of forming the substrate 10 for a semiconductor package will be described below.

Referring to FIG. 9, after removing some exposed portions of the conductive film layer 26, a second or continuous insulating layer 48 is formed on the first insulating layer 20. In this embodiment, the second insulating layer 48 seals the second conductive layer and is formed of a solder masking material, such as an epoxy solder masking material. In this embodiment, the conductive thin film layer 26 is a conductive seed layer.

Referring to FIG. 10, the second insulating layer 48 is patterned to expose portions of the second conductive layer and form a second or top finishing layer on the exposed portions of the second conductive layer. 34.

The substrate 10 thus formed further includes a second insulating layer 48 formed of a solder masking material and formed on the first insulating layer 20 and a top finishing layer on the exposed portions of the second conductive layer 34. As shown in FIG. 10, the second insulating layer 48 covers the second conductive layer and covers a portion of the top surface of the second conductive layer.

Referring to FIG. 11, a semiconductor package 44 formed by the substrate 10 of FIG. 10 is shown. The semiconductor package 44 includes a plurality of outer pads 14, And the outer pads 14 define a first conductive layer. The first conductive layer is buried in a first insulating layer 20, and the first insulating layer 20 is formed by a molding compound 22. A conductive thin film layer 26 is formed on the first conductive layer and at least partially on the first insulating layer 20. A die pad 28, a plurality of bond pads 30 and a plurality of conductive traces 32 are formed on the first conductive layer and define a second conductive layer. A second insulating layer 48 is formed on the first insulating layer 20 and a top finishing layer 34 is formed on portions of the second conductive layer. A semiconductor wafer 36 is attached to the die pad 28 and a plurality of metal lines 40 electrically connect the semiconductor die 36 and the bond pads 30. A sealing material 42 seals the surface of the semiconductor wafer 36, the bonding pads 30, and the second insulating layer 48.

The sealing material 42 may be dielectric or used to form the substrate 10 or The insulating layer is composed of the same material or molding compound. Advantageously, this helps to reduce or prevent stress caused by the mismatch of the properties of the material to the semiconductor package 44.

Advantageously, the second insulating layer 48 covers the exposed lines 32. Masking any unwanted lines 32 and enhancing the adhesion of the lines 32 to the molding compound 22.

Hereinafter, in part, from FIG. 4 and further referring to FIGS. 12 and 13, Another embodiment of a method of forming the substrate 10 for a semiconductor package will be described below.

Referring to FIG. 12, after removing the conductive film layer 26 After the exposed portions, a second or continuous insulating layer 50 is formed on the first insulating layer 20. In this embodiment, the second insulating layer 50 seals the second conductive layer The layer is formed of a solder masking material, such as an epoxy solder masking material. The molding compound can be similar to the molding compound used to form the first insulating layer 20. The second insulating layer 50 can be formed by an injection or compression molding process. In this embodiment, the conductive thin film layer 26 is a conductive seed layer.

Referring to FIG. 13 below, one part of the second insulating layer 50 is removed. The portion is exposed to expose one surface of the first conductive layer and a second or top finishing layer 34 is formed on the exposed surface of the second conductive layer. The portion of the second insulating layer 50 can be removed by a mechanical grinding or a polishing process.

The substrate 10 thus formed further comprises a molding compound material And forming a second insulating layer 50 on the first insulating layer 20 and a top finishing layer 34 on the exposed surface of the second conductive layer. As shown in FIG. 13, one of the top surfaces of the second conductive layer is completely exposed and substantially flush with a top surface of the second insulating layer 50.

Referring to FIG. 14 below, the substrate 10 of FIG. 13 is formed. A semiconductor package 44. The semiconductor package 44 includes a plurality of outer pads 14, and the outer pads 14 define a first conductive layer. The first conductive layer is buried in a first insulating layer 20, and the first insulating layer 20 is formed by a molding compound 22. A conductive thin film layer 26 is formed on the first conductive layer and at least partially on the first insulating layer 20. A die pad 28, a plurality of bond pads 30 and a plurality of conductive traces 32 are formed on the first conductive layer and define a second conductive layer. A second insulating layer 50 is formed on the first insulating layer 20 and a top finishing layer 34 is formed on one surface of the second conductive layer. A semiconductor wafer 36 is attached to the die pad 28 and a plurality of metal wires 40 electrically connect the semiconductor die 36 and the bonding Pad 30. A sealing material 42 seals the surface of the semiconductor wafer 36, the bonding pads 30, and the second insulating layer 50.

The sealing material 42 may be dielectric or used to form the substrate 10 or The insulating layer is composed of the same material or molding compound. Advantageously, this helps to reduce or prevent stress caused by the mismatch of the properties of the material to the semiconductor package 44.

15 to 21 show a method according to another embodiment of the present invention. An enlarged cross-sectional view of a method of forming a substrate for a semiconductor package.

Referring now to Figure 15, a carrier 12 is provided and a plurality of outer pads 14 are provided. The outer pads 14 formed on the carrier 12 and formed on the carrier 12 define a first conductive layer. The carrier can be a steel or copper plate. In the illustrated embodiment, a first or bottom finishing layer 15 is formed on the carrier 12 prior to forming the outer pads 14. In another embodiment, the first or bottom finishing layer 15 can be formed upon completion of the semiconductor packaging process after removal of the carrier 12.

In the illustrated embodiment, a light is formed on the carrier 12. The resist layer 16 and the photoresist layer 16 are patterned to form a plurality 18 in the photoresist layer 16, and the first conductive layer is formed on the carrier 12. One or more metal layers are deposited in the openings 18 formed in the photoresist layer 16 to form the first conductive layer.

Referring to FIG. 16, the first conductive layer and the photoresist layer are respectively A second photoresist layer 52 is formed on 16. The second photoresist layer 52 is then patterned to form a plurality of micro vias 54 extending through the second photoresist layer 52 and exposing portions of a top surface of the first conductive layer Share. The first conductive layer is used by using the patterned second photoresist layer 52 as a mask. Depositing a single metal such as copper (Cu) or a plurality of metal layers such as copper (Cu), nickel (Ni), palladium (Pd), and gold (Au), forming a plurality of micro-passes on the outer pads 14. Hole 56. In this embodiment, the microvias 56 define a second conductive layer. As can be seen in Figure 16, each microvia 56 has a diameter that is less than one of the width or diameter of one of the outer pads 14.

Please refer to FIG. 17 below, in which the micro vias 56 are formed. After the outer pad 14 is over, the first and second photoresist layers 16 and 52 are removed. The microvias 56 are thus formed on the outer pads 14 prior to performing a molding operation to form the first insulating layer 20 on the carrier 12.

Referring to FIG. 18, a molding operation is performed to make a mold. The compound 22 forms a first insulating layer 20 on the carrier 12. As shown in FIG. 18, after the molding operation, the first and second conductive layers are sealed by the first insulating layer 20 and the micro vias 56 are buried in the first insulating layer 20.

In the illustrated embodiment, the molding operation includes forming the The carrier 12 of the first conductive layer is placed in a cavity 58 defined by a first mold portion 60 and a second mold portion 62. The cavity 58 is filled by injection molding a liquid molding compound 22. The molding compound 22 is injected into the cavity 58 in a liquid or molten state at a high temperature and a high pressure to completely fill the cavity 58. The molding compound 22 is then hardened and cured to form the first insulating layer 20 on the carrier 12.

The molding compound 22 is preferably a polymeric thermoset material. or A polymeric thermoplastic material can also be used. In this embodiment, the molding compound 22 comprises a polymer resin and one or more fillers. The one or more fillers are distributed throughout the resin matrix In the volume. The resin may be epoxy based or acrylic based and the one or more fillers may be ceria, ceramic and/or glass filler. In one embodiment, the molding compound 22 comprises one or more fillers between about 70 weight percent and about 95 weight percent. In the same or a different embodiment, the molding compound 22 has a coefficient of thermal expansion between about 5 and about 15 parts per million (ppm/°C) per degree Celsius.

Although an injection molding program is shown in FIG. 18, it belongs to It should be understood by those of ordinary skill in the art that the invention is not limited to the molding process used. For example, in another embodiment, the first insulating layer 20 can be formed by a compression molding process.

Advantageously, a molding operation is used to form the base of the substrate 10 The body can have a high aspect ratio, for example, an aspect ratio greater than one (1), sealing the microvias 56 without damaging the elongated structure of the microvias 56. The molding compound 22 in a liquid or molten state readily conforms to the high aspect ratio characteristics formed on the carrier 22. The cavity 58 defines the molding compound 22 within the desired area to be sealed. The molding compound 22 is hardened and cured to form the first insulating layer 20 before the carrier 12 having the first insulating layer 20 is removed by the mold.

Please refer to FIG. 19 below, in which the molding operation is guided in a lower direction. The electrical layer, in this embodiment, after removing one of the surfaces of the second conductive layer, removes a portion of the first insulating layer 20. A conductive thin film layer 26 is formed on the first insulating layer 20 and the second conductive layer before forming a die pad, a plurality of bonding pads and a plurality of conductive lines on the second conductive layer.

After a molding operation by a mechanical grinding or a polishing process The portion of the first insulating layer 20 is removed. Advantageously, this flattens the height of the microvias 56 and creates a level that is flush with the surface of the first insulating layer 20 for subsequent processing. In this embodiment, the thickness of the first insulating layer 20 is equal to the total height of the outer pads 14 and the micro vias 56.

Due to the nature of the molding process, after the molding operation, the The one or more fillers 64 may remain in the resin matrix in a manner that is least exposed on the surface of the first insulating layer 20 and after the molding operation, the surface of the first insulating layer 20 is mainly a resin. 66. However, when the surface of the first insulating layer 20 is flush with the surface of the second conductive layer, the characteristics of the surface of the first insulating layer 20 are changed. After removing one portion of the first insulating layer 20 by a mechanical polishing or a polishing process after the molding operation, the one or more fillers 64 are exposed on the surface of the first insulating layer 20. The surface of the first insulating layer 20 thus includes a filler region interspersed within the resin region. This is advantageous because the exposed filler surfaces provide better adhesion than the surface of the resins. The ratio of the surface area of the filler to the surface area of the resin depends on the filler content of the molding compound 22. The surface area of the filler exposed on the surface of the first insulating layer 20 for the molding compound 22 having one of the filler contents between about 70% (%) and about 95% (%) Between about 50% and about 80% and the remainder is the surface area of the resin.

The conductive thin film layer 26 can be formed by an electroless deposition process and It may be composed of copper (Cu) or nickel (Ni). The surface of the first insulating layer 20 and the surface of the second conductive layer may be chemically treated to increase adhesion to the conductive thin film layer 26 prior to depositing the conductive thin film layer 26. This can be utilized Roughening a surface of the first insulating layer 20 and/or the second conductive layer (for the one or more fillers 64 and the first conductive layer) before forming the conductive thin film layer 26, and forming The conductive film layer 26 chemically activates one or both of the plurality of surface bonds (for the resin 66) of the first insulating layer 20. Different chemical solutions can be used to treat the surface of the filler, the surface of the resin, and the surface of the second conductive layer. After deposition, the conductive film layer 26 is adhered to the surface of the resin and the surface of the second conductive layer. In comparison, the conductive film layer 26 adheres very well to the surface of the filler and the surface of the second conductive layer, but does not adhere well to the surface of the resin. Due to the high filler content of the molding compound 22, the conductive film layer 26 is mostly bonded to the surface of the filler and thus creates a strong adhesion between the conductive film layer 26 and the first insulating layer 20.

Referring to FIG. 20, a crystal is formed on the second conductive layer. The pad 28, the plurality of bond pads 30 and the plurality of first conductive traces 32 define a third conductive layer. As can be seen from FIG. 20, the microvias 56 electrically connect the outer pads 14 and the third conductive layer. In this embodiment, a second or top finishing layer 34 is formed on the exposed surface of the third conductive layer. In other embodiments, one (1) or more die pads 28 may be formed.

Forming a third photoresist layer 68 on the conductive thin film layer 26 And patterning the third photoresist layer 68 to expose the conductive thin film layer 26 to form the third conductive layer. Using the patterned third photoresist layer 68 as a mask, the third conductive layer can then be formed on the conductive thin film layer 26 by an electroplating deposition process. The third conductive layer may be composed of a single metal such as copper (Cu) or a plurality of metal layers such as copper (Cu), nickel (Ni), palladium (Pd), and gold (Au). form.

Forming a fourth photoresist layer 70 and patterning the fourth photoresist The layer 70 is formed to expose a selected portion of the third conductive layer, and the second or top finishing layer 34 may be formed on the third conductive layer. Electroplating with one or more metal layers of nickel (Ni), palladium (Pd), and gold (Au) by using the fourth photoresist layer 70 as a mask, and then forming the second or the third conductive layer Top finishing layer 34.

Referring to FIG. 21 below, the patterned third and fourth lights are removed. Resistivity layers 68 and 70. For example, the exposed portion of the conductive thin film layer 26 is also removed by chemical etching.

As can be seen from FIG. 21, the conductive thin film layer 26 is connected to the third Between the conductive layer and the first insulating layer 20. The conductive film layer 26 provides a strong adhesion to the surface of the filler and thus the first insulating layer 20. Therefore, the die pad 28 and/or the conductive trace 32 also adheres well to the first insulating layer 20, thereby reducing the gap between the third conductive layer and the first insulating layer 20 in subsequent processes or applications. Stripping and increasing the reliability of the resulting package.

As shown in FIG. 21, the substrate 10 thus formed includes a carrier 12. And a plurality of outer pads 14 formed on the carrier 12, and the outer pads 14 formed on the carrier 12 define a first conductive layer. A plurality of microvias 56 are formed in the outer pads 14, and the microvias 56 define a second conductive layer. A first insulating layer 20 is formed on the carrier 12 by a molding compound 22. The first and second conductive layers are buried in the first insulating layer 20. A conductive thin film layer 26 is formed on the second conductive layer and at least partially on the first insulating layer 20. A die pad 28, a plurality of bond pads 30, and a plurality of conductive lines 32 Formed on the second conductive layer and defining a third conductive layer. The micro vias 56 electrically connect the outer pads 14 and the third conductive layer. In the illustrated embodiment, the substrate 10 also includes a first or bottom finishing layer 15 connected between the carrier 12 and the first conductive layer and a second or a surface formed on one of the third conductive layers. Top finishing layer 34.

In this embodiment, the first conductive layer is formed by the outer pads 14 is defined and the second conductive layer is defined by the vertical pillars or microvias 56. The first insulating layer 20 is formed on the carrier 12 and covers the first and second conductive layers. The top surface of one of the second conductive layers is completely exposed and substantially flush with the top surface of the first insulating layer 20. The third conductive layer is formed on the first insulating layer 20. The third conductive layer is electrically connected to the first conductive layer through the second conductive layer and extends and overlaps over the first insulating layer 20. The third conductive layer defines a wiring line for forming a circuit of the substrate 10.

In this embodiment, the substrate also includes a second connection The conductive thin film layer 26 is interposed between the third conductive layer and the first insulating layer 20 and the third conductive layer. The bottom finishing layer 15 is connected between the first conductive layer and the carrier 12 and the top finishing layer 34 is formed on a top surface of the third conductive layer.

Advantageously, the microvias 56 have a smaller diameter than the outer pads 14, and by providing the microvias 56 to the outer pads, the density and thus the connectivity of the conductive traces 32 can be increased.

Referring to Fig. 22, a semiconductor package 44 is formed from the substrate of Fig. 21. The semiconductor package 44 includes a plurality of outer pads 14 and The outer pads 14 define a first conductive layer. A plurality of microvias 56 are formed on the outer pads 14, and the microvias 56 define a second conductive layer. The first and second conductive layers are buried in a first insulating layer 20, and the first insulating layer 20 is formed by a molding compound 22. A conductive thin film layer 26 is formed on the second conductive layer and at least partially on the first insulating layer 20. A die pad 28, a plurality of bond pads 30, and a plurality of conductive traces 32 are formed on the second conductive layer and define a third conductive layer. The micro vias 56 electrically connect the outer pads 14 and the third conductive layer. A finishing layer 34 is formed on one surface of the third conductive layer. A semiconductor wafer 36 is attached to the die pad 28 and a plurality of metal lines 40 electrically connect the semiconductor die 36 and the bond pads 30. A sealing material 42 seals the semiconductor wafer 36, the metal lines 40, and the bonding pads 30. In the illustrated embodiment, a bottom finishing layer 15 is formed on one of the bottom sides of the outer pads 14. In other embodiments, the semiconductor wafer 36 can be flip-chip bonded to the substrate 10.

The sealing material 42 may be dielectric or used to form the substrate 10 or The insulating layer is composed of the same material or molding compound. Advantageously, this helps to reduce or prevent stress caused by the mismatch of the properties of the material to the semiconductor package 44.

Another embodiment of a method of forming a substrate 10 for a semiconductor package will be described below with reference to FIG. 15 and with further reference to FIGS. 23 through 27.

Referring to FIG. 23, after the outer pads 14 are formed, the photoresist layer 16 is removed and the first conductive layer is defined on the carrier 12. By placing the carrier 12 having the first conductive layer on a cavity 72 defined by a first die portion 74 and a second die portion 76, a molding operation is then performed to A first insulating layer 20 is formed on the carrier 12 by a molding compound 22. As can be seen from Figure 23, the mold has a raised pattern 78 in the first mold portion 74 and defines the mold cavity 72 when closed. When the first mold portion 74 is fabricated, the protrusion pattern 78 can be formed by computer numerical control (CNC) grinding. In another embodiment, the raised pattern 78 can be a central member interposed between the first and second mold portions 74 and 76. The carrier 12 on which the first conductive layer is formed is sandwiched between the first and second mold portions 74 and 76 and in the cavity 72, and the protrusion pattern 78 contacts the first conductive layer. The first conductive layer may first be planarized by mechanical polishing, polishing or stamping to achieve substantial flatness, thereby reducing contactlessness between the raised pattern 78 and the first conductive layer. The molding compound 22 is injected into the cavity 72 at a high temperature and a high pressure in a liquid or molten state, and the molded object 22 conforms to the shape of the cavity 72 having the protrusion pattern 78. When the molding compound 22 is hardened, the first conductive layer is buried in the first insulating layer 20.

Please refer to FIG. 24 below, in which the liquid molding compound 22 has been hard After forming a solid state to form a first dielectric or insulating layer 20 having a plurality of through-mold vias or microvias 80, the carrier 12 having the first insulating layer 20 formed therefrom is removed from the cavity 72. The microvias 80 define the vertical contact posts 56 in the first insulating layer 20. The carrier 12 on which the first insulating layer 20 is formed may be subjected to an extended high temperature period after being removed from the cavity 72 to completely harden the molding compound 22.

As can be seen from Figures 23 and 24, there is a corresponding When a mold portion 74 of one of the micro-via holes 80 in the insulating layer 20 is molded, the first insulating layer 20 is formed in the first insulating layer 20 for forming the A plurality of microvias 80 of the vertical contact posts or microvias 56 are. In this manner, a first insulating layer 20 can be simultaneously formed on the first conductive layer and at least one of the microvias 80 in the first insulating layer 20 exposing the first conductive layer.

In another embodiment, the first molding may be provided at the first The protrusion pattern 78 in the mold portion 74. Advantageously, the cost is reduced by reducing the materials used, which reduces manufacturing costs.

Although an injection molding program is shown in FIG. 23, it belongs to It should be understood by those of ordinary skill in the art that the invention is not limited to the molding process used. For example, in another embodiment, the first insulating layer 20 can be formed by a compression or transfer molding.

Referring to FIG. 25, the first insulating layer 20 will be described below. Another method of forming the microvias 80 therein. According to FIG. 15, the photoresist layer 16 is removed after the outer pads 14 are formed and the first conductive layer is defined on the carrier 12. A molding operation is performed on the carrier 12 by placing the carrier 12 on which the first conductive layer is formed in a cavity 82 defined by a first die portion 84 and a second die portion 86. A molding compound 22 forms the first insulating layer 20. The molding compound 22 is injected into the cavity 82 at a high temperature and a high pressure in a liquid or molten state, and the molding compound 22 conforms to the shape of the cavity 82. When the molding compound 22 is hardened, the first conductive layer is buried in the first insulating layer 20.

Referring again to Figure 24, the liquid molding compound 22 has hardened. The carrier 12 formed with the first insulating layer 20 is removed from the cavity 82 by a cavity 82 and then formed in the first insulating layer 20 for formation by one of laser drilling and mechanical drilling. The microvia or vertical contact column Most of the micro-through holes 80 of 56.

Please refer to FIG. 26 below, after forming the micro-through holes 80 A conductive thin film layer 26 is formed on the first conductive layer and the first insulating layer 20. A second photoresist layer 52 is then formed and patterned on the conductive thin film layer 26 to expose the conductive thin film layer 26. A plurality of microvias 56, a die pad 28, a plurality of bond pads 30, and a plurality of conductive traces 32 are formed on the first conductive layer and define a second conductive layer. The second conductive layer is formed by electroplating on the conductive thin film layer 26 using the patterned second photoresist layer 52 as a mask.

As can be seen from FIG. 26, the second is formed when the second conductive layer is formed The conductive layer fills the microvias 80 to form a vertical contact post 56 for connecting the first conductive layer. The second conductive layer also defines the wiring lines 32 for forming the circuitry of the substrate 10. The second conductive layer can be formed by plating a single metal such as copper (Cu) or a plurality of metal layers such as copper (Cu), nickel (Ni), palladium (Pd), and gold (Au).

Alternatively, the second conductive layer may be formed on the first insulating layer 20. Prior to the layer, the microvias 80 are filled with a conductive material. The conductive material can be injected or printed into the microvias 80. The conductive material may be, for example, a conductive paste of tin (Sn) or silver (Ag) paste.

Referring to FIG. 27, the patterned second photoresist layer 52 is removed. And, for example, the exposed portion of the conductive thin film layer 26 is also removed by chemical etching. In the illustrated embodiment, a second or top finishing layer 34 is formed on the selected surface of the second conductive layer by a photolithography process.

As shown in FIG. 27, the substrate 10 thus formed includes a carrier 12. And a plurality of outer pads 14 formed on the carrier 12, and the outer pads 14 formed on the carrier 12 define a first conductive layer. A first insulating layer 20 is formed on the carrier 12 with a molding compound 22 such that the first conductive layer is buried in the first insulating layer 20. A conductive thin film layer 26 is formed on the first conductive layer and at least partially on the first insulating layer 20. A plurality of microvias 56, a die pad 28, a plurality of bond pads 30, and a plurality of conductive traces 32 are formed on the first conductive layer and define a second conductive layer. In the illustrated embodiment, the substrate 10 also includes a first or bottom finishing layer 15 connected between the carrier 12 and the first conductive layer and a second or a surface formed on one of the second conductive layers. Top finishing layer 34.

In this embodiment, the second conductive layer is formed in the first The conductive layer is electrically connected to the first conductive layer through the plurality of vertical pillars 56. The second conductive layer extends over and overlies the first insulating layer 20 and defines the wiring lines 32 for forming the circuitry of the substrate 10. The conductive thin film layer 26 of this embodiment is connected between the first and second conductive layers or between the first insulating layer 20 and the second conductive layer.

Referring to FIG. 28 below, one of the substrates formed in FIG. 27 is shown. Semiconductor package 44. The semiconductor package 44 includes a plurality of outer pads 14, and the outer pads 14 define a first conductive layer. The first conductive layer is buried in a first insulating layer 20, and the first insulating layer 20 is formed by a molding compound 22. A conductive thin film layer 26 is formed on the first conductive layer and at least partially on the first insulating layer 20. A plurality of microvias 56, a die pad 28, a plurality of bond pads 30, and a plurality of conductive traces 32 are formed on the first conductive layer and define a second conductive layer. A finishing layer 34 is formed on the second conductive On one of the layers. A semiconductor wafer 36 is attached to the die pad 28 and a plurality of metal lines 40 electrically connect the semiconductor die 36 and the bond pads 30. A sealing material 42 seals the semiconductor wafer 36, the metal lines 40, and the bonding pads 30. In the illustrated embodiment, a bottom finishing layer 15 is formed on one of the bottom sides of the outer pads 14.

The sealing material 42 may be dielectric or used to form the substrate 10 or The insulating layer is composed of the same material or molding compound. Advantageously, this helps to reduce or prevent stress caused by the mismatch of the properties of the material to the semiconductor package 44.

29 to 31 show a method according to still another embodiment of the present invention. An enlarged cross-sectional view of a method of forming a substrate for a semiconductor package.

Referring now to Figure 29, a carrier 12 is provided and a plurality of outer pads 14 are provided. The outer pads 14 formed on the carrier and formed on the carrier 12 define a first conductive layer. In the illustrated embodiment, a first or bottom finishing layer 15 is formed on the carrier 12 prior to forming the outer pads 14.

A molding operation is then performed to make a mold on the carrier 12. The compound 22 forms a first insulating layer 20. Due to the molding operation, the first conductive layer is buried in the first insulating layer 20. A portion of the first insulating layer 20 is removed after the molding operation to expose one surface of the first conductive layer.

An exposed surface of the first insulating layer 20 and the first conductive layer A second insulating layer 88 is formed thereon. In this embodiment, the second insulating layer 88 can be a solder mask, a molding compound, a woven fiberglass laminate or a primer. The second insulating layer 88 can be formed on the first conductive layer and the first insulating layer 20 by screen printing, spin coating or lamination. The first insulation Layer 20 and the second insulating layer 88 may be formed of materials of different properties. Preferably, the second insulating layer 88 is formed of a photoimageable material.

By lithography, laser drilling, and mechanical drilling, A plurality of microvias 54 are formed in the second insulating layer 88. As can be seen from FIG. 29, the second insulating layer 88 is patterned to form a plurality of microvias 54.

Forming a guide on the second insulating layer 88 and the first conductive layer Electrical film layer 26.

Referring to FIG. 30, a photoresist layer 90 is formed on the conductive thin film. The film layer 26 is patterned and exposed to expose the conductive film layer 26. A plurality of microvias 56, a die pad 28, a plurality of bond pads 30, and a plurality of conductive traces 32 are formed on the first conductive layer and define a second conductive layer. The second conductive layer is formed by electroplating the conductive thin film layer 26 as a mask using the patterned photoresist layer 90.

As can be seen from FIG. 30, when the second conductive layer is formed, the first The two conductive layers also fill the microvias 54 to form a plurality of vertical contact posts 56 for connecting the first conductive layer. The second conductive layer also defines the wiring lines 32 for forming the circuitry of the substrate 10. The second conductive layer can be formed by plating a single metal such as copper (Cu) or a plurality of metal layers such as copper (Cu), nickel (Ni), palladium (Pd), and gold (Au).

Alternatively, the second conductive layer may be formed on the second insulating layer 88. Prior to the layer, the microvias 80 are filled with a conductive material. The conductive material can be injected or printed into the microvias 80. The conductive material may be, for example, a conductive paste of tin (Sn) or silver (Ag) paste.

Referring to FIG. 31, the patterned photoresist layer 90 is removed and is exemplified. For example, the exposed portion of the conductive film layer 26 is also removed by chemical etching. In the illustrated embodiment, a second or top finishing layer 34 is formed on the selected surface of the second conductive layer by a photolithography process.

As shown in FIG. 27, the substrate 10 thus formed includes a carrier 12 and a plurality of outer pads 14 formed on the carrier 12, and the outer pads 14 formed on the carrier 12 define a first conductive layer. A first insulating layer 20 is formed on the carrier 12 with a molding compound 22 such that the first conductive layer is buried in the first insulating layer 20. A second insulating layer 88 is formed on the first insulating layer 20 and a plurality of microvias 54 are formed in the second insulating layer 88 to expose one surface of the first conductive layer. A conductive thin film layer 26 is formed on the first conductive layer and at least partially on the second insulating layer 88. A plurality of microvias 56, a die pad 28, a plurality of bond pads 30, and a plurality of conductive traces 32 are formed on the first conductive layer and define a second conductive layer. In the illustrated embodiment, the substrate 10 also includes a first or bottom finishing layer 15 connected between the carrier 12 and the first conductive layer and a second or a surface formed on one of the second conductive layers. Top finishing layer 34.

In this embodiment, the second insulating layer 88 is formed on the first insulating layer 20 and the first conductive layer, and the second conductive layer is formed on the first conductive layer and the second insulating layer 88. . The second conductive layer is electrically connected to the first conductive layer through the plurality of vertical pillars 56 and extends over and overlies the second insulating layer 88. The second conductive layer defines the wiring lines for forming the circuitry of the substrate 10. The conductive thin film layer 26 of this embodiment is connected between the first conductive layer and the vertical contact pillars and between the second insulating layer 88 and the second conductive layer.

Referring to FIG. 32, another embodiment of the present invention is shown. An enlarged cross-sectional view of a substrate 10 for a semiconductor package. The substrate 10 includes a carrier 12 and a plurality of outer pads 14 formed on the carrier 12, and the outer pads 14 on the carrier 12 define a first conductive layer. A plurality of first microvias 56 are formed on the outer pads 14, and the microvias 56 define a second conductive layer. A first insulating layer 20 is formed on the carrier 12 by a molding compound 22. The first and second conductive layers are buried in the first insulating layer 20. A second insulating layer 88 is formed on the first insulating layer 20 and a plurality of microvias 54 are formed in the second insulating layer 88 to expose one surface of the first conductive layer. A conductive film layer 26 is formed on the second conductive layer and at least partially on the second insulating layer 88. A plurality of second microvias 92, a die pad 28, a plurality of bond pads 30, and a plurality of conductive traces 32 are formed on the second conductive layer and define a third conductive layer. The second microvias 2 are formed in the microvias 54 and interconnect the second conductive layer and the third conductive layer. In the illustrated embodiment, the substrate 10 also includes a first or bottom finishing layer 15 connected between the carrier 12 and the first conductive layer and a second or a surface formed on one of the third conductive layers. Top finishing layer 34.

As can be seen from Figure 32, in this embodiment, a second layer of micro-pass A hole 92 is formed on the previous conductive layer.

Referring to FIG. 33 below, one of the substrates formed in FIG. 31 is shown. Semiconductor package 44. The semiconductor package 44 includes a plurality of outer pads 14, and the outer pads 14 define a first conductive layer. The first conductive layer is buried in a first insulating layer 20, and the first insulating layer 20 is formed by a molding compound 22. A second insulating layer 88 is formed on the first insulating layer 20 and is mostly micro A via hole 54 is formed in the second insulating layer 88 to expose a surface of the first conductive layer. A conductive thin film layer 26 is formed on the first conductive layer and at least partially on the second insulating layer 88. A plurality of microvias 56, a die pad 28, a plurality of bond pads 30, and a plurality of conductive traces 32 are formed on the first conductive layer and define a second conductive layer. A second or top finishing layer 34 is formed on one surface of the second conductive layer. A semiconductor wafer 36 is attached to the die pad 28 and a plurality of metal lines 40 electrically connect the semiconductor die 36 and the bond pads 30. A sealing material 42 seals the semiconductor wafer 36, the metal lines 40, and the bonding pads 30. In the illustrated embodiment, a bottom finishing layer 15 is formed on one of the bottom sides of the outer pads 14.

The sealing material 42 may be dielectric or used to form the substrate 10 or The insulating layer is composed of the same material or molding compound. Advantageously, this helps to reduce or prevent stress caused by the mismatch of the properties of the material to the semiconductor package 44.

According to FIG. 19 and further referring to FIGS. 34 to 36, the following will explain Another embodiment of a method of forming a substrate 10 for a semiconductor package.

Referring to FIG. 34, a conductive film layer 26 is formed in a shape. After forming the second conductive layer and the first insulating layer 20 on the carrier 12, a first photoresist layer 94 is formed on the conductive thin film layer 26. The first photoresist layer 94 is then patterned to expose the conductive thin film layer 26. A third conductive layer 96 is formed by plating the patterned first photoresist layer 94 as a mask on the conductive thin film layer 26. The third conductive layer 96 defines a plurality of first wiring lines and may be composed of a single metal such as copper (Cu) or a plurality of metal layers such as a combination of copper (Cu), nickel (Ni), palladium (Pd), and gold (Au). form.

Then forming on the first photoresist layer 94 and the third conductive layer 96 A second photoresist layer 98 is patterned and patterned to expose the third conductive layer 96. A fourth conductive layer 100 is formed by electroplating on the third conductive layer 96 by using the patterned second photoresist layer 98 as a mask. The fourth conductive layer 100 defines a plurality of second micro vias or vertical pillars 102 and may be composed of a single metal such as copper (Cu) or, for example, copper (Cu), nickel (Ni), palladium (Pd), and gold (Au). Most of the metal layers are combined to form.

Referring to FIG. 35, after the third conductive layer 96 is formed on the second micro vias 102, the first and second photoresist layers 94 and 98 are removed. For example, the exposed portion of the conductive thin film layer 26 is also removed by chemical etching.

A second insulating layer 104 is formed on the first insulating layer. In this embodiment, the second insulating layer 104 is composed of a molding compound material. Similar to the first insulating layer 20, the second insulating layer 104 may be formed using an exit or a compression molding process to seal the third and fourth conductive layers 96 and 100. After the molding operation, a portion of the second insulating layer 104 may be removed using a mechanical polishing or polishing process to expose one surface of the fourth conductive layer 100. Preferably, the first and second insulating layers 20 and 104 are composed of the same molding compound material.

A second conductive thin film layer 106 is formed on the second insulating layer 104 and the fourth conductive layer 100. The second conductive thin film layer 106 may be composed of copper (Cu) and may be formed by an electroless process.

A third photoresist layer 108 is then formed and patterned on the second conductive thin film layer 106 to expose the second conductive thin film layer 106. By using the patterned third photoresist layer 108 as a mask on the second conductive layer 106 Electroplating forms a fifth conductive layer 110. The fifth conductive layer 110 defines a plurality of second wiring lines and may be composed of a single metal such as copper (Cu) or a plurality of metal layers such as a combination of copper (Cu), nickel (Ni), palladium (Pd), and gold (Au). form.

Referring to FIG. 36, the third photoresist layer 108 is removed and is exemplified. For example, the exposed portion of the second conductive thin film layer 106 is also removed by chemical etching. In the illustrated embodiment, a second or top finishing layer 34 is formed on the selected surface of the fifth conductive layer 110 by a photolithography process.

As shown in FIG. 36, the substrate 10 thus formed includes a carrier 12. And a plurality of outer pads 14 formed on the carrier 12, and the outer pads 14 formed on the carrier 12 define a first conductive layer. A plurality of first microvias 56 are formed on the outer pads 14, and the first microvias 56 define a second conductive layer. A first insulating layer 20 is formed on the carrier 12 by a molding compound 22, and the first insulating layer 20 covers the first and second conductive layers. A conductive thin film layer 26 is formed on the second conductive layer and at least partially on the first insulating layer 20. A third conductive layer 96 is formed on the second conductive layer and the first insulating layer 20, and a fourth conductive layer 100 is formed on the third conductive layer 96. A second insulating layer 104 is formed on the first insulating layer 20 and covers the third and fourth conductive layers 96 and 100. A second conductive thin film layer 106 is formed on the fourth conductive layer 100 and at least partially on the second insulating layer 104. A die pad 28, a plurality of bond pads 30, and a plurality of conductive traces 32 are formed on the fourth conductive layer 100 and define a fifth conductive layer 110. In the illustrated embodiment, the substrate 10 also includes a first or bottom finishing layer 15 connected between the carrier 12 and the first conductive layer and a second surface formed on one surface of the fifth conductive layer 110. Or top finishing layer 34.

In this embodiment, the third conductive layer 96 transmits the plurality of A plurality of first microvias 56 are electrically connected to the second conductive layer and extend and overlap over the first insulating layer 20. In this embodiment, the third conductive layer 96 defines a first wiring line for forming a circuit of the substrate 10 and the fourth conductive layer 100 defines a plurality of second micro vias or vertical pillars. In this embodiment, one of the top surfaces of the fourth conductive layer 100 is completely exposed and substantially flush with the top surface of one of the second insulating layers 104. In this embodiment, the fifth conductive layer 110 is formed on the fourth conductive layer 100 and the second insulating layer 104. The fifth conductive layer 110 is electrically connected to the fourth conductive layer 100 through the plurality of second micro vias 92 and extends over and over the second insulating layer 104. The fifth conductive layer 110 defines a second wiring line for forming a circuit of the substrate 10.

In this embodiment, the conductive film layer 26 is connected to the first Between the second and third conductive layers and between the first insulating layer 20 and the third conductive layer 96. In this embodiment, the second insulating layer 104 is connected between the fourth and fifth conductive layers 100 and 110 and between the second insulating layer 104 and the fifth conductive layer 110.

As will be appreciated by those of ordinary skill in the art, The various steps can be repeated in other embodiments to form a multilayer stacking substrate, and the multilayer stacking substrate can be finished by forming a finishing layer on the last or uppermost conductive layer.

Referring to FIG. 37, one of the substrates formed in FIG. 36 is shown. Semiconductor package 44. The semiconductor package 44 includes a plurality of outer pads 14, and the outer pads 14 define a first conductive layer. Most microvias 56 are formed in the The outer pads 14 are defined, and the micro vias 56 define a second conductive layer. The first and second conductive layers are buried in a first insulating layer 20, and the first insulating layer 20 is formed by a molding compound 22. A conductive thin film layer 26 is formed on the second conductive layer and at least partially on the first insulating layer 20. A third conductive layer 96 is formed on the second conductive layer and the first insulating layer 20, and a fourth conductive layer 100 is formed on the third conductive layer 96. A second insulating layer 104 is formed on the first insulating layer 20 and covers the third and fourth conductive layers 96 and 100. A second conductive thin film layer 106 is formed on the fourth conductive layer 100 and at least partially on the second insulating layer 104. A die pad 28, a plurality of bond pads 30, and a plurality of conductive traces 32 are formed on the fourth conductive layer 100 and define a fifth conductive layer 110. A top finishing layer 34 is formed on one surface of the fifth conductive layer 110. A semiconductor wafer 36 is attached to the die pad 28 and a plurality of metal lines 40 electrically connect the semiconductor die 36 and the bond pads 30. A sealing material 42 seals the semiconductor wafer 36, the metal lines 40, and the bonding pads 30. In the illustrated embodiment, a bottom finishing layer 15 is formed on one of the bottom sides of the outer pads 14.

The sealing material 42 may be dielectric or used to form the substrate 10 or The insulating layer is composed of the same material or molding compound. Advantageously, this helps to reduce or prevent stress caused by the mismatch of the properties of the material to the semiconductor package 44.

Please refer to FIG. 38, another embodiment of the above embodiment. The method of forming the substrate 10 for a semiconductor package can include stamping or stamping the first conductive layer prior to performing the molding operation to produce a rivet head profile as shown in FIG. 38 on the outer pads 14. In this embodiment, defined The first conductive layer of the substrate 10 and the outer pads 14 of the semiconductor package 44 have a rivet head profile as shown in FIG. Advantageously, this helps prevent the outer pads 14 from separating from the first insulating layer 20 and increasing the reliability of the semiconductor package 44.

Although, in the foregoing embodiments, the conductive lines and the The conductive film layers are respectively formed by electroplating and a no-electricity process, but those skilled in the art should understand that the present invention is not limited to these methods and the formation of the conductive lines and the conductive film layers will be described below with reference to FIGS. 39 to 44. Other methods.

Referring to FIG. 39, a first conductive layer 14 will be formed. A carrier 12 is placed in a cavity 112 defined by a first die portion 114 and a second die portion 116. In another embodiment, a carrier 12 having a first conductive layer 14 and a plurality of vertical contact posts 56 may be formed as shown in FIG. As can be seen from Figure 39, the first mold portion 114 is lined with a metal foil 118.

The carrier 12 and the metal foil 118 can be vacuumed and electrostatically absorbed Guide, magnetic attraction or other suitable device to hold the positioning. In this embodiment, the metal foil 118 has a thickness of less than about 30 micrometers (μm). The metal foil 118 can be a copper (Cu) foil. The mold can be preheated.

In the illustrated embodiment, the first and second mold portions 114 are When sandwiched with 116, the carrier 12 and the metal foil 118 are completely enclosed within the cavity 112. In this embodiment, a gap is provided between the first conductive layer 14 (or the vertical contact posts 56) and the metal foil 118 in the cavity 112. The first conductive may be stamped or embossed before being placed in the cavity Layer 14 (or the vertical contact posts 56) is to achieve a uniform height to achieve a consistent gap. The gap is preferably less than about 30 microns (μm).

A liquid molding compound 22 is injected into the cavity at a high pressure. 112. The molding compound 22 can be preheated from a solid state to a liquid state at a high temperature before being injected into the cavity 112. The liquid molding compound 22 fills the cavity 112, connects the carrier 12 and the metal foil 118 and seals the first conductive layer 14. If the metal foil 118 is smaller than the size of the cavity 112, it can also be sealed. The molding compound 22 is partially hardened and cured after a length of elevated temperature to form a first dielectric layer 20. In this procedure, the molding compound 22 is adhered to and bonded to the metal foil 118. In this manner, when the molding compound 22 is deuterated, the metal foil 118 is adhered to the first dielectric layers 20, 22. The metal foil 118 may be chemically or mechanically treated to roughen the surface prior to placement in the cavity 112 to increase adhesion to the first dielectric layer 20.

Please refer to FIG. 40 below, and the compression shown in FIG. 40 will be described below. Molding, as an alternative to injection or transfer molding.

A carrier 12 having a first conductive layer 14 is disposed in a cavity 112 defined by a first mold portion 114 and a second mold portion 116. In another embodiment, a carrier 12 having a first conductive layer 14 and a plurality of vertical contact posts 56 may be formed as shown in FIG. The first mold portion 114 is lined with a metal foil 118. The mold can be preheated.

A molding compound 22 is placed on the metal foil 118 (or on the carrier 12) and the first and second mold portions 114 and 116 are sandwiched together to support the carrier 12 at high pressure and temperature ( Or metal foil 118) pressed in the mold Compound 22 was prepared. The molding compound 22 can be in the form of a paste or a fluid. Alternatively, the molding compound is in a solid or powder form and heated to melt it to a liquid state to seal the first mold portion 114 and completely fill the mold cavity 112. The liquid molding compound 22 is hardened and cured after a length of elevated temperature to form a first dielectric layer 20. In the procedure, the metal foil 118 is combined with the first dielectric layer 20 to form a conductive film layer 118 when the molding compound is cured.

Referring now to Figure 41, the carrier 12 is removed from the mold. in a first dielectric layer 20 on the carrier 12 and sealing the first conductive layer 14 (and the vertical contact pillars 56) and a first conductive thin film layer or line 118 on the first dielectric layer 20 At the same time formed. The assembly can be subjected to another high temperature treatment to completely harden the molding compound 22 and strengthen the bond with the metal layer 118.

Advantageously, the conductive line is formed on the molding compound 22 The method of the conductive thin film layer increases the adhesion of the conductive trace and the conductive thin film layer to the first dielectric layer 20.

Referring now to Figure 42, the method can be similarly used in a A conductive line or a conductive film layer 118 is formed on the second insulating layer 88, as shown in FIG.

Please refer to FIG. 43 below as an alternative to the metal foil 118. In another embodiment, one of the metal layers 120 disposed on a support layer 122 can be used as shown in FIGS. 43 and 44. The metal layer 120 can be formed on the support layer 122 by electroplating or sputtering. The support layer 122 can be an epoxy tape. Advantageously, with this embodiment, the metal foil can be thinned after it is not needed In the case of a thin metal layer. More advantageously, a thin metal layer is used, the surface roughness of the metal layer 120 is in accordance with the surface roughness of the support layer 122 and thus can be borrowed without the adhesion of the metal layer 120 to the first dielectric layer 20. The surface roughness of the metal layer 120 is controlled by selecting a support layer having a desired thickness. The roughening effect helps to increase the adhesion of the metal layer 120 to the first dielectric layer 20.

Forming on the support layer 122 before forming the metal layer 120 A titanium (Ti) layer is formed as a conductive plane for electroplating copper and not bonded to copper.

Referring to FIG. 44, after the first dielectric layer 20 is formed, The support layer 122 may be peeled off, and the metal layer 120 is left on the first dielectric layer 20 as the conductive thin film layer 120.

As can be seen from the foregoing description, the present invention provides a semiconductor for use in A packaged substrate, a method of forming the substrate, a method of packaging a semiconductor wafer with the substrate, and a low-cost semiconductor package based on a panel. Advantageously, large panel processing for producing a plurality of package units per panel can be performed using the substrate of the present invention. This reduces the manufacturing cost per semiconductor package. In embodiments where the insulating layer is formed from the same material as the sealing material, since the substrate body will thus have the same coefficient of thermal expansion as the sealing material and this helps prevent the sealing material from separating from the underlying dielectric layer, Therefore, a more reliable package is formed.

The preferred embodiment of the invention has been presented for purposes of illustration and description. It is to be understood that the invention is not limited or limited to the disclosed forms. It should be understood by those of ordinary skill in the art that without departing from the invention In the case of the broad inventive concept, many changes can be made to the above embodiments. Therefore, it is understood that the invention is not limited to the specific embodiment disclosed, but the invention is intended to be limited to the scope of the invention as defined by the appended claims.

In addition, unless the context clearly requires otherwise, the terms "comprising" and the like shall be interpreted as an inclusive and exclusive or exclusive term throughout the description and claims; in other words, the term "including, but not limited to" .

10‧‧‧ base

12‧‧‧ Carrier

14‧‧‧Outer mat

15‧‧‧First or bottom finishing layer

20‧‧‧First insulation

22‧‧‧Molded compounds

26‧‧‧ Conductive film layer

28‧‧‧ die pad

30‧‧‧Join pad

32‧‧‧Electrical circuit

34‧‧‧Second or top finishing layer

56‧‧‧microvia

64‧‧‧Filling

66‧‧‧Resin

Claims (39)

A method of forming a substrate for a semiconductor package, the method comprising: providing a carrier; forming a plurality of outer pads on the carrier, and the outer pads formed on the carrier define a first conductive layer; performing a molding Operating to form a first insulating layer on the carrier by a molding compound, wherein the first conductive layer is buried in the first insulating layer; and forming a plurality of bonding pads and a plurality of conductive lines on the first conductive layer And one or more of the plurality of microvias, and the one or more of the bonding pads, the conductive lines, and the microvias formed on the first conductive layer define a second Conductive layer. The method of claim 1, wherein the step of forming the first conductive layer on the carrier comprises: forming a photoresist layer on the carrier; patterning the photoresist layer to form a plurality of openings in the photoresist layer; Depositing one or more metal layers in the openings formed in the photoresist layer to form the first conductive layer; and removing the photoresist layer. The method of claim 1, wherein the molding compound comprises a resin and one or more fillers. The method of claim 3, wherein the molding compound comprises the one or more fills between about 70 weight percent and about 95 weight percent material. The method of claim 3, wherein the molding compound has a coefficient of thermal expansion between about 5 and about 15 parts per million (ppm/° C.) per degree Celsius. The method of claim 1, wherein a plurality of first microvias are formed on the outer pads, and the first microvias define the second conductive layer, wherein the bonding pads and the plurality of first conductive lines One or more are formed on the second conductive layer and define a third conductive layer, and wherein the micro vias electrically connect the outer pads and the third conductive layer. The method of claim 6, wherein the first microvias are formed on the outer pads before the molding operation is performed to form the first insulating layer on the carrier and wherein after the molding operation, the The first micro via is buried in the first insulating layer. The method of claim 6, wherein a plurality of microvia holes for the first microvias are formed in the first insulating layer during the molding operation by using a mold portion having a pattern of protrusions, and The protrusion pattern corresponds to one of the microvia holes in the first insulating layer. The method of claim 6, further comprising forming a plurality of microvia holes for the first microvias in the first insulating layer by one of laser drilling and mechanical drilling. The method of claim 6, further comprising forming a microvia through the previous conductive layer. The method of claim 1, further comprising forming one or more continuous insulating layers on the first insulating layer, the one or more continuous insulating layers comprising a solder mask, a molding compound, a woven glass fiber laminate, a primer, a resin coated copper (RCC) film, and one or more of a prepreg or a woven glass laminate having a metal foil By. The method of claim 11, further comprising forming a plurality of microvia holes in one of the one or more continuous insulating layers by one of photolithography, laser drilling, and mechanical drilling. The method of claim 11, further comprising forming the first insulating layer, the one or more continuous insulating layers, and the like before forming the bonding pads and one or more of the conductive lines on a conductive layer A conductive thin film layer is formed on one or more of the conductive layers. The method of claim 13, further comprising one or both of: roughening the surface of the first or continuous insulating layer and/or the conductive layer before forming the conductive thin film layer; and before forming the conductive thin film layer The surface bonding of the first or continuous insulating layer is chemically activated. The method of claim 1, wherein the molding operation comprises: placing the carrier on which the first conductive layer is formed in a cavity defined by a first mold portion and a second mold portion; The molding compound is injected or compressed to fill the cavity in a liquid or molten state; the molding compound is cured to form the first insulating layer on the carrier. The method of claim 15, further comprising lining the first mold portion with a metal foil, wherein the metal foil adheres to the mold when the molding compound is hardened On the compound. The method of claim 16, further comprising the metal foil having a thickness of less than about 30 micrometers (μm). The method of claim 16, wherein the metal foil is disposed on a support layer. The method of claim 1, further comprising: removing a portion of the first insulating layer after the molding operation to expose a surface of a lower conductive layer. The method of claim 1, further comprising: stamping the first conductive layer to create a rivet head profile on the outer pads prior to performing the molding operation. A substrate for a semiconductor package, the substrate comprising: a carrier; a plurality of outer pads formed on the carrier, and the outer pads formed on the carrier define a first conductive layer; a first insulating layer, Forming a molding compound on the carrier, wherein the first conductive layer is buried in the first insulating layer; and one or more of the plurality of bonding pads, the plurality of conductive lines, and the plurality of microvias Formed on the first conductive layer, and one or more of the bonding pads, the conductive lines and the microvias formed on the first conductive layer define a second conductive layer. The substrate of claim 21, wherein the molding compound comprises a resin and one or more fillers. The substrate of claim 22, wherein the molding compound is included at about 70 The one or more fillers are between about 95% by weight and about 95% by weight. The substrate of claim 22, wherein the molding compound has a coefficient of thermal expansion between about 5 and about 15 parts per million (ppm/°C) per degree Celsius. The substrate of claim 21, wherein a plurality of first microvias are formed on the outer pads, and the first microvias define the second conductive layer, wherein the bonding pads and the plurality of first conductive lines One or more are formed on the second conductive layer and define a third conductive layer, and wherein the micro vias electrically connect the outer pads and the third conductive layer. The substrate of claim 25 further comprises a layer of microvias formed on the previous conductive layer. The substrate of claim 21, further comprising one or more continuous insulating layers formed on the first insulating layer, the one or more continuous insulating layers comprising a solder masking material, a molding compound material, and a woven glass A laminate, a primer, a resin coated copper (RCC) film, and one or more of a prepreg or a woven glass laminate having a metal foil. The substrate of claim 27, further comprising a conductive film layer, and the conductive film layer is at least partially formed in the first insulating layer, the one or more continuous insulating layers and a conductive layer Above. The substrate of claim 21, wherein the outer pads defining the first conductive layer have a rivet head profile. A method of packaging a semiconductor wafer, comprising: providing a semiconductor package formed according to the method of claim 1 a substrate; the semiconductor wafer is attached to one of the outer pads and one of the substrate pads; the plurality of metal wires are used to electrically connect the semiconductor wafer and the bonding pads of the substrate; and the semiconductor wafer is sealed with a sealing material And the metal pads and the bonding pads; and removing the carrier to expose the first conductive layer. A semiconductor package comprising: a plurality of outer pads defining a first conductive layer; a first insulating layer formed of a molding compound, wherein the first conductive layer is buried in the first insulating layer; One or more of a die pad, a plurality of bond pads, a plurality of conductive traces, and a plurality of microvias are formed on the first conductive layer, and the die pad is formed on the first conductive layer. The one or more of the bonding pads, the conductive lines and the microvias define a second conductive layer; a semiconductor wafer attached to one of the outer pads and the die pad; a plurality of metal lines And electrically connecting the semiconductor wafer and the bonding pads; and a sealing material sealing the semiconductor wafer, the metal wires and the bonding pads. The semiconductor package of claim 31, wherein the molding compound comprises a Resin and one or more fillers. The semiconductor package of claim 32, wherein the molding compound comprises between about 70 weight percent and about 95 weight percent of the one or more fillers. The semiconductor package of claim 32, wherein the molding compound has a coefficient of thermal expansion between about 5 and about 15 parts per million (ppm/°C) per degree Celsius. The semiconductor package of claim 31, wherein a plurality of first microvias are formed on the outer pads, and the first microvias define the second conductive layer, wherein the pads and the plurality of first conductive lines One or more of the first conductive layers are formed on the second conductive layer and define a third conductive layer, and wherein the micro vias electrically connect the outer pads and the third conductive layer. The semiconductor package of claim 35, further comprising a layer of microvias formed on the previous conductive layer. The semiconductor package of claim 31, further comprising one or more continuous insulating layers formed on the first insulating layer, the one or more continuous insulating layers comprising a solder masking material, a molding compound material, and a A woven glass laminate, a primer, a resin coated copper (RCC) film, and one or more of a prepreg or a woven glass laminate having a metal foil. The semiconductor package of claim 37, further comprising a conductive film layer, wherein the conductive film layer is at least partially formed in the first insulating layer, the one or more continuous insulating layers and a conductive layer Or more than one. The semiconductor package of claim 31, wherein the outer pads defining the first conductive layer have a rivet head profile.