TWI762346B - A kind of ohmic contact manufacturing method of group III nitride semiconductor element - Google Patents

Abstract

The present invention provides a method for fabricating an ohmic contact for reducing the contact resistance of a group III nitride semiconductor element. It mainly uses fluoride gas plasma for etching and surface treatment, and annealing treatment to achieve ohmic contact with ultra-low contact resistance. The manufacturing method does not cause damage to the surface of the semiconductor channel, the overall process is relatively simple, and the manufactured group III nitride semiconductor device has good reliability, which can be applied to group III nitride transistors and diodes.

Description

A kind of ohmic contact manufacturing method of group III nitride semiconductor element

The present invention relates to a group III nitride semiconductor device, and in particular, to a method for manufacturing an ohmic contact of a group III nitride semiconductor device.

In the field of power electronics, it is a future trend to introduce wide-bandgap semiconductor components to improve the energy efficiency of equipment and modules and reduce energy consumption. In particular, gallium nitride high-frequency power components have become the most promising semiconductor components in the next-generation high-power and high-frequency devices due to their excellent performance beyond the limits of silicon materials. Group III nitride semiconductor devices, such as gallium nitride (GaN) semiconductor high electron mobility transistors (HEMTs), typically form a two-dimensional electron gas (2DEG) to achieve high frequency operation with high power output.

Taking metal-insulator-semiconductor (MIS) high electron mobility (HEMT) III-nitride semiconductor devices as an example, the turn-on resistance is roughly related to the contact resistance and the resistance between the source and gate of the two-dimensional electron gas , The resistance between the gate and the drain of the two-dimensional electron gas and the channel resistance, of which the contact resistance accounts for the largest part of the on-resistance, so it is necessary to reduce its resistance value to become an ohmic contact in design, so as to achieve high on-state current, low Power loss, low heat generation and long life cycle.

Two methods of reducing contact resistance in forming ohmic contacts are known, and are described below. One is to re-grow a heavily doped N-type channel layer (eg, N+ GaN layer) on both sides of the barrier layer and on the channel layer after etching the contact electrode region of the barrier layer, and then form Ti/Au metal source and drain to form ohmic contacts on the N-type channel layer. However, this approach may have the following disadvantages: low yield; high manufacturing cost; damage to the inner side of the barrier layer after etching, leading to defects and easy leakage; and requiring complex and expensive molecular beam epitaxy (MBE) to recreate A heavily doped N-type channel layer is grown.

Another way to reduce the contact resistance is to choose to bury the source and gate parts of the Ti/Au metal in the barrier layer. However, this approach may have the following disadvantages: difficulty in controlling etch depth and sidewall slope accuracy; possible non-uniformity issues in wafer-scale wafer processing; possible residue and etch damage; and very difficult Realize HEMT III-nitride semiconductor devices with ultra-thin AlN or Al(Ga)N barrier layers (note: it is difficult to control the etching depth). Accordingly, there is still an urgent need in the industry for a low-complexity, low-cost, and high-yield low-contact-resistance ohmic contact manufacturing method.

According to the purpose of the present invention, a method for manufacturing an ohmic contact of a group III nitride semiconductor device is provided, and the group III nitride semiconductor device includes a transistor and a diode. The manufacturing method of the ohmic contact of the group III nitride semiconductor device includes: providing a group III nitride semiconductor structure without forming a source electrode and a drain electrode; forming a protective layer on the barrier layer of the group III nitride semiconductor structure; on the protective layer Form a patterned mask layer (eg, photoresist layer or other layer of material resistant to fluoride gas plasma etching) to define the location of source and drain electrodes; use fluoride gas plasma to The protective layer of the semiconductor structure is etched, wherein the part of the protective layer at the positions corresponding to the source electrode and the drain electrode is etched at least to the surface of the barrier layer; using fluoride gas plasma to expose the barrier layer of the III-nitride semiconductor structure. The barrier layer is subjected to surface treatment; the mask layer is removed and annealed; after the annealing treatment, metal is implanted at the position of the source electrode and the drain electrode to form the source electrode and the drain electrode; The Ill-nitride semiconductor structure of the drain is subjected to a rapid annealing process.

According to the purpose of the present invention, a semi-finished product of a group III nitride semiconductor device is provided, which is manufactured by using the above-mentioned method for manufacturing an ohmic contact of a group III nitride semiconductor device, comprising: a group III nitride semiconductor structure; and a protective layer, a source electrode and a The drain electrode is formed on the barrier layer of the III-nitride semiconductor structure.

According to the purpose of the present invention, a group III nitride semiconductor device is provided, which comprises another group III nitride semiconductor device semi-finished and a gate electrode formed by removing part of the protective layer of the above-mentioned semi-finished product of the group III nitride semiconductor device. , wherein the gate electrode is formed on the barrier layer, and is located between the source electrode and the drain electrode in the horizontal direction.

All in all, compared with the prior art, the method for manufacturing the ohmic contact of the III-nitride semiconductor device provided by the embodiment of the present invention has the technical effects of low manufacturing cost, high production yield, and simple manufacturing process.

In order to facilitate the examiners to understand the technical features, content and advantages of the present invention and the effects that can be achieved, the present invention is hereby described in detail with the accompanying drawings and in the form of embodiments as follows. The subject matter is only for illustration and auxiliary description, and is not necessarily the real scale and precise configuration after the implementation of the present invention. Therefore, the ratio and configuration relationship of the attached drawings should not be interpreted or limited to the scope of rights of the present invention in actual implementation. Together first to describe.

In order to solve the technical problems of low manufacturing yield and high manufacturing cost of the ohmic contact of the group III nitride semiconductor device in the prior art, the present invention proposes a novel and feasible method for reducing the ohmic contact of the group III nitride semiconductor device, which does not The surface of the semiconductor channel is damaged, the overall process is relatively simple, and the reliability of the manufactured III-nitride semiconductor element is good, and even the resistivity of the contact resistance can be as low as 0.1 ohm·mm. Further, the ohmic contact manufacturing method for reducing the contact resistance of the III-nitride semiconductor element of the present invention is mainly to form a protective layer on the barrier layer on the III-nitride semiconductor structure without the source and drain electrodes, and then, After the pattern is defined through the mask material (eg, photoresist), the protective layer that is not masked by the mask material is etched and surface treated using fluoride gas plasma, and then the photoresist is removed and annealed. Metal is implanted to form the source and gate, and finally, rapid annealing is performed to achieve ohmic contact with ultra-low contact resistance.

In the method for fabricating the ohmic contact of the III-nitride semiconductor element of the present invention, due to the existence of the protective layer, the fluoride gas plasma treatment will not damage the surface of the channel layer, and by controlling the power and treatment time, the fluoride ions will not be damaged. penetrates into the channel layer. In addition, the annealing treatment can further remove the residual fluoride ions. Accordingly, the ohmic contact manufacturing method for reducing the contact resistance of the III-nitride semiconductor device according to the embodiment of the present invention has the technical effects of low manufacturing cost, high production yield, and simple manufacturing process. In addition, an embodiment of the present invention also provides a group III nitride semiconductor element and a semi-finished product thereof manufactured by using the above-mentioned method for manufacturing an ohmic contact of a group III nitride semiconductor element.

Referring to FIG. 2H , a schematic cross-sectional view of a semi-finished product of a Group III nitride semiconductor device according to an embodiment of the present invention is shown in FIG. 2H . The group III nitride semiconductor structure 11 includes the group III nitride semiconductor structure 11 without the source electrode 12 and the drain electrode 13 , the source electrode 12 , the drain electrode 13 and the protective layer 14 , wherein the source electrode 12 , the drain electrode 13 and the protective layer 14 On the surface of the barrier layer 115 of the III-nitride semiconductor structure 11 , and in the horizontal direction, part of the protective layer 14 is located between the sidewall of the source electrode 12 and the sidewall of the drain electrode 13 . Due to etching and surface treatment by fluoride gas plasma, vacuum annealing and rapid annealing, the resistivity of the contact resistance of the source electrode 12 and the drain electrode 13 with respect to the barrier layer 115 can reach 0.1 to 0.2 ohm·kg centimeters (including 0.1 and 0.2 ohm·mm).

In the embodiment of the present invention, the protective layer 14 is made of a dielectric material, and may be a SiN _x layer, a SiO ₂ layer or a Si layer, wherein x represents any number greater than 0. The thickness of the protective layer 14 can be selected from 5 to 100 nm (including 5 nm and 100 nm), preferably, from 5 to 40 nm (including 5 nm and 40 nm) . In addition, the thickness selection of the protective layer 14 is related to the material, fluoride gas plasma power and processing time, and its main purpose is to protect the two-dimensional electron gas (2DEG) layer 1141 from damage during fluoride gas plasma processing. Each of the source electrode 12 and the drain electrode 13 may be a metal stack structure including a first structure layer and a second structure layer ordered from bottom to top, the first structure layer may be a Ti/Al double-layer structure, and the first structure layer may be a Ti/Al double layer structure. The two-structure layer may be a Ni/Au double-layer structure, a Ti/Ta double-layer structure, a Ti layer, a TiN layer, a Cu layer or a W layer, and the present invention is not limited thereto.

In the embodiments of FIGS. 1 and 2A to 2H , the III-nitride semiconductor structure 11 is a HEMT semiconductor structure, and the final semi-finished III-nitride semiconductor device 1 does not have a gate, so it can be used as a HEMT diode. , but the present invention is not limited to this, and in other embodiments, the semi-finished product 1 of the III-nitride semiconductor device may be formed with a gate electrode, and in the horizontal direction, the gate electrode is located on the sidewall of the source electrode 12 and the drain electrode 13 between the side walls. The group III nitride semiconductor structure 11 includes a substrate 111 , a nucleation layer 112 , a buffer layer 113 , a channel layer 114 and a barrier layer 115 , wherein the nucleation layer 112 is formed on the surface of the substrate 111 , and the buffer layer 113 is formed On the surface of the nucleation layer 112 , the channel layer 114 is formed on the surface of the buffer layer 113 , and the barrier layer 115 is formed on the surface of the channel layer 114 . In the III-nitride semiconductor structure 11 , the two-dimensional electron gas layer 1141 is formed in the interface between the channel layer 114 and the barrier layer 115 .

The substrate 111 is, for example, silicon, silicon-on-insulator (SOI), silicon carbide (SiC), sapphire substrate, or other substrates capable of epitaxy of group III nitride semiconductors, and the invention is not limited thereto. The nucleation layer 112 is, for example, a low-temperature GaN layer, a low-temperature AlN layer, a high-temperature GaN layer or a high-temperature AlN layer, and the present invention is not limited thereto. The buffer layer 113 may be, for example, an AlN layer, an AlGaN layer, an InGaN layer, a super lattice AlN/GaN layer, a supercrystalline AlGaN/GaN layer, a supercrystalline AlN/AlGaN, a carbon-doped GaN layer, an iron-doped GaN layer or an undoped GaN layer, and the present invention is not limited thereto. When the buffer layer 113 is an AlGaN layer, the chemical composition formula of AlGaN is _{AlyGa1 -yN} , 5%<=y. The channel layer 114 may be, for example, a GaN layer, an AlGaN layer, an InN layer or an InGaN layer, and the present invention is not limited thereto. The barrier layer 115 may be, for example, an AlGaN layer, an InAlN layer, an InAlGaN layer, an InGaN layer or an AlN layer, and the present invention is not limited thereto. When the barrier layer 115 is an AlGaN layer, the chemical composition formula of AlGaN is AlxGa1 _{- xN} , 0<=x<=40%, for example, x can be 20%, and the thickness of the barrier layer 115 is 20 nanometers m, and the sheet resistance value of the two-dimensional electron gas layer 1141 is <450 ohms/□.

1, FIG. 2A to FIG. 2H, FIG. 1 is a flow chart of a method for reducing the ohmic contact of a group III nitride semiconductor device according to an embodiment of the present invention, and FIG. 2A to FIG. 2H are an embodiment of the present invention. The cross-sectional schematic diagram of the finished product of each step of the ohmic contact manufacturing method of the group nitride semiconductor device.

First, in step S31, a group III nitride semiconductor structure 11 having a two-dimensional electron gas without forming the source electrode 12 and the drain electrode 13 as shown in FIG. 2A is provided, which is similar in structure to the group III nitride semiconductor structure in FIG. 1 . Structure 11. Next, in step S32 , a protective layer 14 ′ is formed on the barrier layer 115 of the III-nitride semiconductor structure 11 , as shown in FIG. 2B , wherein the protective layer 14 ′ is formed by, for example, plasma enhanced chemical vapor deposition (PECVD) method, the material of the protective layer 14' is as described above, and the thickness is selected from 40 nm or less, for example, 10, 20 or 40 nm. In addition, the method of depositing the protective layer 14 ′ may be in-situ metal organic vapor phase epitaxy (in-situ MOCVD), any chemical vapor deposition (CVD), any physical vapor deposition (PVD), or any atomic layer deposition (ALD). After that, in step S33 , a mask layer 17 with a pattern is formed on the protective layer 14 ′ to define the positions of the source electrode 12 and the drain electrode 13 , as shown in FIG. 2C .

Next, in step S34 , the protective layer 14 ′ of the III-nitride semiconductor structure 11 is etched by dry etching using fluoride gas plasma, as shown in FIG. 2D ; in step S35 , using fluoride gas plasma The slurry was surface treated as shown in Figure 2E. Etching and surface treatment can, for example, generate CF ₄ plasma through an Inductively Coupled Plasma (ICP) system, wherein the portion of the protective layer 14 corresponding to the positions of the source electrode 12 and the drain electrode 13 is etched to the surface of the barrier layer 115 . The process of forming the protective layer 14 and realizing the ohmic region. The power of the fluoride gas plasma is selected from between 50 and 300 watts (including 50 and 300 watts), and the treatment time is selected from between 5 and 300 seconds (including 5 and 300 seconds), preferably from 5 to 300 seconds. Between 50 seconds (including 5 and 50 seconds). When the thickness of the protective layer 14' is between 10 and 40 nm, the processing time may be 50 seconds, and the optimum thickness of the protective layer 14' is 30 nm. In addition, in addition to CF ₄ plasma, SF ₆ , CHF ₃ or C ₄ F ₈ plasma can also be selected, and Ar plasma can be selectively mixed. Furthermore, in addition to the inductively coupled plasma system, a reactive ion etching (RIE) or an inductively coupled plasma-reactive ion etching (ICP-RIE) system can also be selected. When the protective layer 14' is about 20 nm, the fluoride gas plasma treatment for about 30 and 50 seconds can reduce the resistivity of the original contact resistance from 0.8 to 0.44 and 0.2 ohm·mm, respectively. Incidentally, the kind, power, processing time, etc. of the fluoride gas plasma for etching and surface treatment may be the same or different from each other.

Next, in step S36, the mask layer 17 is removed, and a surface heat treatment is performed by vacuum annealing to remove fluoride ion bonds, as shown in FIG. 2F . The annealing treatment here may be a multi-step annealing treatment or a single-step annealing treatment, for example, the number of steps of the annealing treatment is preferably 1 to 4 (including 1 and 4). Then, after the annealing treatment, in step S37, the metal is implanted, as shown in FIG. 2G. The metal implantation method may be, for example, deposition through an electron beam gun to form the source electrode 12 and the drain electrode 13 . The annealing treatment can be performed in a vacuum chamber or in an Ar environment, and other gases can be introduced in an Ar environment. The annealing treatment can be rapid annealing treatment or other types of annealing treatment. The temperature of the annealing treatment is approximately between 450 and 650 degrees Celsius (including 450 and 650 degrees), and the total annealing time is approximately between 30 and 240 seconds ( Including 30 and 240 seconds), if the multi-step annealing process is performed, the time of each step is between 15 and 60 seconds (15 and 60 seconds inclusive).

Then, in step S38, a rapid annealing treatment is performed to achieve ultra-low contact resistance, as shown in Figure 2H, wherein the temperature of the rapid annealing treatment is 750 to 850 degrees Celsius (including 750 and 850 degrees Celsius), and the total time of the rapid annealing treatment is about Between 10 and 60 seconds (including 10 and 60 seconds, preferably 30 seconds), and the resistivity of the contact resistance can be reduced to 0.1 to 0.15 ohm·mm.

Please refer to FIG. 3A . FIG. 3A is a schematic cross-sectional view of a group III nitride semiconductor device according to an embodiment of the present invention. In FIG. 3A , the group III nitride semiconductor element 3 is a group III nitride semiconductor element of HEMT. The implementation of the group III nitride semiconductor element 3 is as follows. First, the semi-finished product 1 of the group III nitride semiconductor element shown in FIG. 2H is mesa-etched to define the isolation region RI. Next, a portion of the protective layer 14 between the source electrode 12 and the drain electrode 13 in the horizontal direction is removed to define a gate region. Next, the gate electrode 15 over the barrier layer 115 is formed at the gate electrode region.

Please refer to FIG. 3B . FIG. 3B is a schematic cross-sectional view of a group III nitride semiconductor device according to another embodiment of the present invention. Different from the embodiment of FIG. 3A , after removing part of the protective layer 14 in the III-nitride semiconductor device 4 , a dielectric with a thickness of about 1 to 10 nanometers (including the two end values of 1 and 10 nanometers) is also deposited Layer 88 is over protective layer 14 and barrier layer 115 at the gate region, and gate 15 is then formed over dielectric layer 88 at the gate region.

Please refer to FIG. 3C , which is a schematic cross-sectional view of a group III nitride semiconductor device according to still another embodiment of the present invention. Different from the embodiment of FIG. 3B , when part of the protective layer 14 is removed from the III-nitride semiconductor device 5 , part of the barrier layer 115 is also removed, so that the gate electrode 15 is located on the recess of the barrier layer 115 .

Specifically, the ohmic contact manufacturing method for reducing the contact resistance of the III-nitride semiconductor device according to the embodiment of the present invention uses a fluoride gas plasma treatment with a protective layer and an annealing treatment to reduce the contact resistance twice, so the contact resistance The resistivity can be effectively reduced. Furthermore, compared with the prior art, the method for manufacturing the ohmic contact of the III-nitride semiconductor device according to the embodiment of the present invention has the technical effects of low manufacturing cost, high production yield, and simple manufacturing process.

Looking at the above, it can be seen that the present invention has indeed achieved the desired enhancement effect under the breakthrough of the previous technology, and it is not easy for those who are familiar with the art to think about it. Furthermore, the present invention has not been disclosed before the application, and it has It is progressive and practical, and obviously meets the requirements for patent application. It is recommended to file a patent application in accordance with the law. I urge your bureau to approve this patent application for invention, in order to encourage invention, and it is extremely convenient.

The above-mentioned embodiments are only to illustrate the technical ideas and characteristics of the present invention, and the purpose is to enable those who are familiar with the art to understand the content of the present invention and implement it accordingly. It should not be used to limit the patent scope of the present invention. That is, all equivalent changes or modifications made according to the spirit disclosed in the present invention should still be covered within the patent scope of the present invention.

1: Semi-finished products of III-nitride semiconductor devices 3 to 5: Group III nitride semiconductor devices 11: Group III nitride semiconductor structure 111: Substrate 112: Nucleation layer 113: Buffer layer 114: channel layer 115: Barrier layer 12: Source 13: Drain 14, 14': protective layer 15: Gate 88: Dielectric layer 17: Mask layer S31～S38: Steps RI: Isolated area 1141: Two-dimensional electron gas layer

The drawings of the present invention are only used to facilitate the understanding of the present invention by those skilled in the art to which the present invention pertains, and the dimensions and dispositions thereof are merely schematic representations, and are not intended to limit the present invention, wherein the drawings are briefly described as follows : 1 is a flowchart of a method for manufacturing an ohmic contact resistance of a group III nitride semiconductor device according to an embodiment of the present invention; 2A to 2H are schematic cross-sectional views of a finished product of each step of a method for manufacturing an ohmic contact resistance of a group III nitride semiconductor device according to an embodiment of the present invention; 3A is a schematic cross-sectional view of a group III nitride semiconductor device according to an embodiment of the present invention; 3B is a schematic cross-sectional view of a group III nitride semiconductor device according to another embodiment of the present invention; 3C is a schematic cross-sectional view of a group III nitride semiconductor device according to still another embodiment of the present invention.

1: Semi-finished products of group III nitride semiconductor devices

11: Group III nitride semiconductor structure

111: Substrate

112: Nucleation layer

113: Buffer layer

114: channel layer

115: Barrier layer

12: Source

13: Drain

14: Protective layer

1141: Two-dimensional electron gas layer

Claims (9)

A method for manufacturing an ohmic contact of a group III nitride semiconductor device, comprising: providing a group III nitride semiconductor structure (11') without forming a source electrode (12) and a drain electrode (13); A protective layer (14') is formed on a barrier layer (115) of the compound semiconductor structure (11); a mask layer (17) with a pattern is formed on the protective layer (14') to define the source electrode (12) and the position of the drain electrode (13); use fluoride gas plasma to perform etching treatment on the protective layer (14') of the III-nitride semiconductor structure (11'), wherein the protective layer (14') ) corresponding to the position of the source (12) and the drain (13) is etched at least to the surface of the barrier layer (115); using the fluoride gas plasma for the III-nitride semiconductor structure (11) The exposed barrier layer (115) is subjected to surface treatment; and the mask layer (17) is removed, and an annealing treatment is performed; after the annealing treatment, the source electrode (12) and the drain electrode are Metal is implanted at the position of (13) to form the source (12) and the drain (13); and for the group III nitride semiconductor structure formed with the source (12) and the drain (13) (11) performing a rapid annealing treatment; wherein the protective layer (14') is a _SiNx layer or a _SiO2 layer, the thickness of the protective layer (14') is between 5 and 100 nm, the fluoride gas plasma For a _CF4 , _SF6 or _C4F8 plasma, the power of the fluoride gas plasma is between 50 and 300 watts, and the treatment time of the fluoride gas plasma is between ₅ and 300 seconds. The method for manufacturing an ohmic contact of a group III nitride semiconductor device according to claim 1, wherein the temperature of the annealing treatment is between 450 degrees Celsius and 650 degrees Celsius. The method for manufacturing an ohmic contact of a group III nitride semiconductor device according to claim 1, wherein the temperature of the rapid annealing treatment is between 750 degrees Celsius and 850 degrees Celsius. The method for manufacturing an ohmic contact of a group III nitride semiconductor device according to claim 1, wherein the barrier layer (115) is an AlGaN layer, and its chemical composition formula is Al _x Ga _1-x N, 0<=x< =40%, or the barrier layer (115) is an AlN layer. A semi-finished product of a group III nitride semiconductor element, which is manufactured by using the method for manufacturing an ohmic contact of a group III nitride semiconductor element according to one of claims 1 to 4, comprising: the group III nitride semiconductor structure (11 ); and the protective layer (14), the source electrode (12) and the drain electrode (13) are formed on the barrier layer (115) of the III-nitride semiconductor structure (11). The group III nitride semiconductor element semi-finished product as claimed in claim 5, wherein the resistivity of the contact resistance of the group III nitride semiconductor element is 0.1 to 0.2 ohms. between millimeters. A group III nitride semiconductor element, comprising: another semi-finished product (1) of a group III nitride semiconductor element, wherein a part of the protective layer ( 14) formed after removal; and a gate electrode (15), the gate electrode (15) is formed on the barrier layer (115), and in the horizontal direction, is located between the source electrode (12) and the drain electrode between poles (13). The group III nitride semiconductor device according to claim 7, further comprising: A dielectric layer (88) under the gate (15) and over the barrier layer (115) and over the protective layer (14). The group III nitride semiconductor device according to claim 7, wherein part of the barrier layer (115) of the semi-finished product (1) of the group III nitride semiconductor device is further removed to form the barrier layer (115) The other group III nitride semiconductor element semi-finished product (1) has a groove, and the gate electrode (15) is located on the groove.

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