TWI762286B - Driving device and display - Google Patents

Abstract

A driving device includes a first initiating circuit, a second initiating circuit and a output circuit. The first initiating circuit adjusts a first node voltage according to a first driving signal during a first period, and adjusts the first node voltage according to a second driving signal during a second period. The second initiating circuit adjusts a second node voltage according to the first driving signal during the first period, and adjusts the second node voltage according to the second driving signal during the second period. The output circuit outputs a third driving signal, adjusts the third driving signal to a first voltage level according to the first node voltage during the first period, and adjusts the third driving signal to a second voltage level according to the second node voltage during a third period. The first driving signal has the second voltage level during the first period, and has the first voltage level during the third period. A display is also disclosed herein.

Description

Drives and Displays

The present disclosure is related to a driving technology, especially a driving device.

When driving a pixel circuit in a display, positive and negative pulses with the same pulse width are required, such as a pulse with an enable voltage level during data writing and a pulse with disable during data writing. A pulse of energy level. The above-mentioned pulse wave enables the display to write data voltage row by row under low frequency operation, compensate for the variation of the threshold voltage level of the thin film transistor, and at the same time reset the voltage of the light-emitting element to ensure that the light-emitting element is turned off to avoid flicker (Flicker) phenomenon. occurs to increase the contrast of the display. Therefore, how to develop the above-mentioned related technologies is an important topic in the field.

Embodiments of the present invention include a driving device. The driving device includes a first start-up circuit, a second start-up circuit and an output circuit. The first start-up circuit is used for adjusting a first node voltage of a first node according to a first driving signal in a first period, and is used for adjusting a first node voltage according to a second driving signal in a second period. The second start-up circuit is used for adjusting a second node voltage of a second node according to the first driving signal in the first period, and is used for adjusting the second node voltage according to the second driving signal in the second period. The output circuit is used for outputting a third driving signal, and is used for adjusting the third driving signal to a first voltage level according to the first node voltage in the first period, and for adjusting the first voltage level according to the second node voltage in a third period Three driving signals to a second voltage level. The first period, the second period and the third period are arranged in sequence. The first driving signal has a second voltage level during the first period, and has a first voltage level during the third period.

Embodiments of the present invention include a display. The display includes a display device and a driving device for driving the display device. The driving device includes a first driving unit, a second driving unit and a third driving unit. The first driving unit is used for generating a second driving signal according to a first driving signal. The second driving unit is used for generating a third driving signal according to the first driving signal. The third driving unit includes a first start-up circuit, a second start-up circuit and an output circuit. The first start-up circuit is used for adjusting a first node voltage of a first node according to the second driving signal in a first period, and for adjusting the first node voltage according to the third driving signal in a second period. The second start-up circuit is used for adjusting a second node voltage of a second node according to the second driving signal in the first period, and is used for adjusting the second node voltage according to the third driving signal in the second period. The output circuit is used for outputting a fourth driving signal, and is used for adjusting the fourth driving signal to a first voltage level according to the first node voltage in the first period, and for adjusting the first voltage level according to the second node voltage in a third period Four driving signals to a second voltage level. The first period, the second period and the third period are arranged in sequence. The second driving signal has a second voltage level during the first period, and has a first voltage level during the third period.

In this document, when an element is referred to as being "connected" or "coupled," it may be referred to as "electrically connected" or "electrically coupled." "Connected" or "coupled" may also be used to indicate the cooperative operation or interaction between two or more elements. In addition, although terms such as "first", "second", . . . are used herein to describe different elements, the terms are only used to distinguish elements or operations described by the same technical terms. Unless the context clearly dictates otherwise, the terms do not specifically refer to or imply a sequence or order, nor are they intended to limit the case.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this case belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the relevant art and the present case, and are not to be construed as idealized or overly formal meaning, unless expressly defined as such herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms including "at least one" unless the content clearly dictates otherwise. "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms "comprising" and/or "comprising" designate the stated feature, region, integer, step, operation, presence of an element and/or part, but do not exclude one or more The presence or addition of other features, entireties of regions, steps, operations, elements, components, and/or combinations thereof.

Several embodiments of the present case will be disclosed in the following figures. For the sake of clarity, many practical details will be described together in the following description. It should be understood, however, that these practical details should not be used to limit the present case. That is, in some embodiments of the present disclosure, these practical details are unnecessary. In addition, for the purpose of simplifying the drawings, some well-known structures and elements will be shown in a simple and schematic manner in the drawings.

FIG. 1 is a schematic diagram of a display 100 according to an embodiment of the present application. Referring to FIG. 1 , the display 100 includes a display device 110 , a driving device 120 , a data input device 130 and a lighting control device 140 . The driving device 120 provides a plurality of driving signals through the driving lines SL(0)~SL(n), for example, the driving signals G(1)~G(n+1) and GB(1)~GB shown in FIG. 2 (n+1), to the display device 110 . The data input device 130 provides a plurality of data signals to the display device 110 through the data lines DL(1)-DL(m). The light-emitting control device 140 provides a plurality of light-emitting signals to the display device 110 through the light-emitting lines EL(1)-EL(n). where n and m are both positive integers. In some embodiments, the display 100 may be made of a glass substrate or a plastic substrate, but is not limited thereto.

As shown in FIG. 1 , the display device 110 includes multiple stages of pixel driving circuits DV( 1 ) to DV(n) connected in series with each other, including a pixel driving circuit 112 . In some embodiments, the pixel driving circuit 112 in the display device 110 performs light-emitting operations according to the signals provided by the driving device 120 , the data input device 130 and the light-emitting control device 140 .

For example, the driving device 120 generates the driving signals G(n-1) and GB(n) to drive the pixel driving circuit 112 to perform data writing operations and light-emitting operations, so that the pixel driving circuit 112 writes the data input device 130 The data signal is provided, and light is emitted according to the light-emitting signal provided by the light-emitting control device 140 .

In different embodiments, the driving device 120 may provide different combinations of the driving signals G(1)-G(n+1) and GB(1)-GB(n+1) to drive the pixel driving circuit 112 . In some embodiments, the pixel driving circuit 112 is implemented by a low-temperature polycrystalline oxide active-matrix organic light-emitting diode (LTPO AMOLED), but the embodiment of the present invention does not limited to this. In other embodiments, the pixel driving circuit 112 may also include other types of light-emitting elements.

FIG. 2 is a schematic diagram of a driving device 200 according to an embodiment of the present application. Please refer to FIG. 2 and FIG. 1 , the driving device 200 is an embodiment of the driving device 120 .

As shown in FIG. 2, the driving device 200 is used for generating the driving signals G(1)-G(n+1) and GB(1) according to the clock signals CK1, CK2, CK3, CK4, XCK1, XCK2, XCK3 and XCK4 ~GB(n+1). In some embodiments, the driving device 200 converts the driving signals G(1)-G(n+1) and GB(1)-GB( n+1) is transmitted to the pixel driving circuits DV(1)~DV(n). In some embodiments, the driving device 200 is further configured to control according to the start signal ST and the reset signal RST.

As shown in FIG. 2 , the drive device 200 includes drive units DU( 1 ) to DU(n+1).

As shown in FIG. 2, the driving unit DU(1) is used for generating the driving signals G(1) and GB(1) according to the clock signals CK3, XCK1, XCK3 and the lower-level driving signal G(2). The driving unit DU(2) is used for generating the driving signals G(2) and GB(2) according to the clock signals CK4, XCK2, XCK4, the upper-level driving signal G(1) and the lower-level driving signal G(3). The driving unit DU(3) is used for generating the driving signals G(3) and GB(3) according to the clock signals CK1, XCK3, XCK1, the upper-level driving signal G(2) and the lower-level driving signal G(4). The driving unit DU(4) is used for generating the driving signals G(4) and GB(4) according to the clock signals CK2, XCK4, XCK2, the upper-level driving signal G(3) and the lower-level driving signal G(5). By analogy, the driving unit DU(n) is used to generate the driving signals G(n) and GB according to the clock signals CK3, XCK1, XCK3, the upper-level driving signal G(n-1) and the lower-level driving signal G(n+1). (n). The driving unit DU(n+1) is used for generating the driving signals G(n+1) and GB(n+1) according to the clock signals CK4, XCK2, XCK4 and the upper-level driving signal G(n).

As shown in FIG. 2, in some embodiments, the driving unit DU(1) is further configured to operate according to the start signal ST, and the driving unit DU(n+1) is further configured to operate according to the reset signal RST.

In some embodiments, each of the driving units DU( 1 )˜DU(n+1) has a similar circuit configuration, such as the circuit configuration of the driving unit 300 shown in FIG. 3 , and is based on the corresponding clock signal to operate.

For example, please refer to FIG. 3 and FIG. 2 , the driving unit DU(n) includes a plurality of switches corresponding to the switches T33 ˜ T312 , T321 and T322 in the driving unit 300 and capacitors corresponding to the capacitors C31 and C32 . The switches corresponding to the switches T311 and T312 are used for receiving the clock signal XCK1, the switches corresponding to the switches T35, T37 and T38 are used for receiving the clock signal CK3, and the capacitor corresponding to the capacitor C32 is used for receiving the clock signal XCK3.

For another example, the driving unit DU( 2 ) includes a plurality of switches corresponding to the switches T33 ˜ T312 , T321 and T322 in the driving unit 300 and capacitors corresponding to the capacitors C31 and C32 . The switches corresponding to the switches T311 and T312 are used for receiving the clock signal XCK2, the switches corresponding to the switches T35, T37 and T38 are used for receiving the clock signal CK4, and the capacitor corresponding to the capacitor C32 is used for receiving the clock signal XCK4.

For another example, the driving unit DU( 3 ) includes a plurality of switches corresponding to the switches T33 ˜ T312 , T321 and T322 in the driving unit 300 and capacitors corresponding to the capacitors C31 and C32 . The switches corresponding to the switches T311 and T312 are used for receiving the clock signal XCK3, the switches corresponding to the switches T35, T37 and T38 are used for receiving the clock signal CK1, and the capacitor corresponding to the capacitor C32 is used for receiving the clock signal XCK1.

For another example, the driving unit DU( 4 ) includes a plurality of switches corresponding to the switches T33 ˜ T312 , T321 and T322 in the driving unit 300 and capacitors corresponding to the capacitors C31 and C32 . The switches corresponding to the switches T311 and T312 are used for receiving the clock signal XCK4, the switches corresponding to the switches T35, T37 and T38 are used for receiving the clock signal CK2, and the capacitor corresponding to the capacitor C32 is used for receiving the clock signal XCK2.

The driving operations of the driving units DU(1)~DU(n+1) are disclosed as above, but the embodiment of the present invention is not limited to this, and other clock signals CK1, CK2, CK3, CK4, XCK1, XCK2, XCK3, XCK4, The manner in which the upper-level driving signal and the lower-level driving signal generate the driving signals G(1)-G(n+1) and GB(1)-GB(n+1) is also within the scope of the present disclosure.

FIG. 3 is a circuit diagram of the driving unit 300 in the driving device according to an embodiment of the present application. Please refer to FIG. 2 and FIG. 3 , the driving unit 300 is an embodiment of the driving unit DU(n).

As shown in FIG. 3, the driving unit 300 is used for receiving the clock signals CK3, XCK1, XCK3, the upper-level driving signal G(n-1) and the lower-level driving signal G(n+1) to generate the driving signals G(n) and GB(n). The driving unit 300 includes start-up circuits 310 and 320 , voltage regulator circuits 330 and 340 and an output circuit 350 .

As shown in FIG. 3, the start-up circuit 310 is used to adjust the voltage level of the node voltage Q(n) of the node N31 according to the driving signals G(n-1) and G(n+1) and the voltage signals U2D and D2U. In some embodiments, the start-up circuit 310 is used to turn on the driving signal G(n-1) or G(n+1) so that the corresponding voltage signal U2D or D2U is written to the node N31.

As shown in FIG. 3, the start-up circuit 320 is used to adjust the voltage level of the node voltage K(n) of the node N32 according to the driving signals G(n-1) and G(n+1) and the voltage signals U2D and D2U. In some embodiments, the start-up circuit 320 is turned on according to the driving signal G(n-1) or G(n+1) so that the corresponding voltage signal U2D or D2U is written into the node N32.

In some embodiments, the voltage signal U2D has the enable voltage level VGH and the voltage signal D2U has the disable voltage level VGL, for example, the embodiment corresponding to the operation described in FIG. 4 . In some embodiments, the voltage signal D2U has an enable voltage level VGH and the voltage signal U2D has a disable voltage level VGL, for example, the embodiment corresponding to the operation described in FIG. 5 . Details regarding the embodiments of Figures 4 and 5 are further described below.

As shown in FIG. 3, the voltage stabilizing circuit 330 is used for stabilizing the node voltage Q(n) of the node N31 and the node voltage P(n) of the node N33 according to the clock signal CK3, and used for stabilizing the node voltage Q(n) according to the node voltage Q(n). The node voltage P(n) of the node N33 is pressed.

As shown in FIG. 3, the voltage stabilizing circuit 340 is used for stabilizing the node voltage K(n) of the node N32 according to the clock signal CK3, and for adjusting the node voltage K(n) according to the clock signal XCK3.

As shown in FIG. 3, the output circuit 350 is used to adjust the node voltage of the node N34 according to the node voltage Q(n) and the node voltage K(n), and to output the driving signal GB(n) from the node N34. As shown in FIG. 3, the output circuit 350 is further configured to adjust the node voltage of the node N35 according to the node voltage Q(n) and the node voltage P(n), and to output the driving signal G(n) from the node N35.

The operation mode of the internal circuit of the driving unit 300 is disclosed as above, but the embodiment of the present invention is not limited thereto, and other operation modes of the start-up circuits 310 , 320 , the voltage regulator circuits 330 , 340 and the output circuit 350 are also within the scope of the present disclosure. .

As shown in FIG. 3, the start-up circuit 310 includes switches T33 and T34. The control end of the switch T33 is used for receiving the driving signal G(n-1), one end of the switch T33 is coupled to the node N31, and the other end of the switch T33 is used for receiving the voltage signal U2D. The control end of the switch T34 is used for receiving the driving signal G(n+1), one end of the switch T34 is coupled to the node N31, and the other end of the switch T34 is used for receiving the voltage signal D2U.

As shown in FIG. 3, the start-up circuit 320 includes switches T310 and T39. The control end of the switch T310 is used for receiving the driving signal G(n+1), one end of the switch T310 is coupled to the node N32, and the other end of the switch T310 is used for receiving the voltage signal U2D. The control end of the switch T39 is used for receiving the driving signal G(n-1), one end of the switch T39 is coupled to the node N32, and the other end of the switch T39 is used for receiving the voltage signal D2U.

As shown in FIG. 3, the voltage regulator circuit 330 includes switches T35-T37. The control end of the switch T35 is used for receiving the clock signal CK3, one end of the switch T35 is coupled to the node N31, and the other end of the switch T35 is used for receiving the voltage signal GL. The control end of the switch T36 is coupled to the node N31, one end of the switch T36 is coupled to the node N33, and the other end of the switch T36 is used for receiving the voltage signal GL. The control end of the switch T37 is used for receiving the clock signal CK3, one end of the switch T37 is coupled to the node N33, and the other end of the switch T37 is used for receiving the voltage signal GH.

As shown in FIG. 3, the voltage regulator circuit 340 includes a switch T38 and a capacitor C32. The control end of the switch T38 is used for receiving the clock signal CK3, one end of the switch T38 is coupled to the node N32, and the other end of the switch T38 is used for receiving the voltage signal GH. One end of the capacitor C32 is coupled to the node N32, and the other end of the capacitor C32 is used for receiving the clock signal XCK3.

As shown in FIG. 3 , the output circuit 350 includes switches T311 , T312 , T321 , T322 and a capacitor C31 . The control end of the switch T311 is coupled to the node N31, one end of the switch T311 is coupled to the node N35, and the other end of the switch T311 is used for receiving the clock signal XCK1. The control end of the switch T312 is coupled to the node N31, one end of the switch T312 is coupled to the node N34, and the other end of the switch T312 is used for receiving the clock signal XCK1. The control end of the switch T321 is coupled to the node N33, one end of the switch T321 is coupled to the node N35, and the other end of the switch T321 is used for receiving the voltage signal GL. The control end of the switch T322 is coupled to the node N32, one end of the switch T322 is coupled to the node N34, and the other end of the switch T322 is used for receiving the voltage signal GH. One end of the capacitor C31 is coupled to the node N31, and the other end of the capacitor C31 is coupled to the node N35.

In some embodiments, switches T311, T312, T321 and T322 are low temperature polysilicon thin film transistors (Low Temperature Poly-Silicon Thin Film Transistor, LTPS TFT) implementation. LTPS transistors have the characteristics of high current drive, high drive power, and can drive large currents in a small layout area. In some embodiments, T33-T310 are implemented with Indium Gallium Zinc Oxide Thin Film Transistor (IGZO TFT). The IGZO transistor has the characteristics of low leakage current, which can prevent the node voltage inside the driving unit 300 from being affected by the leakage current when outputting the driving signal, thereby affecting the outputted driving signal. In different embodiments, the switches T33 ˜ T312 , T321 and T322 can also be implemented by different switching elements.

FIG. 4 is a timing diagram illustrating a driving operation of the driving unit 300 according to an embodiment of the present disclosure. The timing chart shown in FIG. 4 includes periods P41 to P48 in sequence. In some embodiments, the periods P41 to P48 correspond to one frame time.

In some embodiments, the timing diagram shown in FIG. 4 corresponds to different signals shown in FIG. 2 and FIG. 3, such as clock signals CK1, CK2, CK3, CK4, XCK1, XCK2, XCK3, XCK4 and driving The operation of the signals G(n-1), G(n), G(n+1), GB(n), and the node voltages Q(n), P(n) and K(n) in the driving unit 300 voltage level.

As shown in FIG. 4, in the period P41, the driving signal G(n-1) has the enable voltage level VGH, so that the switches T33 and T39 are turned on. At this time, the switch T33 writes the voltage signal U2D with the enable voltage level VGH to the node N31, so that the node voltage Q(n) of the node N31 has a voltage level (VGH-V _TH33 ), wherein the threshold voltage level V _TH33 is the threshold voltage level of the switch T33. At this time, the switch T39 writes the voltage signal D2U with the disable voltage level VGL to the node N32, so that the node voltage K(n) of the node N32 has the disable voltage level VGL, and the switch T322 is turned off.

During the period P41, the voltage level (VGH-V _TH33 ) of the node voltage Q(n) is the enabling voltage level, so that the switches T36, T311 and T312 are based on the voltage level (VGH-V _TH33 ) of the node voltage Q(n) ) is turned on. In some embodiments, the capacitor C31 is used to store the charge of the node N31 to maintain the voltage level of the node N31 after the switch T33 is turned off, so that the switches T36 , T311 and T312 are continuously turned on after the switch T33 is turned off (for example, during the period P42 ). .

During the period P41, the switch T36 writes the voltage signal GL with the disable voltage level VGL to the node N33, so that the node voltage P(n) of the node N33 has the disable voltage level VGL, and the switch T321 according to the node voltage P( n) close. The switch T311 writes the clock signal XCK1 with the disable voltage level VGL to the node N35 so that the node N35 has the disable voltage level VGL. At this time, the output circuit 350 outputs the driving signal G(n) having the disable voltage level VGL from the node N35. The switch T312 writes the clock signal XCK1 with the disable voltage level VGL to the node N34, so that the node N34 has the disable voltage level VGL. At this time, the output circuit 350 outputs the drive signal GB(n) with the disable voltage level VGL from the node N34.

As shown in FIG. 4, in the period P42, the driving signals G(n-1) and G(n+1) have the disable voltage level VGL, so that the switches T33, T34, T310 and T39 in the activation circuits 310 and 320 are activated closure. At this time, the capacitor C31 maintains the node voltage Q(n) at the enabling voltage level, so that the switches T36, T311 and T312 are turned on.

During the period P42, the switch T36 writes the voltage signal GL with the disable voltage level VGL to the node N33, so that the node voltage P(n) of the node N33 has the disable voltage level VGL, and the switch T321 is based on the node voltage P(n). n) close.

During the period P42, the switch T311 writes the clock signal XCK1 with the enable voltage level VGH to the node N35, so that the node N35 has the enable voltage level VGH. At this time, the output circuit 350 outputs the driving signal G(n) with the enable voltage level VGH from the node N35. The capacitor C21 adjusts the voltage of the node N31 by the voltage of the node N35 through capacitive coupling, so that the voltage level of the node N31 is adjusted to a voltage level VQ greater than the voltage level (VGH+V _THLTPS ), wherein the threshold voltage level V _THLTPS is the threshold voltage level of switch T311. In some embodiments, the switch T311 is implemented with an LTPS transistor, and the threshold voltage level V _THLTPS is the threshold voltage level of the LTPS transistor.

During the period P42, the switch T312 writes the clock signal XCK1 with the enable voltage level VGH to the node N34, so that the node N34 has the enable voltage level VGH. At this time, the output circuit 350 outputs the driving signal GB(n) with the enable voltage level VGH from the node N34.

As shown in FIG. 4, in the period P43, the driving signal G(n+1) has the enable voltage level VGH, so that the switches T34 and T310 are turned on. The clock signal CK3 has the enable voltage level VGH, so that the switches T35, T37 and T38 are turned on.

During the period P43, the switch T34 writes the voltage signal D2U with the disable voltage level VGL to the node N31, so that the node voltage Q(n) of the node N31 has the disable voltage level VGL. The switch T35 writes the voltage signal GL with the disable voltage level VGL to the node N31 to further stabilize the node voltage Q(n).

During the period P43, the switch T37 writes the voltage signal GH with the enable voltage level VGH to the node N33, so that the node voltage P(n) of the node N33 has the voltage level (VGH-V _TH37 ), wherein the threshold voltage level V _TH37 is the threshold voltage level of switch T37.

In some embodiments, during the period P43, the voltage level (VGH-V _TH37 ) is the enabling voltage level, so that the switch T321 is turned on according to the voltage level (VGH-V _TH37 ) of the node voltage P(n). In some embodiments, the parasitic capacitance of the node N33 is used to store the charge of the node N33 to maintain the voltage level of the node N33 after the switch T37 is turned off, so that the switch T321 is continuously turned on after the switch T37 is turned off (eg, during the period P44 ).

During the period P43, the switch T321 writes the voltage signal GL having the disable voltage level VGL to the node N35. At this time, the output circuit 350 outputs the driving signal G(n) having the disable voltage level VGL from the node N35.

During the period P43, the switch T310 writes the voltage signal U2D with the enable voltage level VGH to the node N32 to adjust the node voltage K(n) of the node N32. The switch T38 writes the voltage signal GH with the enable voltage level VGH to the node N32 to further stabilize the node voltage K(n). At this time, the node voltage K(n) has a voltage level (VGH-V _TH310 ) or (VGH-V _TH38 ), wherein the threshold voltage levels V _TH38 and V _TH310 are the threshold voltage levels of the switches T38 and T310 , respectively. In some embodiments, the threshold voltage levels V _TH38 and V _{TH310 are} substantially equal. The following description will be given by the case where the node voltage K(n) has a voltage level (VGH-V _TH38 ), but the case where the node voltage K(n) has a voltage level (VGH-V _TH310 ) is also considered in the embodiment of the present invention and within range.

During the period P43, the capacitor C32 is used to store electric charges to further increase the node voltage K(n) after the period P43 (eg, during the period P44).

During the period P43, the parasitic capacitance of the node N34 maintains the node voltage of the node N34 at the enable voltage level VGH. At this time, the output circuit 350 outputs the driving signal GB(n) with the enable voltage level VGH from the node N34.

As shown in FIG. 4, in the period P44, the driving signals G(n-1) and G(n+1) have the disable voltage level VGL, so that the switches T33, T34, T310 and T39 in the activation circuits 310 and 320 are activated closure. At this time, the parasitic capacitance of the node N33 maintains the node voltage P(n) at the enabling voltage level, so that the switch T321 is turned on. The switch T321 writes the voltage signal GL with the disable voltage level VGL to the node N35, so that the node N35 has the disable voltage level VGL. At this time, the output circuit 350 outputs the driving signal G(n) having the disable voltage level VGL from the node N35.

From the period P43 to the period P44, the capacitor C32 maintains the node voltage K(n) at the enabling voltage level. During the period P44, the capacitor C32 is used to receive the clock signal XCK3 with the enable voltage level VGH, and further boost the node voltage K(n) through capacitive coupling. At this time, the node voltage K(n) has a voltage level VK higher than the voltage level (VGH+V _THLTPS ), so that the switch T322 is turned on. The switch T322 writes the voltage signal GH with the enable voltage level VGH into the node N34, so that the node N34 has the enable voltage level VGH. At this time, the output circuit 350 outputs the driving signal GB(n) with the enable voltage level VGH from the node N34.

As shown in FIG. 4, in the periods P45-P46, the ON or OFF states of the switches T33-T312, T321 and T322 are the same as those in the period P44, and have similar operations. Therefore, the similarities between the operations of the periods P45 to P46 and the operations of the period P44 will not be repeated here.

During the period P45~P46, the switches T321 and T322 are turned on according to the node voltages P(n) and K(n), respectively, so that the switch T321 provides a voltage signal GL with a disable voltage level VGL to the node N35, and T322 provides a voltage signal GL with an enable voltage level VGL. The voltage signal GH of the voltage level VGH is sent to the node N34. Correspondingly, the output circuit 350 outputs the drive signal G(n) with the disable voltage level VGL from the node N35, and the output circuit 350 outputs the drive signal GB(n) with the enable voltage level VGH from the node N34. In other words, in the periods P45 to P46, the voltage stabilizing circuits 330 and 340 stabilize the driving signals G(n) and GB(n) by the node voltages P(n) and K(n).

As shown in FIG. 4 , in the period P47 , the clock signal CK3 has the enable voltage level VGH, so that the switches T35 , T37 and T38 are turned on. The switch T35 writes the voltage signal GL to the node N31 so that the node voltage Q(n) has the disable voltage level VGL. The switch T37 writes the voltage signal GH to the node N33 so that the node voltage P(n) has a voltage level (VGH-V _TH37 ).

During the period P47, the switch T321 is turned on according to the voltage level (VGH-V _TH37 ) of the node voltage P(n), and the voltage signal GL is written to the node N35. At this time, the output circuit 350 outputs the driving signal G(n) having the disable voltage level VGL from the node N35.

During the period P47, the switch T38 writes the voltage signal GH to the node N32, and the clock signal XCK3 received by the capacitor C32 has the disable voltage level VGL, so that the node voltage K(n) has the voltage level (VGH-V _TH38 ). At this time, the parasitic capacitance of the node N34 maintains the voltage level of the driving signal GB(n) at the enabling voltage level VGH.

As shown in FIG. 4 , in the period P48 , the clock signal CK3 has the disable voltage level VGL, so that the switches T35 , T37 and T38 are turned off. The driving signals G(n-1) and G(n+1) have the disable voltage level VGL, so that the switches T33, T34, T310 and T39 in the start-up circuits 310 and 320 are turned off.

During the period P48, the node voltage Q(n) has the disable voltage level VGL, so that the switches T36, T311 and T312 are turned off. The parasitic capacitance of the node N33 maintains the node voltage P(n) at (VGH-V _TH37 ), so that the switch T321 is turned on. The switch T321 writes the voltage signal GL with the disable voltage level VGL to the node N35, so that the node N35 has the disable voltage level VGL. At this time, the output circuit 350 outputs the driving signal G(n) having the disable voltage level VGL from the node N35.

From the period P47 to the period P48, the capacitor C32 maintains the node voltage K(n) at the enabling voltage level. During the period P48, the capacitor C32 is used to receive the clock signal XCK3 with the enable voltage level VGH, and further boost the node voltage K(n) through capacitive coupling. At this time, the node voltage K(n) has a voltage level VK higher than the voltage level (VGH+V _THLTPS ), so that the switch T322 is turned on. The switch T322 writes the voltage signal GH with the enable voltage level VGH into the node N34, so that the node N34 has the enable voltage level VGH. At this time, the output circuit 350 outputs the driving signal GB(n) with the enable voltage level VGH from the node N34.

To sum up, the driving unit 300 generates the driving signal GB(n) which is complementary to the driving signal G(n-1) through the operations of the periods P41 to P48. As shown in FIG. 4, in the periods P41 to P48, when the driving signal G(n-1) has the enable voltage level VGH, the driving signal GB(n) has the disable voltage level VGL, and when the driving signal G(n-1) has the enable voltage level VGH, When G(n-1) has the disable voltage level VGL, the driving signal GB(n) has the enable voltage level VGH.

Similarly, the driving unit 300 generates the driving signal G(n) which is complementary to the driving signal GB(n+1) through the operations of the periods P41 to P48. The driving signal GB(n+1) can be generated by the driving unit DU(n+1) shown in FIG. 2 .

In some embodiments, the driving device 120 shown in FIG. 1 drives the pixel driving circuit 112 by the complementary driving signal G(n-1) and the driving signal GB(n).

FIG. 5 is a timing diagram illustrating a driving operation of the driving unit 300 according to an embodiment of the present disclosure. The timing chart shown in FIG. 5 includes periods P51 to P58 in sequence. In some embodiments, the periods P51 to P58 correspond to one frame time.

In some embodiments, the timing diagram shown in FIG. 5 corresponds to different signals shown in FIG. 2 and FIG. 3, such as clock signals CK1, CK2, CK3, CK4, XCK1, XCK2, XCK3, XCK4 and driving The operation of the signals G(n-1), G(n), G(n+1), GB(n), and the node voltages Q(n), P(n) and K(n) in the driving unit 300 voltage level.

As shown in FIG. 5, in the period P51, the driving signal G(n+1) has the enable voltage level VGH, so that the switches T34 and T310 are turned on. At this time, the switch T34 writes the voltage signal D2U with the enable voltage level VGH to the node N31, so that the node voltage Q(n) of the node N31 has a voltage level (VGH-V _TH34 ), wherein the threshold voltage level V _TH34 is the threshold voltage level of switch T34. At this time, the switch T310 writes the voltage signal U2D with the disable voltage level VGL to the node N32, so that the node voltage K(n) of the node N32 has the disable voltage level VGL, and the switch T322 is turned off.

During the period P51, the voltage level (VGH-V _TH34 ) of the node voltage Q(n) is the enabling voltage level, so that the switches T36, T311 and T312 are based on the voltage level (VGH-V _TH34 ) of the node voltage Q(n) ) is turned on. In some embodiments, the capacitor C31 is used to store the charge of the node N31 to maintain the voltage level of the node N31 after the switch T34 is turned off, so that the switches T36 , T311 and T312 are continuously turned on after the switch T33 is turned off (eg, during the period P52 ). .

During the period P51, the switch T36 writes the voltage signal GL with the disable voltage level VGL to the node N33, so that the node voltage P(n) of the node N33 has the disable voltage level VGL, and the switch T321 according to the node voltage P( n) close. The switch T311 writes the clock signal XCK1 with the disable voltage level VGL to the node N35 so that the node N35 has the disable voltage level VGL. At this time, the output circuit 350 outputs the driving signal G(n) having the disable voltage level VGL from the node N35. The switch T312 writes the clock signal XCK1 with the disable voltage level VGL to the node N34, so that the node N34 has the disable voltage level VGL. At this time, the output circuit 350 outputs the drive signal GB(n) with the disable voltage level VGL from the node N34.

As shown in FIG. 4, in the period P52, the driving signals G(n-1) and G(n+1) have the disable voltage level VGL, so that the switches T33, T34, T310 and T39 in the activation circuits 310 and 320 are activated closure. At this time, the capacitor C31 maintains the node voltage Q(n) at the enabling voltage level, so that the switches T36, T311 and T312 are turned on.

During the period P52, the switch T36 writes the voltage signal GL with the disable voltage level VGL to the node N33, so that the node voltage P(n) of the node N33 has the disable voltage level VGL, and the switch T321 is based on the node voltage P(n). n) close.

During the period P52, the switch T311 writes the clock signal XCK1 with the enable voltage level VGH to the node N35, so that the node N35 has the enable voltage level VGH. At this time, the output circuit 350 outputs the driving signal G(n) with the enable voltage level VGH from the node N35. The capacitor C21 adjusts the voltage of the node N31 by the voltage of the node N35 through capacitive coupling, so that the voltage level of the node N31 is adjusted to the voltage level VQ.

During the period P52, the switch T312 writes the clock signal XCK1 with the enable voltage level VGH to the node N34, so that the node N34 has the enable voltage level VGH. At this time, the output circuit 350 outputs the driving signal GB(n) with the enable voltage level VGH from the node N34.

As shown in FIG. 5, in the period P53, the driving signal G(n-1) has the enable voltage level VGH, so that the switches T33 and T39 are turned on. The clock signal CK3 has the enable voltage level VGH, so that the switches T35, T37 and T38 are turned on.

During the period P53, the switch T34 writes the voltage signal U2D with the disable voltage level VGL to the node N31, so that the node voltage Q(n) of the node N31 has the disable voltage level VGL. The switch T35 writes the voltage signal GL with the disable voltage level VGL to the node N31 to further stabilize the node voltage Q(n).

During the period P53, the switch T37 writes the voltage signal GH with the enable voltage level VGH to the node N33, so that the node voltage P(n) of the node N33 has the voltage level (VGH-V _TH37 ).

During the period P53, the voltage level (VGH-V _TH37 ) of the node voltage P(n) is the enabling voltage level, so that the switch T321 is turned on. In some embodiments, the parasitic capacitance of the node N33 is used to store the charge of the node N33 to maintain the voltage level of the node N33 after the switch T37 is turned off, so that the switch T321 is continuously turned on after the switch T37 is turned off (eg, in the period P54 ).

During the period P53, the switch T321 writes the voltage signal GL having the disable voltage level VGL to the node N35. At this time, the output circuit 350 outputs the driving signal G(n) having the disable voltage level VGL from the node N35.

During the period P53, the switch T39 writes the voltage signal D2U with the enable voltage level VGH to the node N32 to adjust the node voltage K(n) of the node N32. The switch T38 writes the voltage signal GH with the enable voltage level VGH to the node N32 to further stabilize the node voltage K(n). At this time, the node voltage K(n) has a voltage level (VGH-V _TH39 ) or (VGH-V _TH38 ), wherein the threshold voltage level V _TH39 is the threshold voltage level of the switch T39 . In some embodiments, the threshold voltage levels V _TH38 and V _{TH39 are} substantially equal. The following description will be given by the case where the node voltage K(n) has a voltage level (VGH-V _TH38 ), but the case where the node voltage K(n) has a voltage level (VGH-V _TH39 ) is also considered in the embodiment of the present invention. and within range.

During the period P53, the capacitor C32 is used to store charges to further increase the node voltage K(n) after the period P53 (eg, during the period P54).

During the period P53, the parasitic capacitance of the node N34 maintains the node voltage of the node N34 at the enable voltage level VGH. At this time, the output circuit 350 outputs the driving signal GB(n) with the enable voltage level VGH from the node N34.

As shown in FIG. 5, in the period P54, the driving signals G(n-1) and G(n+1) have the disable voltage level VGL, so that the switches T33, T34, T310 and T39 in the activation circuits 310 and 320 are activated closure. At this time, the parasitic capacitance of the node N33 maintains the node voltage P(n) at the enabling voltage level, so that the switch T321 is turned on. The switch T321 writes the voltage signal GL with the disable voltage level VGL to the node N35, so that the node N35 has the disable voltage level VGL. At this time, the output circuit 350 outputs the driving signal G(n) having the disable voltage level VGL from the node N35.

From the period P53 to the period P54, the capacitor C32 maintains the node voltage K(n) at the enabling voltage level. During the period P54, the capacitor C32 is used to receive the clock signal XCK3 with the enable voltage level VGH, and further boost the node voltage K(n) through capacitive coupling. At this time, the node voltage K(n) has a voltage level VK higher than the voltage level (VGH+V _THLTPS ), so that the switch T322 is turned on. The switch T322 writes the voltage signal GH with the enable voltage level VGH into the node N34, so that the node N34 has the enable voltage level VGH. At this time, the output circuit 350 outputs the driving signal GB(n) with the enable voltage level VGH from the node N34.

As shown in FIG. 5, in the periods P55-P56, the ON or OFF states of the switches T33-T312, T321 and T322 are the same as those in the period P54, and have similar operations. Therefore, the similarities between the operations of the periods P55 to P56 and the operations of the period P54 will not be repeated here.

During the period P55~P56, the switches T321 and T322 are turned on according to the node voltages P(n) and K(n), respectively, so that the switch T321 provides a voltage signal GL with a disable voltage level VGL to the node N35, and T322 provides a voltage signal GL with an enable voltage level VGL. The voltage signal GH of the voltage level VGH is sent to the node N34. Correspondingly, the output circuit 350 outputs the drive signal G(n) with the disable voltage level VGL from the node N35, and the output circuit 350 outputs the drive signal GB(n) with the enable voltage level VGH from the node N34. In other words, in the periods P55 to P56, the voltage stabilization circuits 330 and 340 stabilize the driving signals G(n) and GB(n) by the node voltages P(n) and K(n).

As shown in FIG. 5, in the period P57, the clock signal CK3 has the enable voltage level VGH, so that the switches T35, T37 and T38 are turned on. The switch T35 writes the voltage signal GL to the node N31 so that the node voltage Q(n) has the disable voltage level VGL. The switch T37 writes the voltage signal GH to the node N33 so that the node voltage P(n) has a voltage level (VGH-V _TH37 ).

In the period P57, the switch T321 is turned on according to the voltage level (VGH-V _TH37 ) of the node voltage P(n), and the voltage signal GL is written to the node N35. At this time, the output circuit 350 outputs the driving signal G(n) having the disable voltage level VGL from the node N35.

During the period P57, the switch T38 writes the voltage signal GH to the node N32, and the clock signal XCK3 received by the capacitor C32 has the disable voltage level VGL, so that the node voltage K(n) has the voltage level (VGH-V _TH38 ). At this time, the parasitic capacitance of the node N34 maintains the voltage level of the driving signal GB(n) at the enabling voltage level VGH.

As shown in FIG. 4 , in the period P58 , the clock signal CK3 has the disable voltage level VGL, so that the switches T35 , T37 and T38 are turned off. The driving signals G(n-1) and G(n+1) have the disable voltage level VGL, so that the switches T33, T34, T310 and T39 in the start-up circuits 310 and 320 are turned off.

During the period P58, the node voltage Q(n) has the disable voltage level VGL, so that the switches T36, T311 and T312 are turned off. The parasitic capacitance of the node N33 maintains the node voltage P(n) at (VGH-V _TH37 ), so that the switch T321 is turned on. The switch T321 writes the voltage signal GL with the disable voltage level VGL to the node N35, so that the node N35 has the disable voltage level VGL. At this time, the output circuit 350 outputs the driving signal G(n) having the disable voltage level VGL from the node N35.

From the period P57 to the period P58, the capacitor C32 maintains the node voltage K(n) at the enabling voltage level. During the period P58, the capacitor C32 is used to receive the clock signal XCK3 with the enable voltage level VGH, and further boost the node voltage K(n) through capacitive coupling. At this time, the node voltage K(n) has a voltage level VK higher than the voltage level (VGH+V _THLTPS ), so that the switch T322 is turned on. The switch T322 writes the voltage signal GH with the enable voltage level VGH into the node N34, so that the node N34 has the enable voltage level VGH. At this time, the output circuit 350 outputs the driving signal GB(n) with the enable voltage level VGH from the node N34.

To sum up, the driving unit 300 generates the driving signal GB(n) which is complementary to the driving signal G(n+1) through the operations of the periods P51 to P58. As shown in FIG. 5, in the periods P51 to P58, when the driving signal G(n+1) has the enable voltage level VGH, the driving signal GB(n) has the disable voltage level VGL, and when the driving signal G(n+1) has the enable voltage level VGH, When G(n+1) has the disable voltage level VGL, the driving signal GB(n) has the enable voltage level VGH.

Similarly, the driving unit 300 generates the driving signal G(n) which is complementary to the driving signal GB(n-1) through the operations of the periods P51 to P58. The driving signal GB(n-1) can be generated by the driving unit DU(n-1) in the driving device 200 shown in FIG. 2 .

Referring to FIG. 4 and FIG. 5, in periods P41-P44, the clock signals CK1-CK4 are sequentially pulled to the enable voltage level VGH, and the clock signals XCK1-XCK4 are sequentially pulled to the disable voltage Level VGL. Correspondingly, in the embodiment corresponding to FIG. 4 , the driving signals G(n-1), G(n) and G(n+1) are sequentially pulled to the enable voltage level VGH. In some embodiments, the operation shown in FIG. 4 is referred to as a forward transmission of a drive (eg, drive 200 shown in FIG. 2).

On the contrary, in the period P51~P54, the clock signals CK1, CK4, CK3, and CK2 are sequentially pulled to the enable voltage level VGH, and the clock signals XCK1, XCK4, XCK3, and XCK2 are sequentially pulled to the disable voltage. Level VGL. Correspondingly, in the embodiment corresponding to FIG. 5 , the driving signals G(n+1), G(n) and G(n-1) are sequentially pulled to the enable voltage level VGH. In some embodiments, the operation shown in FIG. 5 is referred to as a reverse transmission of a drive (eg, drive 200 shown in FIG. 2).

In some previous approaches, the gate driver has only one-way transfer function, and can only perform one of forward transfer or reverse transfer.

Compared with the above method, in the embodiment of the present invention, the driving device 200 and the driving unit 300 shown in FIG. 2 and FIG. 3 can perform forward transmission and reverse transmission.

The various driving methods and transmission methods mentioned above in this case are for illustration, and other various driving methods and transmission methods are within the scope of this case.

To sum up, in the embodiment of the present invention, forward transmission or reverse transmission can be performed by adjusting the voltage levels of the voltage signals U2D and D2U received by the driving unit 300 . In addition, the configuration of the capacitor C32 periodically raises the node voltage K(n) by the clock signal XCK3 to turn on the regulated driving signal GB(n) of the switch T322, and the regulated time is as long as 75% of the frame time. Through the configuration of the node voltages P(n) and Q(n), the switch T321 is turned on in the periods P43~P48 and P53~P58 to stabilize the driving signal G(n) for a long time. In addition, the configuration of the LTPS transistor and the IGZO transistor corresponding to the switches T33-T312, T321 and T322 can reduce the leakage current, drive a larger current and reduce the layout area occupied.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

100: Monitor

110: Display device

120, 200: drive device

130: Data input device

140: Lighting control device

SL(0)~SL(n): drive line

G(1)~G(n+1), GB(1)~GB(n+1): drive signal

DL(1)~DL(m): Data line

EL(1)~EL(n): luminous line

DV(1)~DV(n), 112: pixel drive circuit

CK1, CK2, CK3, CK4, XCK1, XCK2, XCK3, XCK4: Clock signal

DU(1)~DU(n+1), 300: drive unit

ST: start signal

RST: reset signal

T33~T312, T321, T322: switch

C31, C32: Capacitor

310, 320: start circuit

330, 340: voltage regulator circuit

350: Output circuit

U2D, D2U, GL, GH: Voltage signal

VGL: disable voltage level

VGH: enable voltage level

N31~N35: Node

P(n), Q(n), K(n): node voltage

P41~P48, P51~P58: Period V _TH33 , V _TH37 , V _TH38 , V _TH310 , V _THLTPS : Threshold voltage level

FIG. 1 is a schematic diagram of a display according to an embodiment of the present application. FIG. 2 is a schematic diagram of a driving device according to an embodiment of the present application. FIG. 3 is a circuit diagram of a driving unit in a driving device according to an embodiment of the present application. FIG. 4 is a timing diagram illustrating a driving operation of the driving unit according to an embodiment of the present disclosure. FIG. 5 is a timing diagram illustrating the driving operation of the driving unit according to an embodiment of the present disclosure.

Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none

CK3, XCK1, XCK3: clock signal

300: Drive unit

T33~T312, T321, T322: switch

C31, C32: Capacitor

310, 320: start circuit

330, 340: voltage regulator circuit

350: Output circuit

U2D, D2U, GL, GH: Voltage signal

N31~N35: Node

P(n), Q(n), K(n): node voltage

Claims (17)

A drive device, comprising: a first start-up circuit for adjusting a first node voltage of a first node according to a first driving signal in a first period, and for adjusting the first node according to a second driving signal in a second period Voltage; a second start-up circuit for adjusting a second node voltage of a second node according to the first driving signal during the first period, and for adjusting the second node according to the second driving signal during the second period voltage; and an output circuit for outputting a third driving signal and for adjusting the third driving signal to a first voltage level according to the first node voltage during the first period, and for adjusting the third driving signal to a first voltage level according to the first node voltage during a third period The second node voltage adjusts the third driving signal to a second voltage level, wherein the first period, the second period and the third period are arranged in sequence, and The first driving signal has the second voltage level during the first period and has the first voltage level during the third period. The drive device as claimed in claim 1, wherein The first start-up circuit includes: a first switch, a control terminal of the first switch is used for receiving the first driving signal, a first terminal of the first switch is coupled to the first node; and a second switch, a control end of the second switch is used for receiving the second driving signal, a first end of the second switch is coupled to the first node; and The second startup circuit includes: a third switch, a control terminal of the third switch is used for receiving the first driving signal, a first terminal of the third switch is coupled to the second node; and a fourth switch, a control terminal of the fourth switch is used for receiving the second driving signal, and a first terminal of the fourth switch is coupled to the second node. The driving device according to claim 1, further comprising: A capacitor is coupled to the second node and used for receiving a clock signal during the third period to pull the voltage of the second node to a third voltage level higher than the second voltage level. The driving device as claimed in claim 3, wherein the output circuit further comprises: a first switch, a control end of the first switch is coupled to the first node, a first end of the first switch is used for outputting the third driving signal; and a second switch, a control end of the second switch is coupled to the second node, and a first end of the second switch is coupled to the first end of the first switch. The driving device of claim 1, wherein the output circuit is further configured to adjust the third driving signal to the second voltage level according to the first node voltage in a fourth period, and The first period, the fourth period, the second period and the third period are arranged sequentially and consecutively. The driving device of claim 5, wherein the output circuit is further used for outputting a fourth driving signal, and used for adjusting the fourth driving signal to the first voltage level according to the first node voltage during the first period , and is used for adjusting the fourth driving signal to the second voltage level according to the first node voltage during the fourth period. The driving device according to claim 6, further comprising: a first switch, a control end of the first switch is coupled to the first node, Wherein the output circuit includes: a second switch, a control end of the second switch is coupled to the first node, a first end of the second switch is used for outputting the fourth driving signal; and A third switch, a control end of the third switch is coupled to a first end of the first switch, and a first end of the third switch is coupled to the first end of the second switch. The driving device as claimed in claim 7, further comprising: a fourth switch, a first end of the fourth switch is coupled to the first node, and a control end of the fourth switch is used for receiving a clock signal; a fifth switch, a first end of the fifth switch is coupled to the first end of the first switch, and a control end of the fifth switch is used for receiving the clock signal; and a sixth switch, a first end of the sixth switch is coupled to the second node, and a control end of the sixth switch is used for receiving the clock signal. The driving device of claim 8, wherein the first switch, the fourth switch, the fifth switch and the sixth switch are indium gallium zinc oxide thin film transistors, and the second switch and the third switch are Low temperature polysilicon thin film transistors. A display, comprising a display device and a driving device for driving the display device, the driving device comprising: a first driving unit for generating a second driving signal according to a first driving signal; a second driving unit for generating a third driving signal according to the first driving signal; a third drive unit, including: a first start-up circuit for adjusting a first node voltage of a first node according to the second driving signal in a first period, and for adjusting the first node according to the third driving signal in a second period Voltage; a second start-up circuit for adjusting a second node voltage of a second node according to the second driving signal during the first period, and for adjusting the second node according to the third driving signal during the second period voltage; and an output circuit for outputting a fourth driving signal and for adjusting the fourth driving signal to a first voltage level according to the first node voltage during the first period, and for adjusting the fourth driving signal to a first voltage level according to the first node voltage during a third period The second node voltage adjusts the fourth driving signal to a second voltage level, wherein the first period, the second period and the third period are arranged in sequence, and The second driving signal has the second voltage level during the first period and has the first voltage level during the third period. The display of claim 10, further comprising: A capacitor is coupled to the second node for receiving a first clock signal during the third period to pull the voltage of the second node to a third voltage level higher than the second voltage level. The display of claim 11, wherein the output circuit comprises: a first switch, a control end of the first switch is coupled to the first node, a first end of the first switch is used for outputting the fourth driving signal, and a second end of the first switch is used for receiving a second clock signal; and a second switch, a control end of the second switch is coupled to the first node, a first end of the second switch is used for outputting the first driving signal, and a second end of the second switch is used for receiving the second clock signal. The display of claim 12, wherein The first driving unit is further configured to generate the second driving signal according to a third clock signal and a fourth clock signal, The second driving unit is further configured to generate the third driving signal according to the third clock signal and the fourth clock signal, The second clock signal, the third clock signal, the first clock signal and the fourth clock signal have the the first voltage level, and The first period, the fourth period, the second period and the third period are arranged sequentially and consecutively. The display of claim 12, wherein The first driving unit is further configured to generate the second driving signal according to a third clock signal and a fourth clock signal, The second driving unit is further configured to generate the third driving signal according to the third clock signal and the fourth clock signal, The second clock signal, the fourth clock signal, the first clock signal and the third clock signal have the the first voltage level, and The first period, the fourth period, the second period and the third period are arranged sequentially and consecutively. The display of claim 10, further comprising: a first switch, a first end of the first switch is used for outputting the first driving signal; a second switch, a first end of the second switch is coupled to the first node, and a control end of the second switch is used for receiving a first clock signal; a third switch, a first end of the third switch is coupled to a control end of the first switch, and a control end of the third switch is used for receiving the first clock signal; and a fourth switch, a first end of the fourth switch is coupled to the second node, and a control end of the fourth switch is used for receiving the first clock signal. The display of claim 15, wherein The first driving unit is further configured to generate the second driving signal according to a second clock signal, The second driving unit is further configured to generate the third driving signal according to a third clock signal, The second clock signal, the first clock signal and the third clock signal respectively have the second voltage level in a fourth period, the second period and the third period, and The first period, the fourth period, the second period and the third period are arranged sequentially and consecutively. The display of claim 15, wherein The first driving unit is further configured to generate the second driving signal according to a second clock signal, The second driving unit is further configured to generate the third driving signal according to a third clock signal, The second clock signal, the first clock signal and the third clock signal have the second voltage level during the third period, the second period and a fourth period, respectively, and The first period, the fourth period, the second period and the third period are arranged sequentially and consecutively.

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