TW201340069A - Display device and method for generating scanning signal thereof - Google Patents

Abstract

A displaying device and a method for generating a scanning signal are provided. The method includes the following steps. A output enable signal and a shading control signal are received. A plurality of scanning signals are sequentially outputted to a display panel according to the output enable signal. A part of the scanning signals are performed shading process according to the shading control signal.

Description

Display device and scanning signal generating method thereof

The present invention relates to a display technology, and more particularly to a display device and a scan signal generating method thereof.

With the evolution of optoelectronics and semiconductor technology, the display panel has been booming. Among many displays, liquid crystal displays (LCDs) have recently been widely used, and replace cathode ray tube (CRT) displays as the mainstream of next-generation displays. Generally, the liquid crystal display panel is mainly composed of an active device array substrate, an opposite substrate, and a liquid crystal layer sandwiched between the active device array substrate and the opposite substrate, wherein the active device array substrate has a plurality of arrays of pixels. And each pixel includes an active component and a pixel electrode electrically connected to the active component.

In the case of an active device array substrate, the voltage of the pixel electrode has a voltage difference when the active element of each pixel is turned on and off, and the voltage difference is mainly due to the parasitic capacitance of the active device, and the voltage is The difference is generally referred to as a feed-through voltage. However, the feedthrough voltage causes adverse effects such as flicker on the liquid crystal display panel. Therefore, how to reduce the influence of the feedthrough voltage has become an important issue in designing a liquid crystal display.

The invention provides a display device and a scanning signal generating method thereof, which can improve the feedthrough effect of the display panel, save power consumption of driving the display panel, and reduce noise generated when the display panel is driven.

The invention provides a display device comprising a display panel and a gate drive circuit. The gate driving circuit is coupled to the display panel and configured to receive the chamfering control signal and the output enable signal. The gate driving circuit sequentially outputs a plurality of scanning signals to the display panel according to the output enable signal, and chamfers the portions of the scanning signals according to the chamfering control signal.

The invention provides a scanning signal generating method, comprising: receiving a chamfering control signal and an output enabling signal; sequentially outputting a plurality of scanning signals to the display panel according to the output enabling signal; and selecting a part of the scanning signals according to the chamfering control signal Perform chamfering.

Based on the above, the gate driving circuit of the embodiment of the present invention receives the output enable signal and the chamfer control signal, and sequentially outputs a plurality of scan signals according to the output enable signal and according to the chamfer control signal to the portions of the scan signals. By performing the chamfering process, the feedthrough effect of the display panel can be improved, the power consumption of the driving display panel can be saved, and the noise generated when the display panel is driven can be reduced.

The above described features and advantages of the present invention will be more apparent from the following description.

Due to the presence of active elements in the pixels, the voltage of the pixel electrode is reduced by a parasitic capacitance of the active element and a feed through voltage is dropped. This phenomenon is generally referred to as a feed through effect. In the prior art, the entire scan signal is chamfered to reduce the effect of the feed through effect, but at the same time it increases power consumption and causes noise.

1 is a schematic diagram of a display device in accordance with an embodiment of the present invention. 2 is a schematic diagram of the driving waveform of FIG. 1 according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2, in the embodiment, the display device 100 includes a gate driving circuit 101, a gate driver 130, a source driver 140, and a controller 150. The gate driving circuit 101 includes a gate pulse wave modulation. The circuit 110 and the display panel 120 are provided. In the embodiment of the present invention, the display panel 120 can be an active display panel, and can be a display panel of a half source driving (HSD) architecture, that is, two adjacent pixels are shared by one data line. However, the embodiments of the present invention are not limited thereto.

In this embodiment, the gate pulse modulation circuit 110 receives the first gate signal VGH1 and the chamfer control signal YV1C, wherein the first gate signal VGH1 is used to transmit a plurality of first gate pulse signals (eg, GP1_1~GP1_5), and the chamfer control signal YV1C is assumed to be output by the controller 150. The gate pulse modulation circuit 110 performs chamfering on portions of the first gate pulse signals (eg, GP1_1~GP1_5) according to the chamfer control signal YV1C, and sequentially outputs a plurality of second gate pulses. Wave signals (such as GP2_1~GP2_5) form a second gate signal VGH2.

The source driver 140 is controlled by the controller 150 to output a material voltage (eg, VP1 VP5 to VP5) to the display panel 120. The gate driver 130 is electrically connected to the gate pulse modulation circuit 110, the display panel 120, and the controller 150, and sequentially according to the second gate pulse signals (such as GP2_1~GP2_5) and the output enable signal YOE. A plurality of scan signals (such as SC1 to SC5) are outputted to the display panel 120 to drive the display panel 120 to receive the data voltages (eg, VP1 to VP5), thereby causing the display panel 120 to display the corresponding image.

It is assumed here that the enable level of the chamfer control signal YV1C is a low voltage level, and the enable level of the output enable signal YOE is a high voltage level, and the gate pulse of the embodiment is in one picture period. The wave modulation circuit 110 performs chamfering processing on odd-numbered portions (such as GP1_1, GP1_3, and GP1_5) of the first gate pulse signal (such as GP1_1~GP1_5) according to the chamfer control signal YV1C.

Further, as shown in FIG. 2, the chamfering control signal YV1C is at the enable level in the time interval from t12 to t14, so that the gate pulse modulation circuit 110 will be the first gate pulse signal GP1_1. (i.e., one of the odd-numbered portions of the first gate pulse signal) is chamfered by the portion close to the falling edge, so that the corresponding second gate pulse signal GP2_1 produces a notch at a portion close to the falling edge. The gate pulse wave modulation circuit 110 can discharge a portion of the first gate pulse wave signal GP1_1 close to the falling edge to generate a second gate pulse wave signal GP2_1 having a notch angle, but the embodiment of the present invention The chamfering treatment is not limited to this. Moreover, the output enable signal YOE is at an enable level during the time interval from t11 to t13, so that the gate driver 130 outputs the second gate pulse signal GP2_1 as the scan signal SC1, and the remaining odd first pulse pulses The chamfering processing of the signals (such as GP1_3, GP1_5) is similar to the first gate pulse signal GP1_1, and will not be described here.

On the other hand, in the time interval from t15 to t16, that is, the time interval corresponding to the first gate pulse wave signal GP2_2 (i.e., one of the even portions of the first gate pulse wave signal), the chamfering control signal YV1C Will be disabled, so that the gate pulse modulation circuit 110 does not chamfer the first gate pulse signal GP2_2, and the output enable signal YOE will be in the enable level, so that The gate driver 130 outputs the second gate pulse signal GP2_2 as the scan signal SC2. Similarly, the remaining even first gate pulse signals (such as GP1_4) are not chamfered.

According to the above, after receiving the chamfering control signal YV1C and the output enable signal YOE, the gate driving circuit 101 sequentially outputs the enabling signal YOE according to the output scanning signal (such as SC1 to SC5), and according to the chamfering control signal YV1C The odd-numbered parts of the scan signals (such as SC1 to SC5) (such as SC1, SC3, and SC5) are chamfered. Since the number of times of the chamfering process is reduced, the power consumption of the chamfering process can be saved and the noise generated during the circuit operation can be reduced, but the feedthrough effect of the pixels (not shown) of the display panel 120 can be reduced. .

In the above embodiment, the gate pulse modulation circuit 110 performs odd-numbered portions (such as GP1_1, GP1_3, and GP1_5) in the first gate pulse signal (such as GP1_1~GP1_5) according to the chamfer control signal YV1C. The chamfering process, that is, the odd-numbered parts of the scanning signals (such as SC1 to SC5) (such as SC1, SC3, and SC5) are chamfered, but in other embodiments, the gate pulse-modulating circuit 110 can be based on The chamfering control signal YV1C performs chamfering on even-numbered portions of the first gate pulse signal (such as GP1_1~GP1_5), such as even numbers in the scanning signals (such as SC1 to SC5). Parts (such as SC2 and SC4) are chamfered.

3 is a schematic diagram of the driving waveform of FIG. 1 according to another embodiment of the present invention. Referring to FIG. 1 to FIG. 3, in the present embodiment, FIG. 3 is different from FIG. 2 in that the chamfering control signal YV1C is enabled to be close to an even portion (such as GP1_2, GP1_4) corresponding to the first gate pulse signal. The portion of the falling edge is such that the second gate pulse signal (such as GP3_1~GP3_5) shown in Figure 3 is different from the second gate pulse signal (such as GP2_1~GP2_5) shown in Figure 2, and Figure 3 The scan signal (such as SC1~SC5) will be different from the scan signal shown in Figure 2 (such as SC1~SC5). That is, during one picture period, the gate pulse modulation circuit 110 of the embodiment performs chamfering on even parts (such as GP1_2, GP1_4) of the first gate pulse signal (such as GP1_1~GP1_5). deal with.

Further, in the time interval of t21 to t22, that is, corresponding to the first gate pulse wave signal GP1_1 (that is, one of the odd portions of the first gate pulse wave signal), the chamfering control signal YV1C is disabled. The gate pulse modulation circuit 110 does not chamfer the first gate pulse signal GP1_1, and the output enable signal YOE is at the enable level, so the gate driver 130 will The two-gate pulse wave signal GP3_1 is used as the scan signal SC1. Similarly, the remaining odd first gate pulse signals (such as GP1_3, GP1_5) are not chamfered.

On the other hand, in the time interval from t23 to t26, the chamfering control signal YV1C is at the enable level in the time interval from t24 to t26, so the gate pulse modulation circuit 110 will be the first gate pulse signal. GP1_2 performs chamfering processing, so that the corresponding second gate pulse wave signal GP3_2 generates a notch at a portion close to the falling edge, and the output enable signal YOE is an enable level in a time interval from t23 to t25, thus the gate The pole driver 130 outputs the second gate pulse signal GP3_2 as the scan signal SC2, and the chamfer processing of the remaining even first gate pulse signals (such as GP1_4) is similar to the second gate pulse signal GP1_2, where Let me repeat.

According to the above, in the embodiment, after receiving the chamfering control signal YV1C and the output enable signal YOE, the gate driving circuit 101 sequentially outputs the scanning signals (such as SC1 to SC5) according to the output enable signal YOE, and according to The chamfering control signal YV1C performs chamfering on the even-numbered portions of the scanning signals (such as SC1 to SC5) (such as SC2 and SC4).

In the above embodiment, the gate pulse modulation circuit 110 can perform chamfering processing on the odd portions of the plurality of first gate pulse signals (such as GP1_1~GP1_5) according to the chamfer control signal YV1C, or the gate The pulse wave modulation circuit 110 can perform chamfering processing on the even portions of the plurality of first gate pulse signals (eg, GP1_1~GP1_5) according to the chamfer control signal YV1C. In the embodiment of the present invention, the gate pulse wave modulation circuit 110 can perform chamfering processing on one of two adjacent first gate pulse signals (such as GP1_1~GP1_5) according to the chamfer control signal YV1C. That is, the gate driving circuit 101 can perform chamfering processing on one of two adjacent scanning signals (such as SC1 to SC5) according to the chamfering control signal YV1C. In other words, the ratio of the chamfering and the non-shaping of the first gate pulse wave signal by the gate pulse wave modulation circuit 110 (equivalent to the ratio of the chamfering and non-sharpening of the scanning signal by the gate driving circuit 101) may be It is 1:1, but the embodiment of the present invention is not limited thereto, that is, the above ratio may be 2:3 or 4:1, which may be adjusted according to the display effect of a person skilled in the art or the display panel 120.

Moreover, when the display panel 120 appears bright and dark, the occurrence of the bright and dark lines can be suppressed by the distribution of the chamfering and non-sharpening of the first gate pulse signal (equivalent to the scanning signal), that is, when the bright line occurs. When the voltage of the pixel electrode (not shown) is high, the first gate pulse signal corresponding to the bright line is not chamfered to reduce the voltage of the pixel electrode through the feedthrough effect. Since each scanning signal (such as SC1~SC5) is generally designed to correspond to a column of pixels, the horizontal bright line can be suppressed by the distribution of the chamfering and non-shaping of the first gate pulse signal, but through the special structure of the display panel ( For example, HSD) can make each scan signal (such as SC1~SC5) be an odd pixel or an even pixel in a corresponding column of pixels, so it can suppress the distribution of the chamfering and non-sharpening of the first gate pulse signal. Bright and dark lines of odd and even lines.

In addition, in some embodiments of the present invention, the odd portion of the first gate pulse signal (eg, GP1_1~GP1_5) may be chamfered during the first picture period, and the first portion is used during the second picture period. The even portion of the gate pulse signal (eg, GP1_1~GP1_5) is chamfered, wherein the first picture period is adjacent to the second picture period. That is, the above-described embodiment of FIG. 3 can be applied to the first picture to perform chamfering processing on the odd portion of the first gate pulse signal (eg, GP1_1~GP1_5), which is equivalent to the scanning signal (eg, SC1~SC5). The odd part of the) is chamfered. And applying the above-mentioned embodiment of FIG. 4 to the second picture to perform chamfering processing on the even portion of the first gate pulse signal (eg, GP1_1~GP1_5), which is equivalent to the scanning signal (eg, SC1~SC5) The even part is chamfered.

FIG. 4 is a schematic diagram showing the driving waveform of FIG. 1 according to still another embodiment of the present invention. Referring to FIG. 2 and FIG. 4, FIG. 4 is different from FIG. 2 in that the first gate signal VGH1 is a DC voltage. Moreover, during one picture period, the gate pulse wave modulation circuit 110 of the embodiment performs chamfering processing on the first gate signal VGH1 corresponding to the odd scanning signals (such as SC1, SC3, and SC5) (ie, pulling down the voltage level) Bit), so that the second gate signal VGH2 is generated.

Further, in the time interval from t31 to t34, the chamfering control signal YV1C is in the enablement level in the time interval from t32 to t34 (ie, the portion close to the falling edge of the scan signal SC1), and the second gate at this time The signal VGH2 will exhibit a voltage drop condition, and the output enable signal YOE is at the enable level in the time interval from t31 to t33, so the gate driver 130 outputs the second gate signal VGH2 in the time interval from t31 to t33. The waveform is formed to form a scan signal SC1 having a missing angle. On the other hand, in the time interval from t35 to t36, the chamfer control signal YV1C is at the disable level, so the voltage level of the second gate signal VGH2 is not pulled low, and the output enable signal YOE is at t35~ The time interval of t36 is at the enable level, and therefore the gate driver 130 outputs a waveform of the second gate signal VGH2 in the time interval from t31 to t33 to form the scan signal SC2. The generation of the remaining scan signals (such as SC3~SC5) can be understood by referring to the above description and the drawings, and will not be described herein.

FIG. 5 is a flow chart of a method for generating a scan signal of a display device according to an embodiment of the invention. Referring to FIG. 5, in the embodiment, the scan signal generating method of the display device includes the following steps. First, an output enable signal and a chamfer control signal are received (step S510). Next, a plurality of scan signals are output in accordance with the output enable signal (step S520). Furthermore, a portion of the first gate pulse signals is chamfered according to the chamfer control signal (step S530). The order of the above steps is for illustration, and the embodiment of the present invention is not limited thereto. For details of the scanning signal generating method of the display device according to the embodiment of the present invention, reference may be made to the description of the embodiment of FIG. 1 to FIG. 4, and details are not described herein again.

In summary, the display device and the scan signal generating method thereof according to the embodiments of the present invention, the gate driving circuit sequentially outputs a plurality of scanning signals according to the output enable signal and according to the chamfering control signal to the scanning signals. Part of the chamfering process. In this way, the feedthrough effect of the display panel can be improved, the power consumption of the driving display panel can be saved, and the noise generated when the display panel is driven can be reduced. Moreover, when a bright and dark line appears on the display panel, the occurrence of the bright and dark lines can be suppressed by the distribution of the chamfering and non-shaping of the first gate pulse wave signal (equivalent to the scanning signal).

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Display device

101. . . Gate drive circuit

110. . . Gate pulse wave modulation circuit

120. . . Display panel

130. . . Gate driver

140. . . Source driver

150. . . Controller

GP1_1~GP1_5. . . First gate pulse signal

GP2_1~GP2_5, GP3_1~GP3_5. . . Second gate pulse signal

T11~t16, t21~t26, t31~t36. . . Time point

SC1, SC2, SC3, SC4, SC5. . . Scanning signal

S510, S520, S530. . . step

VGH1. . . First gate signal

VGH2. . . Second gate signal

VP1~VP5. . . Data voltage

YV1C. . . Chamfer control signal

YOE. . . Output enable signal

1 is a schematic diagram of a display device in accordance with an embodiment of the present invention.

2 is a schematic diagram of the driving waveform of FIG. 1 according to an embodiment of the invention.

3 is a schematic diagram of the driving waveform of FIG. 1 according to another embodiment of the present invention.

4 is a schematic diagram of the driving waveform of FIG. 1 according to still another embodiment of the present invention.

FIG. 5 is a flow chart of a method for generating a scan signal of a display device according to an embodiment of the invention.

100. . . Display device

101. . . Gate drive circuit

110. . . Gate pulse wave modulation circuit

120. . . Display panel

130. . . Gate driver

140. . . Source driver

150. . . Controller

SC1, SC2, SC3, SC4, SC5. . . Scanning signal

VGH1. . . First gate signal

VGH2. . . Second gate signal

VP1~VP5. . . Data voltage

YV1IC. . . Chamfer control signal

YOE. . . Output enable signal

Claims (10)

A display device includes: a display panel; and a gate driving circuit coupled to the display panel, the gate driving circuit is configured to receive a chamfering control signal and an output enable signal, and according to the output enable signal A plurality of scan signals are sequentially outputted to the display panel, and portions of the scan signals are chamfered according to the chamfer control signal. The display device of claim 1, wherein the gate driving circuit comprises: a gate pulse wave modulation circuit for receiving a first gate signal and the chamfer control signal, the gate The pulse wave modulation circuit performs chamfering processing on the first gate signal according to the chamfering control signal, and outputs a second gate signal; and a gate driver electrically connected to the gate pulse wave modulation electric And the display panel is configured to receive the output enable signal, and the gate driver sequentially outputs the scan signals to the display panel according to the second gate signal and the output enable signal. The display device of claim 1, wherein the gate driving circuit performs a chamfering process on an odd portion of the scan signals. The display device of claim 1, wherein the gate driving circuit performs a chamfering process on an even portion of the scan signals. The display device of claim 1, wherein the gate driving circuit performs a chamfering process on one of the adjacent two scanning signals. The display device of claim 1, wherein the gate pulse modulation circuit performs a chamfering process on the odd portions of the scan signals during a first picture period, and during a second picture period. The even portion of the scan signals is chamfered, and the first picture period is adjacent to the second picture period. A scanning signal generating method for a display device includes: receiving a chamfering control signal and an output enabling signal; sequentially outputting a plurality of scanning signals to a display panel according to the output enabling signal; and controlling the signal pair according to the chamfering One of the adjacent two scan signals of the scan signals is chamfered. The scanning signal generating method of the display device according to claim 7, wherein the step of chamfering the portions of the scanning signals according to the chamfering control signal comprises: controlling the signal according to the chamfering control signal A gate signal is chamfered to output a second gate signal. The method for generating a scan signal of the display device according to claim 8, wherein the step of sequentially outputting the plurality of scan signals to the display panel according to the output enable signal comprises: according to the second gate signal and the output The enable signal sequentially outputs the scan signals to the display panel. The display device of claim 7, wherein the step of chamfering one of the adjacent ones of the scan signals according to the chamfer control signal comprises: during a first picture period And performing an off-angle processing on the odd-numbered portions of the scan signals; and performing a chamfering process on the even-numbered portions of the scan signals in a second picture period, wherein the first picture period is adjacent to the second picture period .