TWI756786B - Substrate structure and the manufacture thereof - Google Patents

Abstract

A substrate structure in which an encapsulating body made of material of solder mask is formed on a substrate body, and the encapsulating body has a hollow portion exposing a part of a circuit layer, wherein the edge of the hollow portion is formed with a stepped structure to avoid Copper migration.

Description

Substrate structure and method of making the same

The present invention relates to a substrate structure, in particular to a substrate structure for wiring with Bump On Lead type.

As the size of semiconductor products is shrinking, the requirements for line spacing in semiconductor packages are getting smaller and smaller. For this reason, the flip-chip package substrate adopts bump on lead/bump on trace (BOL for short) for wiring. design.

However, the pitch of the circuit designed by the BOL method is extremely small, so it is impossible to form a solder mask between the circuits for electrical isolation, so a window is usually opened on the whole layer of the solder mask. The process forms an opening that can expose a plurality of BOL lines at the same time.

As shown in FIG. 1A , a circuit layer 13 is formed on the outer surface 10a of the substrate body 10 of a conventional packaging substrate 1 using the BOL method, and the circuit layer 13 has a plurality of conductive traces 130 and a plurality of integrated conductive traces The electrical contact pads 131 at the ends of the lines 130 are provided with a solder resist layer 11 on the substrate body 10, so that the solder resist layer 11 has an opening 110 corresponding to all the electrical contact pads 131, so that the electrical contact The upper surface and the side surface of the pad 131 are completely exposed to the opening 110 .

In the conventional package substrate 1, the window opening process is completed by exposure and development, and in order to increase the structural strength and prevent the circuit layer 13 from being exposed to the risk of short circuit, the thickness h of the solder mask layer 11 is designed to be much larger than the The thickness t of the circuit layer 13 (the gap e shown in FIG. 1C ), so in order to ensure the accuracy of the target area of the exposed surface 13 a (copper material) of the circuit layer 13 (as shown in FIG. 1C ), the exposure and development work The light energy F in the circuit layer 13 will be based on the exposed surface 13 a of the circuit layer 13 , that is, the light energy F will only act on the exposed surface 13 a of the circuit layer 13 , so the light energy F is not easy to act on the solder mask layer 11 . The bottom (ie, the outer surface 10a of the substrate body 10 ), so that after the development operation, the bottom of the wall surface of the opening 110 of the solder mask 11 is easily corroded by the developer solution due to insufficient illumination, thereby forming an undercut structure V (as shown in Figure 1B).

However, in the conventional package substrate 1, the undercut structure V will have residual developer solution, so based on the requirement of fine line spacing, the spacing between the conductive traces 130 is getting smaller and smaller, resulting in the conductive traces The copper material of the line 130 will migrate along the remaining developer solution of the undercut structure V, that is, the phenomenon of copper migration, so that the irregular conductors 9 will be formed at the undercut structure V, so that the package substrate 1 is formed. If the reliability is not good, the conductor 9 may be connected to the two adjacent conductive traces 130 to cause an electrical short circuit.

Furthermore, although increasing the light energy F can prevent the undercut structure V from being formed at the bottom of the solder mask layer 11, if the light energy F is too large, the solder mask material on the circuit layer 13 will be overexposed (overexposed). ), resulting in that it is difficult to remove the solder resist on the circuit layer 13 after the developing operation, resulting in that the area of the exposed surface 13a of the circuit layer 13 is too small. Therefore, in the subsequent packaging process, other electronic components cannot be effectively connected, and even the occurrence of The problem of poor electrical transmission.

Therefore, how to overcome the various deficiencies of the above-mentioned conventional technologies has become an urgent problem to be solved at present.

In order to solve the above-mentioned problems of the prior art, the present invention proposes a substrate structure, which includes: a substrate body, which has a joint surface; a circuit layer, which is formed on the joint surface; and a cladding body, which is formed on the joint. The surface covers the circuit layer and has a hollow part exposing part of the circuit layer, wherein the edge of the hollow part is formed with a stepped structure, and the hollow part is not filled with conductive materials.

The present invention also provides a manufacturing method of a substrate structure, which includes: providing a substrate body with a bonding surface, and forming a circuit layer on the bonding surface; and forming a cladding body on the bonding surface, so that the cladding is The body covers the circuit layer, and the coating system has a hollow part exposing part of the circuit layer, wherein the edge of the hollow part is formed with a stepped structure.

In the aforementioned substrate structure and its manufacturing method, no undercut structure is formed at the bottom of the hollow portion.

In the aforementioned substrate structure and its manufacturing method, the circuit layer has a plurality of conductive traces separated from each other, so that a part of the surface of the plurality of conductive traces is exposed to the hollow portion. For example, the cladding body is not formed between the line segments of the plurality of conductive traces exposed to the hollow portion.

In the above-mentioned substrate structure and its manufacturing method, the manufacturing process of the cladding body is to stack a plurality of insulating protection layers on the bonding surface. For example, the bottommost insulating protective layer of the cladding body covers the circuit layer, and the bottommost insulating protective layer of the cladding body is formed by exposure and developing, and the exposure energy is applied to the bonding surface, so that the The plurality of insulating protective layers respectively form openings to serve as the hollow portions. Further, the widths of at least two of the plurality of openings are inconsistent, so that the edge of the hollow portion forms the stepped structure. Or, the wall surface of at least one of the plurality of openings is a flat surface; or, the wall surface of the opening of the insulating protective layer of the bottommost layer of the cladding body can be a vertical surface or a sloped surface with a narrow upper and a lower width relative to the joint surface .

In the aforementioned substrate structure and its manufacturing method, the coating system solder resist material.

As can be seen from the above, the substrate structure and the manufacturing method of the present invention are mainly designed to avoid the occurrence of the cladding by the design that the edge of the hollow portion of the cladding body has a stepped structure, and the circuit layers and/or conductive elements do not fill the hollow portion. The bottom of the cladding body forms an undercut structure, so compared with the prior art, the substrate structure of the present invention can effectively avoid the phenomenon of copper migration, and prevent short-circuit between adjacent conductive traces, which is beneficial to The reliability of the substrate structure of the present invention is improved.

Furthermore, in the manufacturing method of the present invention, if the cladding body includes a plurality of insulating protective layers stacked on each other, the thickness of the bottom insulating protective layer only needs to be slightly higher than that of the circuit layer, so the light energy does not need to be set too high. Therefore, compared with the prior art, even if the light energy is set to the strength so that the bottom of the insulating protective layer of the bottom layer will not form an undercut structure (for example, the energy directly hits the bonding surface), the bottom layer of the The material of the insulating protective layer at the hollow portion will not be overexposed, so that the required metal area of the circuit layer can still be effectively exposed.

1: Package substrate

10: Substrate body

10a: External surface

11: Solder mask

110: Opening

13,23: Circuit layer

13a: Exposed Surfaces

130,230: Conductive traces

131,231: Electrical Contact Pads

2: Substrate structure

2a: Coating

20: Substrate body

20a: Joint surface

200: Dielectric layer

201: wiring layer

21: The first insulating protective layer

210: First Opening

210a: First Wall

211: Steps

22: Second insulating protective layer

220: Second Opening

220a: Second Wall

230a: Line segment

24: Conductive elements

9: Conductor

D1, D2: width

E,e: gap

F, F1, F2: Light energy

h,t: thickness

T: stepped structure

V: Undercut structure

W: hollow part

FIG. 1A is a partial top plan view of a conventional package substrate.

FIG. 1B is a cross-sectional view taken along section line B-B of FIG. 1A .

FIG. 1C is a cross-sectional view taken along section line C-C of FIG. 1A .

FIG. 2 is a partial top plan schematic view of the substrate structure of the present invention.

Fig. 2' is a cross-sectional view taken along section line L'-L' of Fig. 2 .

FIG. 2" is a cross-sectional view of the section line L"-L" of FIG. 2. FIG.

2A to 2C are schematic partial cross-sectional views of different aspects of the cladding body of FIG. 2'.

3A to 3E are schematic cross-sectional views along the section line L1-L1 of FIG. 2 according to the first embodiment of the manufacturing method of the substrate structure of the present invention.

3A' to 3E' are schematic cross-sectional views along the section line L2-L2 of FIG. 2 according to the first embodiment of the manufacturing method of the substrate structure of the present invention.

The following specific embodiments are used to illustrate the implementation of the present invention, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this specification are only used to cooperate with the contents disclosed in the specification for the understanding and reading of those who are familiar with the art, and are not intended to limit the implementation of the present invention. Therefore, it has no technical significance, and any modification of the structure, change of the proportional relationship or adjustment of the size should still fall within the scope of the The technical content disclosed by the invention can be covered within the scope. At the same time, the terms such as "above", "first", "second" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the present invention. Changes or adjustments to their relative relationships, provided that there is no substantial change in the technical content, shall be regarded as the scope of the present invention.

FIG. 2 is a partial top plan view of the substrate structure 2 of the present invention. As shown in FIG. 2 , the substrate structure 2 includes a substrate body 20 , a circuit layer 23 , and a covering body 2 a having a hollow portion W. As shown in FIG. In this embodiment, the cladding body 2a includes a first insulating protection layer 21 and a second insulating protection layer 22 which are stacked on each other.

The outer surface of the substrate body 20 is defined as the bonding surface 20a, so that electronic components such as chips, package substrates or packaging modules can be connected to the bonding surface 20a of the substrate body 20 .

In this embodiment, the substrate body 20 is a circuit structure with a core layer or a coreless layer, such as a package substrate, which includes at least a dielectric layer 200 and a device. The wiring layer 201 on the dielectric layer 200 is shown in FIG. 2 ′ and FIG. 2 ″. For example, the wiring layer 201 is formed by a redistribution layer (RDL) method, and its material is copper, The material for forming the dielectric layer 200 is a dielectric material such as Polybenzoxazole (PBO), Polyimide (PI), Prepreg (PP) and the like. It should be understood that the substrate body 20 can also be other bearing units for connecting electronic components, such as a metal plate of a lead frame, or a wafer, chip, silicon interposer, silicon material, glass, etc. The semiconductor sheet is not limited to the above.

The wiring layer 23 is formed on the bonding surface 20a of the substrate body 20 and is electrically connected to the wiring layer 201 of the substrate body 20, as shown in FIG. 2".

In this embodiment, the circuit layer 23 includes a plurality of conductive traces 230 and electrical contact pads 231 integrally combined with the conductive traces 230, and the conductive traces 230 are separated from each other without short-circuiting, The electrical contact pads 231 are used for bonding conductive elements 24 such as solder materials (as shown in FIG. 2 ”), so that the substrate structure 2 is connected to a chip, a package substrate or a package module through the conductive elements 24 and other electronic components.

The first insulating protection layer 21 is formed on the bonding surface 20a of the substrate body 20 and has at least one first opening 210, as shown in FIG. 2 and FIG. The surface 20a, the partial line segments 230a of the conductive traces 230 and the electrical contact pad 231 are exposed to the first opening 210, as shown in FIG. 2 and FIG. 2", so that the first insulating protective layer 21 only covers part The circuit layer 23 and a part of the bonding surface 20a.

In this embodiment, the first insulating protective layer 21 is a photosensitive solder mask, the outline of the first opening 210 is roughly rectangular, groove-like or other suitable shapes, and the first wall of the first opening 210 The 210a series is flat. For example, the first wall surface 210a is a vertical surface (as shown in FIG. 2A ) or an inclined surface (as shown in FIG. 2 ′, the thickness of the first wall surface 210a is narrow at the top and wide at the bottom or the appearance is slope-like) relative to the joint surface 20a , and the first wall surface 210a is a vertical surface (as shown in FIG. 2A ) or an inclined surface (as shown in FIG. An insulating protective layer 21 is formed between the first wall surface 210a of the first opening 210 and the joint surface 20a There is no undercut structure formed therebetween. Specifically, the electrical contact pad 231 is not in contact with the first insulating protection layer 21 , and some line segments 230 a of the conductive traces 230 protrude out of the first wall surface 210 a of the first opening 210 , so that the Part of the line segment 230 a of the conductive trace 230 and the electrical contact pad 231 are exposed from the first opening 210 .

The second insulating protection layer 22 is formed on a part of the surface of the first insulating protection layer 21 and has at least one second opening 220 exposing the first opening 210, as shown in FIG. 2 and FIG. 2', So that part of the bonding surface 20a of the substrate body 20, part of the line segments 230a of the conductive traces 230 and the electrical contact pad 231 are exposed to the second opening 220, as shown in FIG. 2 and FIG. The two insulating protection layers 22 only cover part of the upper part of the circuit layer 23 , wherein the first opening 210 and the second opening 220 are used as the hollow part W, and the circuit layer 23 and/or the conductive element 24 do not fill the hollow part Part W. It should be understood that the arrangement range of the second insulating protection layer 22 is almost equal to (slightly smaller than) the arrangement range of the first insulating protection layer 21 .

In this embodiment, the second insulating protective layer 22 is a photosensitive solder mask, and the outline of the second opening 220 is rectangular, groove-like or other appropriate shapes roughly corresponding to the outline of the first opening 210 , and The second wall surface 220a of the second opening 220 is a flat surface. For example, the second wall surface 220a is a vertical surface (as shown in FIG. 2B ) or an inclined surface relative to the joint surface 20a (as shown in FIG. The second wall surface 220a shown in 2C is a slope with a wide upper and a narrow lower surface or a cliff-like or cliff-like appearance), and the second insulating protection layer 22 is on the second wall 220a of the second opening 220 and the first wall 220a. A stepped structure T is formed between the first walls 210a of the first opening 210 of the insulating protection layer 21 . Specifically, the first wall surface 210a of the first opening 210 of the first insulating protective layer 21 protrudes into the second opening 220, so that the protruding portion of the first insulating protective layer 21 serves as the step portion 211, so as to The stepped structure T is formed. It should be understood that the circuit layer 23 does not contact the second insulating protection layer 22 .

Therefore, the cladding body 2 a is not formed between the line segments 230 a of the conductive traces 230 exposed to the hollow portion W, and the cladding body 2 a is also not formed between the electrical contact pads 231 .

Furthermore, there are many kinds of materials for the solder resist layer, and even many kinds of photosensitive materials, so the material of the first insulating protective layer 21 and the material of the second insulating protective layer 22 may be the same or different.

FIGS. 3A to 3E and FIGS. 3A′ to 3E′ are schematic cross-sectional views of the manufacturing method of the first embodiment of the substrate structure 2 of the present invention, wherein FIGS. The process state, and FIGS. 3A' to 3E' show the process state of the section line L2-L2 of FIG. 2 .

In this embodiment, the process states shown in FIGS. 3A to 3E and the process states shown in FIGS. 3A' to 3E' correspond to steps at the same time point.

As shown in FIG. 3A and FIG. 3A', and referring to FIG. 2, a substrate body 20 is provided, and a circuit layer 23 is formed on the bonding surface 20a.

As shown in FIG. 3B and FIG. 3B', a first insulating protection layer 21 is formed on all the bonding surfaces 20a of the substrate body 20. As shown in FIG.

As shown in FIG. 3C and FIG. 3C ′, at least one first opening 210 is formed on the first insulating protective layer 21 by exposure and development, so that part of the bonding surface 20 a of the substrate body 20 and part of the conductive trace 230 are formed. The line segment 230 a and the electrical contact pad 231 are exposed from the first opening 210 .

In this embodiment, during exposure and development, the light energy F1 takes the bonding surface 20a of the substrate body 20 as a reference, so that the light energy F1 acts on the bonding surface 20a of the substrate body 20, so the first insulating protective layer The bottom side of 21 can fully absorb the light energy F1, so after the developing operation, the bottom of the first wall surface 210a of the first opening 210 can avoid being corroded by the developing solution due to sufficient light. Therefore, the first wall surface 210a of the first opening 210 presents a flat surface, and the bottom of the first wall surface 210a of the first opening 210 does not form an undercut structure.

As shown in FIG. 3D and FIG. 3D', a second insulating protection layer 22 is formed on the entire surface of the first insulating protection layer 21 and a part of the bonding surface 20a of the substrate body 20, and the second insulating protection layer 22 is formed. The layer 22 fills the first opening 210 to cover the segments 230 a of the conductive traces 230 and the electrical contact pad 231 .

As shown in FIG. 3E and FIG. 3E ′, at least one second opening 220 exposing the first opening 210 is formed on the second insulating protective layer 22 by exposure and development, so that part of the bonding surface 20 a of the substrate body 20 is formed. , and part of the line segments 230 a of the conductive traces 230 and the electrical contact pad 231 are exposed to the second opening 220 .

In this embodiment, the width D2 of the second opening 220 of the second insulating protection layer 22 is larger than the width D1 of the first opening 210 of the first insulating protection layer 21, so as to facilitate the formation of the stepped structure T (as shown in FIG. 2 ). ' shown).

Furthermore, during the exposure and development operation, the light energy F2 can be adjusted according to requirements to form a desired shape of the second wall surface 220 a of the second opening 220 . For example, when the light energy F2 is relatively large, the second wall surface 220a can be formed as shown in FIG. 2A with a sloped surface narrow at the top and wide at the bottom; when the light energy F2 is normal, a vertical second wall surface 220a as shown in FIG. 2B can be formed. Two wall surfaces 220a; when the light energy F2 is small, a second wall surface 220a with a sloped surface wide in the upper part and narrow in the lower part as shown in FIG. 2C can be formed, and an undercut structure may be formed. It should be understood that since the second insulating protection layer 22 does not contact the circuit layer 23 , even if the second insulating protection layer 22 forms an undercut structure, the phenomenon of copper migration will not be caused.

In the subsequent process, a plurality of conductive elements 24 can be formed on the electrical contact pads 231 (as shown in FIG. 2 ”), so that the substrate structure 2 can be connected to a chip, a package substrate or a package through the conductive elements 24 Electronic components such as modules.

The manufacturing method of the substrate structure 2 of the present invention is based on the fabrication of the first insulating protective layer 21 and the second insulating protective layer 22, so that the thickness of the first insulating protective layer 21 only needs to cover the wiring 23 (that is, the first insulating protective layer The difference E between the thickness of an insulating protective layer 21 and the thickness of the circuit layer 23 is extremely small, as shown in FIG. 3B and FIG. 3B ′), so the thickness of the first insulating protective layer 21 is extremely thin, so compared with the prior art , the illumination energy F1 of the present invention can directly act on the bonding surface 20a of the substrate body 20 (or the illumination energy F1 can be set Therefore, the bottom of the first insulating protection layer 21 will not form an undercut structure), so that the phenomenon of copper migration (Cu migration) can be effectively avoided, so as to improve reliability.

Furthermore, in the manufacturing method of the present invention, since the thickness of the first insulating protective layer 21 is extremely thin, the illumination energy F1 does not need to be set too large. The bottom of the first insulating protective layer 21 will not form the strength of the undercut structure, and the material of the first insulating protective layer 21 at the hollow portion W will not be overexposed, thus ensuring that the circuit layer 23 is effectively exposed. Metal area (ie, part of the segments 230a of the conductive traces 230 and the electrical contact pads 231) is required.

To sum up, in the substrate structure and the manufacturing method of the present invention, the edge of the hollow portion of the cladding body is designed with a stepped structure, and the circuit layer and/or the conductive element does not fill the hollow portion, so as to The bottom of the cladding body is prevented from forming an undercut structure, so the substrate structure of the present invention can effectively avoid the phenomenon of copper migration, and prevent short-circuit between adjacent conductive traces, which is beneficial to improve the substrate of the present invention The reliability of the structure.

The above embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the right of the present invention should be listed in the scope of the patent application described later.

2: Substrate structure

2a: Coating

20: Substrate body

20a: Joint surface

200: Dielectric layer

201: wiring layer

21: The first insulating protective layer

210a: First Wall

211: Steps

22: Second insulating protective layer

220a: Second Wall

T: stepped structure

Claims (23)

A substrate structure, comprising: a substrate body, which has a bonding surface; a circuit layer, which is formed on the bonding surface; and a cladding body, which is formed on the bonding surface and covers the circuit layer, and has an exposed portion The hollow portion of the circuit layer, wherein the edge of the hollow portion is formed with a stepped structure, and the hollow portion is not filled with conductive materials. The substrate structure according to claim 1, wherein no undercut structure is formed at the bottom of the hollow portion. The substrate structure of claim 1, wherein the circuit layer has a plurality of conductive traces separated from each other, so that a part of the surface of the plurality of conductive traces is exposed to the hollow portion. The substrate structure of claim 3, wherein the cladding body is not formed between the line segments of the plurality of conductive traces exposed to the hollow portion. The substrate structure of claim 1, wherein the cladding system comprises a plurality of insulating protective layers stacked on each other. The substrate structure of claim 5, wherein the bottommost insulating protective layer of the cladding body covers the circuit layer. The substrate structure of claim 5, wherein the plurality of insulating protection layers respectively form openings to serve as the hollow portions. The substrate structure of claim 7, wherein the widths of at least two of the plurality of openings are inconsistent, so that the edge of the hollow portion forms the stepped structure. The substrate structure of claim 7, wherein the wall surface of at least one of the plurality of openings is a flat surface. The substrate structure according to claim 7, wherein the wall surface of the opening of the insulating protection layer of the bottommost layer of the cladding body is a vertical surface or a sloped surface with a narrow upper and a lower width relative to the joint surface. The substrate structure according to claim 1, wherein the cladding system solder resist. A method for manufacturing a substrate structure, comprising: providing a substrate body with a bonding surface, and forming a circuit layer on the bonding surface; and forming a covering body on the bonding surface, so that the covering body covers the bonding surface A circuit layer, and the cladding system has a hollow part exposing part of the circuit layer, wherein the edge of the hollow part is formed with a stepped structure, and the hollow part is not filled with conductive materials. The manufacturing method of the substrate structure according to claim 12, wherein no undercut structure is formed at the bottom of the hollow portion. The manufacturing method of the substrate structure according to claim 12, wherein the circuit layer has a plurality of conductive traces separated from each other, so that a part of the surface of the plurality of conductive traces is exposed to the hollow portion. The manufacturing method of the substrate structure according to claim 14, wherein the cladding body is not formed between the line segments of the plurality of conductive traces exposed to the hollow portion. The manufacturing method of the substrate structure as claimed in claim 12, wherein the manufacturing process of the cladding body is to stack a plurality of insulating protective layers on the bonding surface. The manufacturing method of the substrate structure according to claim 16, wherein the bottommost insulating protective layer of the cladding body covers the circuit layer. The manufacturing method of the substrate structure according to claim 17 further comprises forming the bottommost insulating protective layer of the cladding body by exposure and development, and the exposure energy is applied to the bonding surface. The manufacturing method of the substrate structure according to claim 16, wherein the plurality of insulating protection layers respectively form openings to serve as the hollow portions. The manufacturing method of the substrate structure according to claim 19, wherein the widths of at least two of the plurality of openings are inconsistent, so that the edge of the hollow portion forms the stepped structure. The manufacturing method of the substrate structure according to claim 19, wherein the wall surface of at least one of the plurality of openings is a flat surface. The manufacturing method of the substrate structure according to claim 19, wherein the wall surface of the opening of the insulating protective layer of the bottommost layer of the cladding body is a vertical surface or a sloped surface with a narrow upper and a lower width relative to the joint surface. The manufacturing method of the substrate structure according to claim 12, wherein the coating system solder resist.

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