TWI749845B - Conductive lines of integrated circuit and method for fabticating the same - Google Patents

Abstract

A method for fabricating conductive lines of an integrated circuit includes: providing a substrate and a first dielectric layer on the substrate; forming a first etch mask on the first dielectric layer; using the first etch mask to etch the first dielectric layer, such that a trench is formed therein; forming a first conductive structure and a conductive layer on the first conductive structure and the first dielectric layer; forming a second etch mask aligned with the first conductive structure on the conductive layer; and using the second etch mask to etch the conductive layer, such that a second conductive structure is formed and in contact with the first conducive structure.

Description

Integrated circuit wire structure and manufacturing method thereof

The present invention relates to the technical field of semiconductors, in particular to an integrated circuit wire structure and a manufacturing method thereof.

With the development of semiconductor technology, the requirements for the volume and area of integrated circuits have become more stringent. Among them, in order to achieve more efficient operation speed and achieve lower energy consumption, the size of the semiconductor structure has become the key.

However, there are often technical limitations in forming the conductive structure of the semiconductor. For example, the height of the photoresist is too high to easily collapse, and it is difficult to form a conductive structure of a specific size or shape.

Therefore, how to overcome technical difficulties and form a conductive structure of a specific size is a problem that the industry urgently wants to invest in research and development resources to solve.

In view of this, one purpose of the present invention is to provide an integrated circuit Manufacturing method of wire structure.

In one or more embodiments of the present invention, the manufacturing method of the integrated circuit wire structure includes providing a substrate and a first dielectric layer on the substrate; forming a first etching mask on the first dielectric layer; An etching mask etches the first dielectric layer to form a trench; forms a first conductive structure in the trench, and forms a conductive layer on the first conductive structure and the first dielectric layer; forms an alignment on the conductive layer A second etching mask of the first conductive structure; and etching the conductive layer through the second etching mask to form a second conductive structure contacting the first conductive structure.

In some embodiments of the present invention, the manufacturing method further includes: forming a first etch stop layer between the substrate and the first dielectric layer.

In some embodiments of the present invention, the first dielectric layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is located on the first dielectric layer.

In some embodiments of the present invention, the manufacturing method further includes: forming a second etch stop layer between the first dielectric layer and the second dielectric layer.

In some embodiments of the present invention, forming the trench includes: forming a second sub-trench in the second dielectric layer; and forming a first sub-trench in the first dielectric layer to communicate with the second sub-trench to form a trench .

In some embodiments of the present invention, the width of the first sub-trench is smaller than the width of the second sub-trench.

In some embodiments of the present invention, the first conductive structure includes a first conductive substructure and a second conductive substructure, and the second conductive substructure is On the first conductive substructure, and the width of the second conductive substructure is greater than the width of the first conductive substructure.

Another object of the present invention is to provide a wire structure for an integrated circuit.

In some embodiments of the present invention, an integrated circuit wire structure includes a substrate, a first dielectric layer, a second dielectric layer, a first conductive structure, and a second conductive structure. The first dielectric layer is located on the substrate. The first conductive structure is located in the first dielectric layer. The second dielectric layer is located on the first dielectric layer, and the second conductive structure is located in the second dielectric layer. The first conductive structure includes a first conductive substructure and a second conductive substructure. The second conductive substructure is located on the first conductive substructure, and the second conductive structure contacts the second conductive substructure of the first conductive structure.

In some embodiments of the present invention, the width of the second conductive substructure is greater than the width of the first conductive substructure.

In some embodiments of the present invention, the first conductive structure has a first upper bottom and a first lower bottom, the width of the first upper bottom is greater than that of the first lower bottom, and the second conductive structure has a second upper bottom and a first lower bottom. The width of the second bottom bottom is smaller than the width of the second bottom bottom, and the first top bottom is in contact with the second bottom bottom.

In summary, the integrated circuit wire structure of the present invention has the first conductive structure and the second conductive structure that are connected, so an integrated circuit wire structure with a high aspect ratio can be formed. Furthermore, the first integrated circuit wire structure of the present invention has a first conductive substructure and a second conductive substructure that contact up and down, wherein the width of the second conductive substructure is greater than that of the first conductive substructure. The width of the substructure can be used to improve the wire interconnection structure in the current semiconductor field.

100: Manufacturing method

110, 120, 130, 140, 150, 160: steps

200: Integrated circuit wire structure

210: substrate

221: first etch stop layer

223: second etch stop layer

231: first dielectric layer

231a: first dielectric layer

231b: second dielectric layer

232: groove

232a: first sub groove

232b: second sub groove

233: second dielectric layer

251: The first etching mask

251a, 253a: opening

253: Second etching mask

271: The first conductive structure

271a: first conductive substructure

271b: second conductive substructure

271c: first upper top

271d: the first bottom

272: Conductive layer

273: second conductive structure

273a: second upper top

273b: second bottom bottom

In order to describe the above or other advantages and features of the present invention, the principle described above will be explained in more detail by referring to its specific embodiments, and the specific embodiments are shown in the accompanying drawings. These drawings only exemplarily describe the invention and therefore are not to be considered as limiting the scope. Through the accompanying drawings, the principle of the present invention will be clearly explained, and additional features and details will be fully described. Among them: Figure 1 is a flowchart of a manufacturing method of an integrated circuit wire structure according to some embodiments of the present invention; and Figures 2 to 7 can be represented as schematic cross-sectional views of each step of the manufacturing method in Figure 1.

The invention can be implemented in many different forms. Representative embodiments are shown in the drawings and will be described in detail herein. The present disclosure contains examples or descriptions of principles, and aspects of the present disclosure shall not be limited to the illustrated embodiments.

Please refer to Figure 1. FIG. 1 is a flowchart of a manufacturing method 100 of an integrated circuit wire structure according to some embodiments of the present invention. The manufacturing method 100 starts at step 110, where step 110 includes providing a substrate and a first dielectric layer on the substrate. Then the manufacturing method 100 proceeds to Step 120. Step 120 includes forming a first etching mask on the first dielectric layer. The manufacturing method 100 then proceeds to step 130, which includes etching the first dielectric layer through the first etching mask to form a trench. Then the manufacturing method 100 proceeds to step 140, which includes forming a first conductive structure in the trench, and forming a conductive layer on the first conductive structure and the first dielectric layer. Then, the manufacturing method 100 proceeds to step 150, which includes forming a second etching mask aligned with the first conductive structure on the conductive layer. Finally, the manufacturing method 100 proceeds to step 160, which includes etching the conductive layer through the second etching mask to form a second conductive structure contacting the first conductive structure.

FIGS. 2 to 7 may be shown as schematic cross-sectional views of various steps of the manufacturing method 100 in FIG. 1. FIG. Please refer to FIG. 2. FIG. 2 can be used to represent step 110 and step 120 in which the first dielectric layer 231 is located on the substrate 210. Wherein, the substrate 210 may include a doped or undoped semiconductor material (such as silicon), or an active layer of a semiconductor-on-insulator (SOI) substrate. The substrate 210 may also include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors, including SiGe , GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; or a combination thereof. The first dielectric layer 231 is an interlayer dielectric (ILD) and may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), Fluorine-doped silicate glass (FSG) or tetraethyl orthosilicate (TEOS), etc. Can use spin coating, flowable chemistry Vapor deposition (FCVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc. form the first dielectric layer 231, and the present invention is not limited thereto.

In some embodiments of the present invention, the manufacturing method 100 further includes forming a first etch stop layer 221 between the substrate 210 and the first dielectric layer 231. The first etch stop layer 221 may be made of silicon carbide, silicon nitride, and oxygen. Silicon nitride, silicon carbonitride, etc. are formed, and can be formed using a suitable deposition process (such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination thereof), The present invention is not limited to this.

In some embodiments of the present invention, the first dielectric layer 231 includes a first dielectric layer 231a and a second dielectric layer 231b, and the second dielectric layer 231b is located on the first dielectric layer 231a. In addition, the manufacturing method 100 may further include forming a second etch stop layer 223 between the first dielectric layer 231a and the second dielectric layer 231b, wherein the first etch stop layer 221 and the second etch stop layer 223 are substantially the same. This will not be repeated here. In addition, the first dielectric layer 231a and the second dielectric layer 231b can be made of the same material, but can also be made of different materials, and the present invention is not limited to this.

In step 120, a first etching mask 251 is formed on the first dielectric layer 231. The first etching mask 251 may be a patterned hard mask or a patterned photoresist, wherein the first etching mask 251 has an opening 251 a to at least partially expose the first dielectric layer 231.

Please refer to Figures 3 and 4. Figures 3 and 4 can be used to represent step 130, in which the first dielectric layer 231 is etched through the first etching mask 251 (as shown in Figure 2) to form trenches 232 . The portion of the opening 251a (as shown in FIG. 2) that exposes the first dielectric layer 231 is removed, and the portion of the first etching mask 251 that covers the first dielectric layer 231 is retained. That is, the first etching mask 251 can define the size and shape of the trench 232.

In FIG. 3, the second sub-trench 232b of the trench 232 is formed in the second dielectric layer 231b. Next, in FIG. 4, the first sub-trench 232a of the trench 232 is formed in the first dielectric layer 231a, wherein the first sub-trench 232a communicates with the second sub-trench 232b to jointly form the trench 232. In addition, the width of the first sub-groove 232a is smaller than the width of the second sub-groove 232b. In addition, the first sub-trench 232a may be formed first and then the second sub-trench 232b is formed, and the present invention is not limited thereto.

Specifically, the second sub-trench 232b can be formed in the second dielectric layer 231b by anisotropic etching through the first etching mask 251, and the first etching mask 251 can be removed. Next, any suitable method such as photolithography and anisotropic etching is used to form the first sub-trench 232a in the first dielectric layer 231. Among them, the anisotropic etching may be, for example, dry etching, such as plasma etch or reactive ion etch (RIE), and the present invention is not limited thereto.

Please refer to Figure 5. Figure 5 can be used to show step 140 and Step 150. In step 140, the first conductive structure 271 is formed in the trench 232 (as shown in FIG. 4), and a conductive layer 272 is formed on the first conductive structure 271 and the first dielectric layer 231, wherein the first conductive structure 271 and The conductive layer 272 may be integrally formed. In step 150, a second etching mask 253 is formed on the conductive layer 272, wherein the second etching mask 253 is aligned with the first conductive structure 271, for example, the second etching mask 253 shields the first conductive structure 271 from above. The second etching mask 253 can be a patterned hard mask or a patterned photoresist, and has an opening 253a, but the present invention is not limited to this. Specifically, the first conductive structure 271 and the conductive layer 272 can be formed by chemical vapor deposition, physical vapor deposition, plating (for example, electroplating or electroless plating) or other suitable methods, and the present invention is not based on this. limit.

In some embodiments of the present invention, the first conductive structure 271 includes a first conductive substructure 271a and a second conductive substructure 271b, the second conductive substructure 271b is located on the first conductive substructure 271a, and the second conductive substructure 271a The width of 271b is greater than the width of the first conductive substructure 271a. The first conductive structure 271 is made of a conductive material, and the conductive material can be tungsten, aluminum, copper, titanium, tantalum, titanium nitride or alloys thereof. In some embodiments of the present invention, the first conductive substructure 271a and the second conductive substructure 271b are made of the same conductive material, but the first conductive substructure 271a and the second conductive substructure 271b can also be made of the same conductive material. It is composed of different conductive materials, and the present invention is not limited to this.

Please refer to Figure 6, Figure 6 can be used to represent step 160, Step 160 includes etching the conductive layer 272 (as shown in Fig. 5) through the second etching mask 253 (as shown in Fig. 5) and its openings 253a (as shown in Fig. 5) to form a second conductive structure contacting the first conductive structure 271 273, wherein the second conductive structure 273 contacts the second conductive substructure 271b from above. Specifically, the second etching mask 253 can be used in conjunction with an anisotropic etching process to form the second conductive structure 273, and the second etching mask 253 and its opening 253a can define the size and shape of the second conductive structure 273. In addition, the second conductive structure 273 is made of conductive material. The first conductive structure 271 and the second conductive structure 273 are made of the same conductive material, but the first conductive structure 271 and the second conductive structure are made of the same conductive material. 273 (for example, the second conductive substructure 271b) can also be made of different conductive materials, but the present invention is not limited thereto.

Please refer to FIG. 7, after step 160 is completed, a second dielectric layer 233 may be formed on the first dielectric layer 231, wherein the second dielectric layer 233 surrounds the second conductive structure 273. The first dielectric layer 231 and the second dielectric layer 233 can be made of the same material, but the first dielectric layer 231 and the second dielectric layer 233 can also be made of different dielectric materials. The present invention is not limited to this.

Please refer to FIG. 7. FIG. 7 shows a semiconductor integrated circuit wire structure 200 including a substrate 210, a first dielectric layer 231, a second dielectric layer 233, a first conductive structure 271, and a second conductive structure 273. The first dielectric layer 231 is located on the substrate 210. The second dielectric layer 233 is located on the first dielectric layer 231, the first conductive structure 271 is located in the first dielectric layer 231, and the second conductive structure 273 is located on the second dielectric layer 231. In the layer 233, the second conductive structure 273 contacts the first conductive structure 271 to form a conductive circuit structure with a high aspect ratio (for example, the aspect ratio is greater than 10), and the width of the second conductive structure 273 is the same as the second conductive substructure 271b The width is about the same. Since the various components of the integrated circuit wire structure 200 and their manufacturing methods have been described in detail in the previous paragraphs, they will not be repeated here.

In some embodiments of the present invention, the first conductive structure 271 includes a first conductive substructure 271a and a second conductive substructure 271b, the second conductive substructure 271b is located on the first conductive substructure 271a, and the second conductive substructure 271a 273 contacts the second conductive substructure 271b of the first conductive structure 271. In addition, the width of the second conductive substructure 271b is greater than the width of the first conductive substructure 271a. In some embodiments, the first conductive substructure 271a may be a via, but the invention is not limited thereto.

Specifically, the first conductive structure 271 has a first top top 271c and a first bottom bottom 271d, and the width of the first top top 271c is greater than the width of the first bottom bottom 271d. The second conductive structure 273 has a second upper top 273a and a second lower bottom 273b, and the width of the second upper top 273a is smaller than the width of the second lower bottom 273b. In addition, the first upper top portion 271c of the first conductive structure 271 contacts the second lower bottom portion 273b of the second conductive structure 273.

In summary, the integrated circuit wire structure of the present invention has the first conductive structure and the second conductive structure that are connected, so that an integrated circuit wire structure with a high aspect ratio can be formed. Furthermore, the first product of the present invention The bulk circuit wire structure has a first conductive substructure and a second conductive substructure that are in contact up and down, wherein the width of the second conductive substructure is greater than the width of the first conductive substructure to improve the existing wire interconnection structure in the semiconductor field.

200: Integrated circuit wire structure

210: substrate

221: first etch stop layer

223: second etch stop layer

231: first dielectric layer

231a: first dielectric layer

231b: second dielectric layer

233: second dielectric layer

271: The first conductive structure

271a: first conductive substructure

271b: second conductive substructure

271c: first upper top

271d: the first bottom

273: second conductive structure

273a: second upper top

273b: second bottom bottom

Claims (9)

A method for manufacturing an integrated circuit wire structure includes: providing a substrate and a first dielectric layer on the substrate; forming a first etching mask on the first dielectric layer; and etching the first etching mask through the first etching mask A first dielectric layer to form a trench; a first conductive structure is formed in the trench, and a conductive layer is formed on the first conductive structure and the first dielectric layer, wherein the first conductive structure has a first conductive structure An upper bottom and a first lower bottom, the width of the first upper bottom is greater than the width of the first lower bottom; a second etching mask aligned with the first conductive structure is formed on the conductive layer; and through the second etching The mask etches the conductive layer to form a second conductive structure contacting the first conductive structure, the second conductive structure has a second upper bottom and a second lower bottom, the second upper bottom has a smaller width than the second lower bottom The width of the first upper bottom part contacts the second lower bottom part. The manufacturing method according to claim 1, further comprising: forming a first etch stop layer between the substrate and the first dielectric layer. The manufacturing method according to claim 1, wherein the first dielectric layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is located on the first dielectric layer. The manufacturing method as described in claim 3, further comprising: A second etch stop layer is formed between the first dielectric layer and the second dielectric layer. The manufacturing method according to claim 3, wherein forming the trench includes: forming a second sub trench in the second dielectric layer; forming a first sub trench in the first dielectric layer to communicate with the second sub trench Groove to form the groove. The manufacturing method according to claim 5, wherein the width of the first sub-groove is smaller than the width of the second sub-groove. The manufacturing method according to claim 1, wherein the first conductive structure includes a first conductive substructure and a second conductive substructure, the second conductive substructure is located on the first conductive substructure, and the second conductive substructure The width of the structure is greater than the width of the first conductive substructure. An integrated circuit wire structure, comprising: a substrate; a first dielectric layer located on the substrate; a first conductive structure located in the first dielectric layer; a second dielectric layer located on the first dielectric layer And a second conductive structure located in the second dielectric layer, wherein the first conductive structure includes a first conductive substructure and a second conductive substructure, the second conductive The substructure is located on the first conductive substructure, the second conductive structure contacts the second conductive substructure of the first conductive structure, wherein the first conductive structure has a first upper bottom and a first lower bottom, the first The width of the upper bottom is greater than the width of the first lower bottom, and the second conductive structure has a second upper bottom and a second lower bottom. The width of the second upper bottom is smaller than the width of the second lower bottom. The bottom part contacts the second lower bottom part. The integrated circuit wire structure according to claim 8, wherein the width of the second conductive substructure is greater than the width of the first conductive substructure.

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