TWI747075B - Interface circuit and communication apparatus - Google Patents

Abstract

An interface circuit includes a plurality of communication devices, an analog-to-digital (AD) conversion circuit that converts an analog signal to digital data, and a control circuit that reads the digital data in response to read-request signals received from the plurality of communication devices.

Description

Interface circuit and communication device

The invention relates to an interface circuit and a communication device.

In recent years, in mobile communication terminals such as mobile phones and smart phones, a single terminal is required to cope with the multi-band and multi-mode multi-frequency and wireless methods. For such communication devices that cope with multi-frequency bands and multi-modes, it is required to perform high-speed processing of multiple transmission and reception signals without deteriorating the quality. For example, LAA (Licensed-Assisted Access) has been standardized, in which unlicensed frequency bands in the 5GHz band used in wireless LANs are used as a supplementary to carrier aggregation (CA) in LTE-Advanced. Cell, thereby seeking to improve throughput.

The communication device generally has a structure that monitors the temperature and compensates for the gain caused by the temperature change. For example, a structure is disclosed in which an analog signal from a temperature sensor is AD converted and imported (for example, Patent Document 1). Prior art literature Patent literature

Patent Document 1: Specification of US Patent No. 8526995

The problem to be solved by the invention

For example, in a structure in which communication elements for wireless LAN and communication elements for LTE are mixed, when temperature sensors and AD conversion circuits are provided for each communication element, the circuit scale and power consumption increase. Subject.

The present invention has been completed in view of the above circumstances, and its object is to realize an interface circuit and a communication device that can reduce the circuit scale and power consumption. Technical means to solve the problem

An interface circuit of one aspect of the present invention includes: a plurality of communication elements; an AD conversion circuit for AD conversion of analog signals to digital data; Digital data.

In this structure, the AD conversion circuit is shared by a plurality of communication elements. As a result, the circuit scale and power consumption of the interface circuit can be reduced.

A communication device according to one aspect of the present invention includes: the above-mentioned interface circuit; a power amplifier circuit that amplifies a high-frequency signal; and a sensor that detects the temperature of the power amplifier circuit and uses the detected value as the aforementioned analog signal Output.

In this configuration, by sharing the AD conversion circuit by a plurality of communication elements, the circuit scale and power consumption of the communication device can be reduced. Invention effect

According to the present invention, it is possible to provide an interface circuit and a communication device capable of reducing circuit scale and power consumption.

Hereinafter, the interface circuit and the communication device according to the embodiment will be described in detail based on the drawings. In addition, the present invention is not limited by this embodiment. Each embodiment is an illustration, and it is self-evident that partial substitution or combination of the structure shown in the different embodiment can be performed. After the second embodiment, description of the matters common to the first embodiment will be omitted, and only the differences will be described. In particular, the same action and effect based on the same structure will not be mentioned in each embodiment. (Embodiment 1)

FIG. 1 is a block diagram showing an example of a schematic configuration of an interface circuit according to the embodiment. FIG. 2 is a diagram showing an example of the configuration of the main part of the communication device according to the embodiment. As shown in FIG. 1, the interface circuit 1 includes communication elements 10-1 and 10-2, an AD conversion circuit 20, and a control circuit 30. In the present disclosure, the communication element 10-1 is, for example, a communication element for LTE in the 5 GHz band, and the communication element 10-2 is, for example, a communication element for WiFi. In addition, in the present disclosure, the AD conversion circuit 20 converts the analog signal A_sig AD from the sensor 2 into digital data ts_data. In addition, in the present disclosure, the sensor 2 and the AD conversion circuit 20 are shared by two communication elements 10-1 and 10-2. In the following description, because the two communication elements 10-1, 10-2 and their constituent elements are the same, it is omitted when there is no need to distinguish between the two communication elements 10-1, 10-2 and their constituent elements. Symbols "-1", "-2", "_1", "_2".

As shown in FIG. 2, when the interface circuit 1 according to the embodiment is applied to the communication device 100, for the sensor 2, for example, a temperature sensor that detects the temperature of the power amplifier circuit 4 for high-frequency amplification can be exemplified. The sensor, but not limited to this, may also be an ultrasonic sensor, an infrared sensor, or a vibration sensor, for example. Furthermore, the sensor 2 only needs to be an analog circuit, and may be, for example, a voltmeter, an ammeter, or the like.

The communication element 10 outputs a read request signal of the digital data ts_data which is AD-converted to the analog signal A_sig which is the detection value of the sensor 2.

The control circuit 30 reads the digital data ts_data from the AD conversion circuit 20 according to the read request signal (the activation signal tkick and the import signal catch described later) output from the communication element 10 and outputs it to the communication element 10.

As shown in FIG. 1, the communication element 10-1 has a communication interface 3-1, a startup circuit 11-1, and a register 12-1. The communication element 10-2 has a communication interface 3-2, a startup circuit 11-2, and a register 12-2.

In the present disclosure, the communication interface 3-1 is, for example, the serial communication interface in the communication device 10-1 for LTE in the 5GHz band, and the communication interface 3-2 is, for example, the serial communication in the communication device 10-2 for WiFi. interface.

The communication interface 3-1 outputs the read command wr_1 of the digital data ts_data and the communication clock signal clk_1 to the startup circuit 11-1. The communication interface 3-2 outputs the read command wr_2 of the digital data ts_data and the communication clock signal clk_2 to the startup circuit 11-2. In the present disclosure, the communication clock signal clk_1 and the communication clock signal clk_2 are clock signals that are not synchronized with each other. The communication clock signal clk_1 and the communication clock signal clk_2 can also be synchronized.

The activation circuit 11-1 receives the read command wr_1 from the communication interface 3-1, and based on the read command wr_1, generates and outputs the activation signal tkick_1 for generating the enabling signal ts_en described later. The enabling signal ts_en is a signal output from the control circuit 30 in order to activate the AD conversion circuit 20. The activation signal tkick_1 is output to the control circuit 30 and the activation circuit 11-2.

The activation circuit 11-2 receives the read command wr_2 from the communication interface 3-2, and generates and outputs the activation signal tkick_2 for generating the enable signal ts_en based on the read command wr_2. The activation signal tkick_2 is output to the control circuit 30 and the activation circuit 11-1.

In addition, when the data of the read command wr_1 from the communication interface 3-1 and the activation signal tkick_2 from the activation circuit 11-2 is "1", the activation circuit 11-1 replaces the activation signal tkick_1, generates and outputs The import signal catch_1 of the digital data ts_data from the AD conversion circuit 20 is imported. The import signal catch_1 is output to the control circuit 30.

In addition, when the data of the read command wr_2 from the communication interface 3-2 and the activation signal tkick_1 from the activation circuit 11-1 are "1", the activation circuit 11-2 replaces the activation signal tkick_2 and generates and outputs for The import signal catch_2 of the digital data ts_data from the AD conversion circuit 20 is imported. The import signal catch_2 is output to the control circuit 30.

The control circuit 30 is based on the activation signal tkick_1 and the import signal catch_1 received as the read request signal from the activation circuit 11-1, and the activation signal tkick_2 and the import signal received as the read request signal from the activation circuit 11-2. The signal catch_2 controls the AD conversion circuit 20. In addition, the control circuit 30 outputs the digital data ts_data AD-converted by the AD conversion circuit 20 as the imported data data_1 to the temporary memory 12-1. In addition, the control circuit 30 outputs the digital data ts_data AD-converted by the AD conversion circuit 20 as the imported data data_2 to the register 12-2.

The register 12-1 outputs the imported data data_1 from the control circuit 30 to the communication interface 3-1.

The register 12-2 outputs the imported data data_2 from the control circuit 30 to the communication interface 3-2.

Next, the basic operations of the starting circuit 11-1 and the starting circuit 11-2 will be described. Fig. 3 is a block diagram showing an example of the internal structure of the starting circuit. Fig. 4 is a timing chart showing a first basic operation example of the starting circuit. Fig. 5 is a timing chart showing a second basic operation example of the starter circuit. Fig. 6 is a timing chart showing a third basic operation example of the starting circuit. Fig. 7 is a timing chart showing a fourth basic operation example of the starting circuit. In FIG. 4, an example of outputting the read command wr_1 from the communication interface 3-1 is shown. In FIG. 5, an example is shown in which the read command wr_2 is output from the communication interface 3-2 in a predetermined period P'after the read command wr_1 is output from the communication interface 3-1. Fig. 6 shows an example of outputting a read command wr_2 from the communication interface 3-2 after a predetermined period P'. In FIG. 7, an example is shown in which the read command from the communication interface 3-2 is output during two cycles of the communication clock signal clk_2 after the read command wr_1 is output from the communication interface 3-1 wr_2.

As shown in Figure 4, if the control signal generation circuit 111-1 of the start circuit 11-1 receives the read command wr_1 from the communication interface 3-1, it will start the signal tkick_1 in synchronization with the rising edge of the communication clock signal clk_1. The data value is set to "1".

The synchronization circuit 112-2 of the activation circuit 11-2 synchronously sets the data value of the activation synchronization signal sync_tkick_1 to "1" in synchronization with the rising edge of the communication clock signal clk_2 two cycles from the rising edge of the activation signal tkick_1.

After the given period P has elapsed, the control signal generating circuit 111-1 synchronizes with the rising edge of the start reset signal tkick_1_rst output from the control circuit 30 and sets the data value of the start signal tkick_1 to "0".

The synchronization circuit 112-2 synchronously sets the data value of the start synchronization signal sync_tkick_1 to "0" in synchronization with the rising edge of the communication clock signal clk_2 two cycles from the falling edge of the start signal tkick_1.

In addition, as shown in FIG. 5, if the control signal generating circuit 111-2 of the activation circuit 11-2 receives a signal from the communication interface 3-2 during a given period P'when the data value of the activation synchronization signal sync_tkick_1 becomes "1" Read the command wr_2, and set the data value of the catch_2 input signal to "1" in synchronization with the rising edge of the communication clock signal clk_2. Then, the control signal generating circuit 111-2 sets the data value of the lead-in signal catch_2 to "0" in synchronization with the rising edge of the lead-in reset signal catch_rst output from the control circuit 30.

In addition, as shown in FIG. 6, if the control signal generating circuit 111-2 is not included in the activation signal tkick_1 for a given period P when the data value becomes "1" and the data value of the activation synchronization signal sync_tkick_1 becomes "1" When any one of the periods P′ receives the read command wr_2 from the communication interface 3-2, the data value of the start signal tkick_2 is set to "1" in synchronization with the rising edge of the communication clock signal clk_2.

In addition, as shown in FIG. 7, if the control signal generating circuit 111-2 has two communication clock signals clk_2 from when the data value of the start signal tkick_1 becomes "1" until the data value of the start synchronization signal sync_tkick_1 becomes "1" When receiving the read command wr_2 from the communication interface 3-2 during the cycle, the data value of the start signal tkick_2 is set to "1" in synchronization with the rising edge of the communication clock signal clk_2. Then, the control signal generating circuit 111-2 sets the data value of the start signal tkick_2 to "0" in synchronization with the rising edge of the start reset signal tkick_2_rst output from the control circuit 30 after the predetermined period p has elapsed.

The synchronization circuit 112-1 synchronizes with the rising edge of the communication clock signal clk_1 after two cycles from the falling edge of the start signal tkick_2 and sets the data value of the start synchronization signal sync_tkick_2 to "0".

Next, the specific operation of the interface circuit 1 according to the embodiment will be described. FIG. 8 is a timing chart showing a specific first operation example of the interface circuit according to the embodiment. FIG. 9 is a timing chart showing a specific second operation example of the interface circuit according to the embodiment. FIG. 10 is a timing chart showing a specific third operation example of the interface circuit according to the embodiment. FIG. 11 is a timing chart showing a specific fourth operation example of the interface circuit according to the embodiment. FIG. 12 is a timing chart showing a specific fifth operation example of the interface circuit according to the embodiment. FIG. 13 is a timing chart showing a specific sixth operation example of the interface circuit according to the embodiment. FIG. 14 is a timing chart showing a specific seventh operation example of the interface circuit according to the embodiment. 15 is a timing chart showing a specific eighth operation example of the interface circuit according to the embodiment. In FIGS. 8 to 11, the time point when the read command wr_1 is output from the communication interface 3-1 and the data value of the activation signal tkick_1 becomes "1" is shown as a starting point. In FIGS. 12 to 15, the time point when the read command wr_2 is output from the communication interface 3-2 and the data value of the activation signal tkick_2 becomes "1" is shown as a starting point.

In the present disclosure, the clock cycles of the communication clock signal clk_1 and the communication clock signal clk_2 are considered to be sufficiently small relative to the clock cycle of the sampling clock signal ts_clk in the AD conversion circuit 20. That is, the predetermined periods P, P', p, and p'shown in Figs. 4 to 7 are regarded as substantially equal. In addition, as shown in FIGS. 8 to 15, in the present disclosure, a period of 10 clock cycles including the sampling clock signal ts_clk from the data value of the enable signal tkick_1 or the enable signal tkick_2 to "1" is used as the AD conversion circuit 20 In the "standby period P1" in the standby period P1, the period of 8 clock cycles including the sampling clock signal ts_clk after the standby period P1 is regarded as the "AD conversion period P2" in the AD conversion circuit 20, and the standby period P1 and the AD conversion period P2 The total period is referred to as the “operation period P0” of the AD conversion circuit 20. The control circuit 30 has a function of counting the sampling clock signal ts_clk in the AD conversion circuit 20. The standby period P1 corresponds to the predetermined periods P, P', p, and p'shown in Figs. 4 to 7.

In addition, the number of clock cycles included in the standby period P1 and the number of clock cycles included in the AD conversion period P2 are examples, and are not limited to the number of clock cycles described above. For example, the number of clock cycles included in the standby period P1 may be the number of clock cycles that can ensure the time until the AD conversion in the AD conversion circuit 20 stabilizes. In addition, although the present embodiment illustrates the case where the digital data ts_data in the AD conversion circuit 20 is 8-bit data, for example, when the digital data ts_data in the AD conversion circuit 20 is 12-bit data, the AD conversion period P2 only needs to be in the form of 12 clock cycles including the sampling clock signal ts_clk. The present disclosure is not limited by the number of clock cycles included in the standby period P1 and the number of clock cycles included in the AD conversion period P2.

In FIGS. 8 to 11, the following example is shown, that is, at the time when the read command wr_1 is output from the communication interface 3-1 and the data value of the activation signal tkick_1 output from the activation circuit 11-1 becomes "1" At this point, counting starts during the standby period P1, the AD conversion period P2, and the operation period P0. That is, in the examples shown in FIGS. 8 to 11, based on the read command wr_1 from the communication interface 3-1, the digital data ts_data after AD conversion is imported into the register 12-1 as the imported data data_1.

The control circuit 30 starts the output of the sampling clock signal ts_clk in the AD conversion circuit 20 when the data value of the start signal tkick_1 becomes "1", and sets the data value of the enable signal ts_en to "1" to start the sampling clock Count of signal ts_clk.

If 10 clock cycles of the sampling clock signal ts_clk have elapsed during the standby period P1, the control circuit 30 sets the data value of the AD conversion command xTCONV to "1" in synchronization with the falling edge of the sampling clock signal ts_clk, and outputs the start complex Bit signal tkick_1_rst. As a result, the data value of the start signal tkick_1 is reset to "0".

The AD conversion circuit 20 converts the analog signal A_sigAD from the sensor 2 into digital data ts_data in 8 clock cycles of the sampling clock signal ts_clk of the P2 during the subsequent AD conversion period.

If 8 clock cycles of the sampling clock signal ts_clk have passed during the AD conversion period P2, the control circuit 30 reads the AD converted digital data ts_data from the AD conversion circuit 20, and outputs it to the register 12 as the imported data data_1. 1. In addition, the control circuit 30 sets the data value of the enable signal ts_en and the AD conversion command xTCONV to "0" in synchronization with the falling edge of the sampling clock signal ts_clk.

In the examples shown in FIGS. 8 and 9, in the standby period P1, the data value of the activation signal tkick_2 output from the activation circuit 11-2 is "0", that is, the read command is not output from the communication interface 3-2 wr_2. In this case, the control circuit 30 does not output the AD-converted digital data ts_data to the register 12-2.

In FIG. 9, the following example is shown, that is, the data value of the start signal tkick_2 output from the start circuit 11-2 during the AD conversion period P2 is "1", that is, the data value is read from the output of the communication interface 3-2 Instruction wr_2. In this case, the control circuit 30 starts the counting of 10 clock cycles of the sampling clock signal ts_clk in the new standby period P1 at the time point when the data value of the start signal tkick_2 becomes "1". In addition, in this case, the control circuit 30 maintains the data value "1" of the enabling signal ts_en.

In FIG. 10, the following example is shown, that is, the data value of the lead-in signal catch_2 output from the startup circuit 11-2 during the standby period P1 is "1", that is, the read command is output from the communication interface 3-2 wr_2. In this case, the control circuit 30 outputs the AD-converted digital data ts_data to the register 12-1 as the import data data_1, and outputs to the register 12-2 as the import data data_2.

In addition, if 8 clock cycles of the sampling clock signal ts_clk have elapsed during the AD conversion period P2, the control circuit 30 sets the data value of the enable signal ts_en and the AD conversion command xTCONV in synchronization with the falling edge of the sampling clock signal ts_clk "0", and output the import reset signal catch_rst. As a result, the data value of the import signal catch_2 is reset to "0".

In FIG. 11, an example is shown in which the data value of the activation signal tkick_1 output from the activation circuit 11-1 becomes "1", and the data value of the activation signal tkick_2 output from the activation circuit 11-2 becomes "1". 1". Here, the data value of the activation signal tkick_1 and the data value of the activation signal tkick_2 become "1" at the same time, which means that, as shown in Fig. 7, the data value of the activation signal tkick_1 becomes "1" until the synchronization signal sync_tkick_1 is activated. During the two cycles of the communication clock signal clk_2 until the data value becomes "1", the read command wr_2 from the communication interface 3-2 is input. In this case, the control circuit 30 outputs the AD-converted digital data ts_data to the register 12-1 as the import data data_1, and outputs to the register 12-2 as the import data data_2.

In FIGS. 12 to 15, the following example is shown, that is, when the read command wr_2 is output from the communication interface 3-2 and the data value of the activation signal tkick_2 output from the activation circuit 11-2 becomes "1" At this point, counting starts during the standby period P1, the AD conversion period P2, and the operation period P0. That is, in the example shown in FIGS. 12 to 15, based on the read command wr_2 from the communication interface 3-2, the digital data ts_data after the AD conversion is imported as the import data data_2 into the register 12-2.

The control circuit 30 starts the output of the sampling clock signal ts_clk in the AD conversion circuit 20 when the data value of the start signal tkick_2 becomes "1", and sets the data value of the enable signal ts_en to "1" to start the sampling clock Count of signal ts_clk.

If 10 clock cycles of the sampling clock signal ts_clk have elapsed during the standby period P1, the control circuit 30 sets the data value of the AD conversion command xTCONV to "1" in synchronization with the falling edge of the sampling clock signal ts_clk, and outputs the start complex Bit signal tkick_2_rst. As a result, the data value of the start signal tkick_2 is reset to "0".

The AD conversion circuit 20 converts the analog signal A_sigAD from the sensor 2 into digital data ts_data in 8 clock cycles of the sampling clock signal ts_clk of the P2 during the subsequent AD conversion period.

If 8 clock cycles of the sampling clock signal ts_clk have passed during the AD conversion period P2, the control circuit 30 reads the AD converted digital data ts_data from the AD conversion circuit 20, and outputs it to the register 12 as the imported data data_2 -2. In addition, the control circuit 30 sets the data value of the enable signal ts_en and the AD conversion command xTCONV to "0" in synchronization with the falling edge of the sampling clock signal ts_clk.

In the examples shown in FIGS. 12 and 13, in the standby period P1, the data value of the activation signal tkick_1 output from the activation circuit 11-1 is "0", that is, the read command is not output from the communication interface 3-1 wr_1. In this case, the control circuit 30 does not output the AD-converted digital data ts_data to the register 12-1.

In FIG. 13, the following example is shown, that is, during the AD conversion period P2, the data value of the activation signal tkick_1 output from the activation circuit 11-1 is "1", that is, the data value of the activation signal tkick_1 output from the communication interface 3-1 is "1". Issue the instruction wr_1. In this case, the control circuit 30 starts counting of 10 clock cycles of the sampling clock signal ts_clk in the new standby period P1 when the data value of the start signal tkick_1 becomes "1". In addition, in this case, the control circuit 30 maintains the data value "1" of the enabling signal ts_en.

In FIG. 14, the following example is shown, that is, in the standby period P1, the data value of the catch_1 output signal from the start circuit 11-1 is "1", that is, the data value of the catch_1 output from the communication interface 3-1 is read Instruction wr_1. In this case, the control circuit 30 outputs the AD-converted digital data ts_data as the imported data data_2 to the register 12-2, and outputs it as the imported data data_1 to the register 12-1.

In addition, if 8 clock cycles of the sampling clock signal ts_clk have elapsed during the AD conversion period P2, the control circuit 30 sets the data value of the enable signal ts_en and the AD conversion command xTCONV in synchronization with the falling edge of the sampling clock signal ts_clk "0", and output the import reset signal catch_rst. As a result, the data value of the import signal catch_1 is reset to "0".

In FIG. 15, an example is shown in which the data value of the activation signal tkick_2 output from the activation circuit 11-2 becomes "1", and the data value of the activation signal tkick_1 output from the activation circuit 11-1 becomes "1". 1". In this case, the control circuit 30 outputs the AD-converted digital data ts_data as the imported data data_2 to the register 12-2, and outputs it as the imported data data_1 to the register 12-1.

Fig. 16 is a diagram showing output targets of digital data in each of the operation examples shown in Figs. 8 to 15. As shown in FIG. 16, the control circuit 30 sets the communication element 10-1 as the output target of the digital data ts_data when the data value of the activation signal tkick_1 output from the activation circuit 11-1 becomes "1". In addition, if the data value of the start signal tkick_1 output from the start circuit 11-1 becomes "1" in the standby period P1 of the AD conversion circuit 20, the data value of the catch_2 output signal from the start circuit 11-2 becomes "1", the control circuit 30 sets the communication element 10-2 as the output target of the digital data ts_data.

In addition, as shown in FIG. 16, the control circuit 30 sets the communication element 10-2 as the output target of the digital data ts_data at the time point when the data value of the activation signal tkick_2 output from the activation circuit 11-2 becomes "1". In addition, if the data value of the start signal tkick_2 output from the start circuit 11-2 becomes "1" in the standby period P1 of the AD conversion circuit 20, the data value of the lead-in signal catch_1 output from the start circuit 11-1 becomes "1" "1", the control circuit 30 sets the communication element 10-1 as the output target of the digital data ts_data.

In addition, FIG. 15 shows an example in which the data value of the activation signal tkick_2 output from the activation circuit 11-2 becomes "1", and the data value of the activation signal tkick_1 output from the activation circuit 11-1 It becomes "1", but in FIG. 16, the data value of the start signal tkick_2 output from the start circuit 11-2 becomes "1" at the same time that the data value of the start signal tkick_1 output from the start circuit 11-1 becomes "1" In the case of ", the control circuit 30 outputs the AD-converted digital data ts_data to the register 12-1 as the imported data data_1, and outputs to the register 12-2 as the imported data data_2.

In this embodiment, as described above, the AD conversion circuit 20 is shared by the two communication elements 10-1 and 10-2. Therefore, the circuit scale and power consumption of the communication device 100 can be reduced. Specifically, compared with a structure in which an analog circuit and an AD conversion circuit are provided for each communication element (that is, a structure including a plurality of analog circuits, a plurality of AD conversion circuits, and a plurality of communication elements), in this embodiment In this case, the AD conversion circuit 20 is shared by two communication elements 10-1 and 10-2. By reducing the AD conversion circuit, the circuit area can be reduced. In addition, by reducing the number of AD conversion circuits, it is also possible to reduce the power consumed in the plurality of AD conversion circuits.

In addition, the time required for reading the digital data ts_data can be shortened. Specifically, in this embodiment, not only one AD conversion circuit is shared, but also a control circuit that reads digital data based on read request signals from a plurality of communication elements. If the AD conversion circuit is only shared, after the action of one communication element is completed, the action of the other communication element is started. As a result, the operation period of the AD conversion circuit requires an amount corresponding to the number of communication elements. However, in the embodiment of the present application, the operation period of the AD conversion circuit 20 can be shortened by using the control circuit to perform control as described above.

In addition, although the example in which the AD conversion circuit 20 is shared by two communication elements 10-1 and 10-2 is shown in the above-mentioned embodiment, it is also possible to share the AD conversion circuit 20 by a plurality of communication elements of three or more.

Fig. 17 is a diagram showing a configuration example in which six communication elements share an AD conversion circuit. FIG. 18 is a diagram showing an example of an output target of digital data in the configuration example shown in FIG. 17.

In the example of the structure shown in FIG. 17, as shown in Example 1 of FIG. 18, the start signal tkick_1 is output from the communication element 10-1, and the catch_5 is output from the communication element 10-5 during the standby period P1. In this case Next, the control circuit 30 sets the communication element 10-1 and the communication element 10-5 as the output target of the digital data ts_data.

In addition, in the configuration example shown in FIG. 17, as shown in Example 2 of FIG. 18, the start signal tkick_4 is output from the communication element 10-4, and during the standby period P1, the import signal catch_1 is output from the communication element 10-1, and The import signal catch_6 is output from the communication element 10-6. In this case, the control circuit 30 sets the communication element 10-1, the communication element 10-4, and the communication element 10-6 as the output objects of the digital data ts_data.

In addition, in the configuration example shown in FIG. 17, as shown in Example 3 of FIG. 18, the start signal tkick_2 is output from the communication element 10-2, and during the standby period P1, the import signal catch_3 is output from the communication element 10-3, and The import signal catch_5 is output from the communication element 10-5. In this case, the control circuit 30 sets the communication element 10-2, the communication element 10-3, and the communication element 10-5 as the output objects of the digital data ts_data.

In addition, in the configuration example shown in FIG. 17, as shown in Example 4 of FIG. 18, the start signal tkick_5 is output from the communication element 10-5, and during the standby period P1, the import signal catch_1 is output from the communication element 10-1, and from The communication element 10-2 outputs the import signal catch_2, and the communication element 10-6 outputs the import signal catch_6. In this case, the control circuit 30 connects the communication element 10-1, the communication element 10-2, the communication element 10-5, and The communication component 10-6 is set as the output target of the digital data ts_data.

In addition, in the structural example shown in FIG. 17, as shown in Example 5 of FIG. 18, the start signal tkick_3 and the start signal tkick_6 are simultaneously output from the communication element 10-3 and the communication element 10-6. In this case, the control The circuit 30 sets the communication element 10-3 and the communication element 10-6 as the output target of the digital data ts_data.

In this way, in the interface circuit 1 according to the embodiment, the AD conversion circuit 20 can be shared by a plurality of communication elements 10. As a result, the circuit scale and power consumption of the communication device 100 can be reduced. In addition, the time required for reading the data can be shortened.

The above-mentioned embodiments are used to make the present invention easy to understand, and are not used to limit the interpretation of the present invention. The present invention can be changed/improved without departing from its gist, and the present invention also includes equivalents thereof.

In addition, the present disclosure can adopt the following structures as described above or in place of the above.

(1) An interface circuit of one aspect of the present invention includes: a plurality of communication elements; an AD conversion circuit that AD converts analog signals into digital data; and a control circuit, based on the read request signals from the plurality of the aforementioned communication elements, Read the aforementioned digital data.

In a configuration in which AD conversion circuits are provided for each of a plurality of communication elements, the consumption current corresponding to the plurality of AD conversion circuits is required. In the above structure, the AD conversion circuit is shared by a plurality of communication elements. As a result, compared to a configuration in which the AD conversion circuit is provided for each of a plurality of communication elements, the circuit scale and power consumption of the interface circuit can be reduced.

(2) In the interface circuit of (1) above, in the case of receiving a read request signal from the first communication element among the plurality of communication elements, the control circuit outputs the digital data to the first communication element In the case of receiving a read request signal of a second communication element different from the first communication element, the control circuit outputs the digital data to the second communication element.

In this structure, the AD conversion circuit can be shared by a plurality of communication elements.

(3) In the interface circuit of (1) above, after receiving the read request signal from the first communication element of the plurality of communication elements, the AD conversion circuit needs a standby period, and the AD conversion circuit needs a standby period, and the signal is received during the standby period In the case of a read request signal from a second communication element different from the aforementioned first communication element, the control circuit outputs the aforementioned digital data to the second communication element.

If the AD conversion circuit is only shared, after the action of one communication element is completed, the action of the other communication element is started. As a result, the operation period of the AD conversion circuit requires an amount corresponding to the number of communication elements. In the interface circuit of this structure, the time required for data reading can be shortened by the above-mentioned processing.

(4) In the interface circuit of (1) above, the communication element includes: a communication interface, which outputs a read command of the digital data; The start signal or the import signal used to import the aforementioned digital data as the aforementioned read request signal. The aforementioned communication element includes a first communication element and a second communication element different from the first communication element. After the activation circuit has output the activation signal, the AD conversion circuit requires a standby period, and during the standby period the read command output from the communication interface of the second communication element is received, the activation of the second communication element The circuit outputs the aforementioned lead-in signal.

In this structure, digital data is simultaneously output to both the communication element that has output the start signal and the communication element that has output the lead-in signal during the standby period. As a result, the time required for data reading can be shortened. In addition, the circuit scale of the startup circuit can be reduced.

(5) A communication device according to one aspect of the present invention includes: any one of the above-mentioned (1) to (4) interface circuits; a power amplifier circuit that amplifies high-frequency signals; and a sensor that affects the power amplifier circuit The temperature is detected, and the detected value is output as the aforementioned analog signal.

In an interface circuit having an AD conversion circuit for each of a plurality of communication elements, consumption current corresponding to the plurality of AD conversion circuits is required. In the structure using the interface circuit of the present structure in which the AD conversion circuit is shared by a plurality of communication elements, the circuit scale and consumption of the interface circuit can be reduced compared to a structure in which the AD conversion circuit is provided for each of the plurality of communication elements. electricity. Therefore, the circuit scale and power consumption of the communication device can be reduced. In addition, if only the AD conversion circuit is shared, after the action of one communication element is completed, the action of the other communication element is started. As a result, the operation period of the AD conversion circuit requires an amount corresponding to the number of communication elements. In the structure using the interface circuit of this structure, the time required for data reading can be shortened by the above-mentioned processing.

According to the present disclosure, the circuit scale and power consumption can be reduced, and furthermore, the time required for data reading can be shortened.

1: Interface circuit 2: sensor 3-1, 3-2: Communication interface 4: Power amplifier circuit 10, 10-1, 10-2, 10-3, 10-4, 10-5, 10-6: communication components 11-1, 11-2: Starting circuit 12-1, 12-2: register 20: AD conversion circuit 30: Control circuit 100: Communication device 111-1, 111-2: Control signal generation circuit 112-1, 112-2: Synchronization circuit

FIG. 1 is a block diagram showing an example of a schematic configuration of an interface circuit according to the embodiment. FIG. 2 is a diagram showing an example of the configuration of the main part of the communication device according to the embodiment. Fig. 3 is a block diagram showing an example of the internal structure of the starting circuit. Fig. 4 is a timing chart showing a first basic operation example of the starting circuit. Fig. 5 is a timing chart showing a second basic operation example of the starter circuit. Fig. 6 is a timing chart showing a third basic operation example of the starting circuit. Fig. 7 is a timing chart showing a fourth basic operation example of the starting circuit. FIG. 8 is a timing chart showing a specific first operation example of the interface circuit according to the embodiment. FIG. 9 is a timing chart showing a specific second operation example of the interface circuit according to the embodiment. FIG. 10 is a timing chart showing a specific third operation example of the interface circuit according to the embodiment. FIG. 11 is a timing chart showing a specific fourth operation example of the interface circuit according to the embodiment. FIG. 12 is a timing chart showing a specific fifth operation example of the interface circuit according to the embodiment. FIG. 13 is a timing chart showing a specific sixth operation example of the interface circuit according to the embodiment. FIG. 14 is a timing chart showing a specific seventh operation example of the interface circuit according to the embodiment. 15 is a timing chart showing a specific eighth operation example of the interface circuit according to the embodiment. Fig. 16 is a diagram showing output targets of digital data in each of the operation examples shown in Figs. 8 to 15. Fig. 17 is a diagram showing a configuration example in which six communication elements share an AD conversion circuit. FIG. 18 is a diagram showing an example of an output target of digital data in the configuration example shown in FIG. 17.

1: Interface circuit

2: sensor

3-1, 3-2: Communication interface

10-1, 10-2: communication components

11-1, 11-2: Starting circuit

12-1, 12-2: register

20: AD conversion circuit

30: Control circuit

Claims (5)

An interface circuit comprising: a plurality of communication elements; an AD conversion circuit that AD converts analog signals into digital data; and a control circuit that reads the digital data according to the read request signals from the plurality of communication elements, and The aforementioned digital data is output to the aforementioned communication element which outputs the aforementioned read request signal. The interface circuit according to claim 1, wherein, in the case of receiving a read request signal from a first communication element among the plurality of communication elements, the control circuit outputs the digital data to the first communication element, In the case of receiving a read request signal of a second communication element different from the first communication element, the control circuit outputs the digital data to the second communication element. The interface circuit according to claim 1, wherein the AD conversion circuit needs a standby period after receiving a read request signal from the first communication element among the plurality of communication elements, and the AD conversion circuit needs a standby period during the standby period. In the case of a read request signal of a second communication element different from the first communication element, the control circuit outputs the digital data to the second communication element. The interface circuit according to claim 1, wherein the communication element includes: a communication interface that outputs a read command for the digital data; and an activation circuit that generates an activation for starting the AD conversion circuit based on the read command A signal or an import signal for importing the aforementioned digital data as the aforementioned read request signal. The aforementioned communication element includes a first communication element and a second communication element different from the first communication element. After the circuit outputs the aforementioned start signal, the aforementioned AD conversion The circuit needs a standby period, and in the case where the read command output from the communication interface of the second communication element is received during the standby period, the activation circuit of the second communication element outputs the lead-in signal. A communication device comprising: the interface circuit according to any one of claims 1 to 4; a power amplifier circuit for amplifying high-frequency signals; and a sensor for detecting the temperature of the power amplifier circuit, and The detected value is output as the aforementioned analog signal.

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