TWI746295B - Clock and data recovery circuit and associated signal processing method - Google Patents

Abstract

The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.

Description

Clock and data recovery circuit and its signal processing method

The present invention relates to a clock and data recovery (CDR) circuit, and more specifically, to a clock and data recovery circuit suitable for high-speed applications and a signal processing method thereof.

In a conventional digital-based (Digital-based) clock and data recovery (CDR) circuit, loop latency (loop latency) is controlled by a digital controller in the digital-based CDR . The speed of digital controllers is usually limited by conventional semiconductor processes, which causes digital-based CDR circuits to suffer long loop delays. Therefore, conventional digital-based CDR circuits are not suitable for high-speed applications.

Therefore, the object of the present invention is to provide a digital-based CDR circuit that can reduce the overall loop delay time to solve the above-mentioned problems.

According to an embodiment of the present invention, a clock and data recovery (CDR) circuit is provided. The clock and data recovery circuit includes a first phase detector, a controller, and a phase filter. In the operation of the CDR, the first phase detector compares the phase of the input signal with the phase of the clock signal to generate the first phase detector. Phase detection result. The controller generates a control signal according to the first phase detection result. The phase filter receives the control signal and the auxiliary signal to generate a clock signal, wherein the auxiliary signal is generated according to the first phase detection result.

According to another embodiment of the present invention, there is provided a signal processing method for a clock and data recovery circuit, including: comparing the phase of an input signal with the phase of a clock signal to generate a phase detection result; and passing through a controller according to the phase detection result Generate a low-frequency control signal, wherein the control signal includes frequency and phase information; generate a high-frequency auxiliary signal according to the phase detection result, wherein the auxiliary signal includes phase information; and use a phase filter to receive the control signal and The auxiliary signal is used to generate the clock signal, wherein the phase filter has a first path and a second path, the first path is used to receive the control signal to generate the clock signal, and the second path The path uses the auxiliary signal to adjust the phase of the clock signal to reduce the overall delay of the CDR circuit.

In the CDR circuit of the present invention, the total delay time of the CDR circuit can be effectively reduced by the auxiliary signal in the second path, so the performance of the CDR circuit can be improved.

These and other objects of the present invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in the various drawings and drawings.

100, 200, 300: CDR circuit

110, 210, 310: phase detector

120, 220, 320: Controller

130, 230, 330: phase filter

132,232,240,332,339: phase interpolator

134,234,334: phase detector

136,236,336: loop filter

138,238,338: Oscillator

400, 402, 404, 406, 408: steps

The accompanying drawings are included to provide a further understanding of the present invention, and the accompanying drawings are incorporated in this specification and constitute a part of this specification. The drawings illustrate the embodiments of the present invention, and together with the description are used to explain the principle of the present invention. In the drawings: Figure 1 is a schematic diagram showing a CDR circuit according to the first embodiment of the present invention.

Fig. 2 is a schematic diagram showing a CDR circuit according to the second embodiment of the present invention.

Fig. 3 is a schematic diagram showing a CDR circuit according to a third embodiment of the present invention.

Fig. 4 shows a flowchart of a signal processing method of a CDR circuit according to an embodiment of the present invention.

Certain vocabulary is used to refer to specific elements in the specification and the scope of the patent application. Those skilled in the art should understand that electronic device manufacturers may use different terms to refer to the same component. This specification and the scope of the patent application do not use differences in names as a way of distinguishing elements, but use differences in functions of elements as a basis for distinction. The "including" mentioned in the entire specification and the scope of the patent application is an open term, so it should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect electrical connection means. Therefore, if it is described that the first device is electrically connected to the second device, it means that the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or connection means.

FIG. 1 is a schematic diagram showing the CDR circuit 100 according to the first embodiment of the present invention. As shown in Figure 1, the CDR circuit 100 includes a phase detector 110, a controller 120, and a phase filter 130. The phase filter 130 includes a phase interpolator 132, a phase detector 134, a loop filter 136, and an oscillator. 138. In addition, the phase detector 134 in the phase filter 130 may be replaced by a phase and frequency detector.

In the operation of the CDR circuit 100, the phase detector 110 receives the input signal (input serial data) Din and the clock signal CLK to generate a phase detection result V_pd1, where the phase detection result V_pd1 indicates the phases of the input signal Din and the clock signal CLK Information, that is, whether the clock signal CLK is phase-lead or phase-lag relative to the input signal Din and/or the phase of both Position difference information. Then, the controller 120 implemented by a digital circuit receives the phase detection result V_pd1 and generates a control signal Vc1, thereby controlling the phase interpolator 132 to adjust the phase of the clock signal CLK to generate a phase-shifted clock signal CLK′. Wherein, the controller 120 may be a digital filter for filtering the phase detection result V_pd1 in frequency. In this embodiment, the control signal Vc1 is a digital code generated based on the phase information of the input signal Din and the clock signal CLK, and the phase interpolator 132 uses the control signal Vc1 to compensate the phase error of the clock signal CLK to generate Phase shift clock signal CLK'. Then, the phase detector 134 compares the phase of the phase-shifted clock signal CLK' with the phase of the reference clock signal CLK_REF to generate a phase detection result V_pd2, where the phase detection result V_pd2 indicates the phase-shifted clock signal CLK' and the reference clock signal CLK_REF The phase information (phase difference information). The loop filter 136 receives the phase detection result V_pd2 to generate a filtered signal Vc2. Finally, the oscillator 138 receives the filtered signal Vc2 and generates a clock signal CLK as the output clock signal of the CDR circuit 100.

The above operations of the phase detector 110, the controller 120, the phase interpolator 132, the phase detector 134, the loop filter 136, and the oscillator 138 can be regarded as the first path of the CDR circuit 100. Since the speed of the controller 120 is generally limited by the semiconductor process, the first path has a longer loop delay, which deteriorates the performance of the CDR circuit 100. Specifically, since the operating frequency of the controller 120 in the first path is low, the phase detection result V_pd1 and the control signal Vc1 are both low-speed signals with a slower frequency, and the control signal Vc1 contains both frequency and phase information. In order to solve the long loop delay problem of the first path, the phase detector 110 further generates an auxiliary signal V_aux to the oscillator 138, so that the oscillator 138 generates a clock signal CLK based on both the filtered signal Vc2 and the auxiliary signal V_aux , In order to reduce the total delay time of the CDR circuit 100. In detail, the auxiliary signal V_aux may be a pulse signal indicating phase information of the input signal Din and the clock signal CLK (for example, the auxiliary signal V_aux may be generated based on the phase detection result V_pd1), and the auxiliary signal V_aux may be a high-speed signal with a faster frequency, where Contains only For phase information, the oscillator 138 can refer to both the auxiliary signal V_aux and the filtered signal Vc2 at the same time to determine the frequency of the clock signal CLK (that is, both the auxiliary signal V_aux and the filtered signal Vc2 can control/adjust the frequency of the clock signal CLK).

In the embodiment shown in FIG. 1, the phase detector 110 and the oscillator 138 further form a second path, which uses the auxiliary signal V_aux to adjust the phase of the clock signal CLK. Therefore, since the delay time of the second path without passing through the controller is much smaller, the loop delay time of the first path and the total delay time of the CDR circuit 100 can be effectively reduced, and thus the performance of the CDR circuit 100 can be improved.

FIG. 2 is a schematic diagram showing a CDR circuit 200 according to the second embodiment of the present invention. As shown in Figure 2, the CDR circuit 200 includes a phase detector 210, a controller 220, a phase filter 230, and a phase interpolator 240. The phase filter 230 includes a phase interpolator 232, a phase detector 234, and a loop filter.器236 and oscillator 238. In addition, the phase detector 234 in the phase filter 230 may be replaced by a phase and frequency detector.

In the operation of the CDR circuit 200, the phase detector 210 receives the input signal Din and the clock signal CLK to generate a phase detection result V_pd1, where the phase detection result V_pd1 indicates the phase information of the input signal Din and the clock signal CLK, that is, the clock signal The CLK is phase-lead or phase-lag relative to the input signal Din, and/or the phase difference information between the two. Then, the controller 220 implemented by a digital circuit receives the phase detection result V_pd1 and generates a control signal Vc1, thereby controlling the phase interpolator 232 to adjust the phase of the clock signal CLK to generate a phase-shifted clock signal CLK′. In this embodiment, the control signal Vc1 is a digital code generated based on the phase information of the input signal Din and the clock signal CLK, and the phase interpolator 232 uses the control signal Vc1 to compensate the phase error of the clock signal CLK to generate Phase shift clock signal CLK'. The control signal Vc1 is the frequency A slower low-speed signal, and the control signal Vc1 contains both frequency and phase information. In addition, the phase detector 210 also generates a phase control signal Vc3 to control the phase interpolator 240 to adjust the phase of the reference clock signal, thereby generating a phase-shifted reference clock signal as the auxiliary signal V_aux, wherein the phase control signal Vc3 can be based on the input signal Din and the clock The phase information of the signal CLK is generated (for example, the phase control signal Vc3 can be generated based on the phase detection result V_pd1). The phase control signal Vc3 can be a high-speed signal with a relatively fast frequency, which contains only phase information. Then, the phase detector 234 compares the phase of the phase-shifted clock signal CLK' with the phase of the auxiliary signal V_aux to generate a phase detection result V_pd2, where the phase detection result V_pd2 indicates the phases of the phase-shifted clock signal CLK' and the auxiliary signal V_aux Information (phase difference information). The loop filter 236 receives the phase detection result V_pd2 to generate a filtered signal Vc2. Finally, the oscillator 238 receives the filtered signal Vc2 and generates the clock signal CLK as the output clock signal of the CDR circuit 200.

The above operations of the phase detector 210, the controller 220, the phase interpolator 232, the phase detector 234, the loop filter 236, and the oscillator 238 can be regarded as the first path of the CDR circuit 200. Since the speed of the controller 220 is generally limited by the semiconductor process, the first path has a longer loop delay time, which may deteriorate the performance of the CDR circuit 200. In order to solve the problem of the long loop delay time of the first path, the phase detector 210, the phase interpolator 240, the phase detector 234, the loop filter 236, and the oscillator 238 form the second path of the CDR circuit 200. As shown in Figure 2, because the second path can be regarded as using the auxiliary signal V_aux to adjust the phase of the clock signal CLK, and the second path has a smaller delay time, it can effectively reduce the loop delay of the first path Time and the total delay time of the CDR circuit 200, and therefore the performance of the CDR circuit 200 can be improved.

FIG. 3 is a schematic diagram showing a CDR circuit 300 according to the third embodiment of the present invention. As shown in Figure 3, the CDR circuit 300 includes a phase detector 310, a controller 320, and a phase filter 330. Among them, the phase filter 330 includes a phase interpolator 332, a phase detector 334, a loop filter 336, an oscillator 338, and a phase interpolator 339. In addition, the phase detector 334 in the phase filter 330 may be replaced by a phase and frequency detector.

In the operation of the CDR circuit 300, the phase detector 310 receives the input signal Din and the clock signal CLK" to generate a phase detection result V_pd1, where the phase detection result V_pd1 indicates the phase information of the input signal Din and the clock signal CLK", that is, The clock signal CLK" is phase-lead or phase-lag relative to the input signal Din and/or the phase difference information between the two. Then, the controller 320 implemented by the digital circuit receives the phase detection result V_pd1 and generate a control signal Vc1, thereby controlling the phase interpolator 332 to adjust the phase of the clock signal CLK to generate a phase-shifted clock signal CLK'. In this embodiment, the control signal Vc1 is based on the input signal Din and the clock signal The digital code generated by the phase information of CLK, and the phase interpolator 332 uses the control signal Vc1 to compensate the phase error of the clock signal CLK to generate a phase-shifted clock signal CLK'. The control signal Vc1 is a low-speed signal with a slower frequency , And the control signal Vc1 contains both frequency and phase information. Then, the phase detector 334 compares the phase of the phase-shifted clock signal CLK' with the phase of the reference clock signal REF_CLK to generate a phase detection result V_pd2, where the phase detection result V_pd2 indicates the phase information (phase difference information) of the phase shift clock signal CLK' and the reference clock signal REF_CLK. The loop filter 336 receives the phase detection result V_pd2 to generate the filtered signal Vc2. The oscillator 338 receives the filtered signal Vc2 and generates the clock signal CLK is used as the output clock signal of the CDR circuit 300.

In addition, the phase detector 310 also generates an auxiliary signal V_aux to control the phase interpolator 339 to adjust the phase of the clock signal CLK, thereby generating a clock signal CLK", wherein the auxiliary signal V_aux can be generated according to the phase information of the input signal Din and the clock signal CLK" (For example, the auxiliary signal V_aux may be generated based on the phase detection result V_pd1) The auxiliary signal V_aux may be a high-speed signal with a faster frequency, It only contains phase information.

The above operations of the phase detector 310, the controller 320, the phase interpolator 332, the phase detector 334, the loop filter 336, the oscillator 338, and the phase interpolator 339 can be regarded as the first path of the CDR circuit 300. Since the speed of the controller 320 is generally limited by the semiconductor process, the first path has a longer loop delay time, which may deteriorate the performance of the CDR circuit 300. In order to solve the problem of the long loop delay time of the first path, the phase detector 310 and the phase interpolator 339 form the second path of the CDR circuit 300. In the embodiment shown in Figure 3, because the second path can be regarded as using the auxiliary signal V_aux to adjust the phase of the clock signal CLK, and the second path has a smaller delay time, the first path can be effectively reduced The loop delay time of the CDR circuit 200 as well as the overall delay time of the CDR circuit 200, and therefore the performance of the CDR circuit 300 can be improved.

Fig. 4 shows a flowchart of a signal processing method of a CDR circuit according to an embodiment of the present invention. With reference to the above-mentioned embodiment shown in Figs. 1 to 3, the flow is described as follows.

Step 400: Start.

Step 402: Compare the phase of the input signal with the phase of the clock signal to generate a phase detection result.

Step 404: Generate a low-frequency control signal through the controller according to the phase detection result, where the control signal includes frequency and phase information.

Step 406: Generate a high-frequency auxiliary signal that only includes phase information based on the phase detection result without going through the controller.

Step 408: Use a phase filter to receive the control signal and the auxiliary signal to generate a clock signal, where the phase filter has a first path for receiving the control signal and generating a clock signal, and the phase filter also has a second path to use The auxiliary signal reduces the total delay time of the CDR circuit.

In short, in the CDR circuit of the present invention, the CDR circuit has a first path and a second path, where the first path is a conventional loop with a higher delay time, and the second path has a smaller delay time to This effectively reduces the total delay time of the CDR circuit. Therefore, the performance of the CDR can be improved.

Those skilled in the art will readily recognize that various modifications and changes can be made to the device and method while maintaining the teachings of the present invention. Therefore, the above disclosure should be construed as being limited only by the scope of the attached patent application. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: CDR circuit

110: Phase detector

120: Controller

130: Phase filter

132: Phase Interpolator

134: Phase Detector

136: loop filter

138: Oscillator

Claims (11)

A clock and data recovery (CDR) circuit includes: a first phase detector for comparing the phase of an input signal with that of a clock signal to generate a first phase detection result; a controller, coupled to the first phase detector A device for generating a control signal according to the first phase detection result; and a phase filter, coupled to the controller, for receiving the control signal and an auxiliary signal to generate the clock signal, wherein the The auxiliary signal is generated according to the first phase detection result, wherein the control signal and the auxiliary signal have different frequencies. Such as the CDR circuit of claim 1, wherein the phase filter has a first path and a second path, the first path is used for receiving the control signal to generate the clock signal, and the second path is used for The auxiliary signal is used to adjust the phase of the clock signal to reduce the overall delay time of the CDR circuit. The CDR circuit of claim 1, wherein the phase filter includes: a phase interpolator for adjusting the phase of the clock signal with reference to the control signal, thereby generating a phase-shifted clock signal; and a second phase detector, Coupled to the phase interpolator for comparing the phase of the phase-shifted clock signal with the phase of the reference clock signal to generate a second phase detection result; a loop filter, coupled to the second phase detector , For receiving the second phase detection result to generate a filtered signal; and an oscillator, coupled to the loop filter, for receiving the filtered signal and the auxiliary signal to generate the clock signal. The CDR circuit of claim 3, wherein the auxiliary signal is a pulse signal indicating phase information of the input signal and the clock signal. The CDR circuit of claim 4, wherein the auxiliary signal is generated by the first phase detector, the auxiliary signal includes phase difference information between the input signal and the clock signal, and the frequency of the auxiliary signal is high The frequency of the control signal. The CDR circuit of claim 3, wherein the frequency of the clock signal generated by the oscillator is determined by both the filtered signal and the auxiliary signal. The CDR circuit of claim 1, wherein the phase filter includes: a first phase interpolator for adjusting the phase of the clock signal with reference to the control signal to generate a phase-shifted clock signal; and a second phase detection A loop filter, coupled to the first phase interpolator, for comparing the phase of the phase-shifted clock signal with the phase of the auxiliary signal to generate a second phase detection result; a loop filter, coupled to the A second phase detector receives the second phase detection result to generate a filtered signal; and an oscillator, coupled to the loop filter, receives the filtered signal to generate the clock signal. For example, the CDR circuit of claim 7, further comprising: a second phase interpolator, coupled to the first phase detector and the phase filter, and uses the phase control signal generated based on the first phase detection result to adjust The phase of the reference clock signal is used to generate a phase-shifted reference clock signal as an auxiliary signal. The CDR circuit of claim 1, wherein the phase filter includes: a first phase interpolator for adjusting the phase of the intermediate clock signal with reference to the control signal to generate a phase-shifted clock signal; and a second phase detector , Coupled to the first phase interpolator, for comparing the phase of the phase-shifted clock signal with the phase of the reference clock signal to generate a second phase detection result; a loop filter, coupled to the second A phase detector, configured to receive the second phase detection result to generate a filtered signal; an oscillator, coupled to the loop filter, configured to receive the filtered signal to generate the intermediate clock signal; and a second A phase interpolator, coupled to the oscillator and the first phase detector, is used to adjust the phase of the intermediate clock signal with reference to the auxiliary signal to generate the clock signal. The CDR circuit of claim 9, wherein the auxiliary signal is generated by the first phase detector, the auxiliary signal includes phase difference information between the input signal and the clock signal, and the frequency of the auxiliary signal is high The frequency of the control signal. A signal processing method for a clock and data recovery circuit (CDR) includes: comparing the phase of the input signal with the phase of the clock signal to generate a phase detection result; according to the phase detection result, a controller generates a low-frequency control signal, wherein The control signal includes frequency and phase information; a high-frequency auxiliary signal is generated according to the phase detection result, wherein the auxiliary signal includes phase information; and a phase filter is used to receive the control signal and the auxiliary signal to generate the The clock signal, Wherein, the phase filter has a first path and a second path, the first path is used to receive the control signal to generate the clock signal, and the second path uses the auxiliary signal to adjust the clock The phase of the signal to reduce the overall delay of the CDR circuit.

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