TWI744933B - Conductive wire structrue and manufacturing method thereof - Google Patents
Conductive wire structrue and manufacturing method thereof Download PDFInfo
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- 229910052581 Si3N4 Inorganic materials 0.000 description 4
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
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- 239000010937 tungsten Substances 0.000 description 3
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
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- 229910052799 carbon Inorganic materials 0.000 description 2
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
本發明是有關於一種半導體元件及其製造方法,且特別是有關於一種導線結構及其製造方法。The present invention relates to a semiconductor element and its manufacturing method, and more particularly to a wire structure and its manufacturing method.
隨著半導體技術的進步,元件的尺寸也不斷地縮小。當積體電路的積集度增加時,導線的關鍵尺寸(critical dimension)以及導線與導線之間的距離會隨著縮小。當導線的關鍵尺寸縮小時,會導致後續形成的接觸窗難以與導線進行對準,而降低接觸窗與導線之間的對準裕度(alignment margin)。此外,當導線與導線之間的距離縮小時,接觸窗容易同時連接到相鄰兩條導線而產生短路的問題。With the advancement of semiconductor technology, the size of components is also continuously shrinking. When the integration degree of the integrated circuit increases, the critical dimension of the wire and the distance between the wire and the wire will decrease. When the critical size of the wire is reduced, it will be difficult to align the subsequently formed contact window with the wire, and the alignment margin between the contact window and the wire will be reduced. In addition, when the distance between the wire and the wire is reduced, the contact window is likely to be connected to two adjacent wires at the same time, resulting in a short circuit problem.
本發明提供一種導線結構及其製造方法,其可提升接觸窗與導線之間的對準裕度,且可防止在相鄰兩條導線之間產生短路的問題。The present invention provides a wire structure and a manufacturing method thereof, which can improve the alignment margin between a contact window and the wire, and can prevent the problem of a short circuit between two adjacent wires.
本發明提出一種導線結構的製造方法,包括以下步驟。提供基底。在基底上形成導體層。藉由自對準雙重圖案化(self-alignment double patterning,SADP)製程在導體層上形成矩形環狀間隙壁。形成圖案化光阻層。圖案化光阻層暴露出矩形環狀間隙壁的第一部分與第二部分。第一部分與第二部分位在矩形環狀間隙壁的對角線上的兩個角落處。利用圖案化光阻層作為罩幕,移除第一部分與第二部分,而形成第一間隙壁與第二間隙壁。第一間隙壁與第二間隙壁為L形。移除圖案化光阻層。將第一間隙壁的圖案與第二間隙壁的圖案轉移至導體層,而形成L形的第一導線與L形的第二導線。The present invention provides a method for manufacturing a wire structure, which includes the following steps. Provide a base. A conductor layer is formed on the substrate. A rectangular ring-shaped spacer is formed on the conductor layer by a self-alignment double patterning (SADP) process. A patterned photoresist layer is formed. The patterned photoresist layer exposes the first part and the second part of the rectangular ring-shaped spacer. The first part and the second part are located at two corners on the diagonal of the rectangular ring-shaped spacer. The patterned photoresist layer is used as a mask, and the first part and the second part are removed to form a first gap wall and a second gap wall. The first spacer and the second spacer are L-shaped. Remove the patterned photoresist layer. The pattern of the first spacer and the pattern of the second spacer are transferred to the conductor layer to form an L-shaped first wire and an L-shaped second wire.
本發明提出一種導線結構,包括第一導線與第二導線。第二導線位在第一導線的一側。第一導線包括第一導線部與第一接墊部。第一導線部在第一方向上延伸,且具有第一端與第二端。第一接墊部連接於第一導線部的第一端。第二導線包括第二導線部與第二接墊部。第二導線部在第二方向上延伸,且具有第三端與第四端。第三端鄰近於第一端,且第四端鄰近於第二端。第二方向為第一方向的相反方向。第二接墊部連接於第二導線部的第四端。第一假想延伸部從第一導線部的第二端以遠離第一導線部的第一端的方式在第一方向上延伸。第二假想延伸部從第二導線部的第三端以遠離第二導線部的第四端的方式在第二方向上延伸。第一接墊部朝第二假想延伸部延伸但不與第二假想延伸部相交。第二接墊部朝第一假想延伸部延伸但不與第一假想延伸部相交。The present invention provides a wire structure including a first wire and a second wire. The second wire is located on one side of the first wire. The first wire includes a first wire portion and a first pad portion. The first wire portion extends in the first direction and has a first end and a second end. The first pad part is connected to the first end of the first wire part. The second wire includes a second wire portion and a second pad portion. The second wire portion extends in the second direction and has a third end and a fourth end. The third end is adjacent to the first end, and the fourth end is adjacent to the second end. The second direction is the opposite direction of the first direction. The second pad part is connected to the fourth end of the second wire part. The first imaginary extension portion extends from the second end of the first wire portion in a first direction away from the first end of the first wire portion. The second imaginary extension portion extends in the second direction from the third end of the second wire portion so as to be away from the fourth end of the second wire portion. The first pad portion extends toward the second imaginary extension portion but does not intersect the second imaginary extension portion. The second pad portion extends toward the first imaginary extension portion but does not intersect the first imaginary extension portion.
基於上述,在本發明所提出的導線結構的製造方法中,藉由自對準雙重圖案化製程、圖案化製程與圖案轉移製程形成L形的第一導線與L形的第二導線,因此可有效地簡化製程,以降低製程複雜性。此外,由上述方法所製作的L形的第一導線與L形的第二導線可增加用來與後續形成的接觸窗進行電性連接的面積,因此可有效地提高接觸窗與第一導線之間的對準裕度以及接觸窗與第二導線之間的對準裕度。此外,藉由上述方法可彈性調整第一導線與第二導線之間的距離,因此可防止因接觸窗同時連接到第一導線與第二導線所產生的短路問題。Based on the above, in the manufacturing method of the wire structure proposed in the present invention, the L-shaped first wire and the L-shaped second wire are formed by a self-aligned double patterning process, a patterning process, and a pattern transfer process. Effectively simplify the process to reduce the complexity of the process. In addition, the L-shaped first wire and the L-shaped second wire produced by the above method can increase the area for electrical connection with the contact window formed later, so that the contact window and the first wire can be effectively increased. And the alignment margin between the contact window and the second wire. In addition, the distance between the first wire and the second wire can be flexibly adjusted by the above method, so that the short circuit problem caused by the contact window being connected to the first wire and the second wire at the same time can be prevented.
此外,在本發明所提出的導線結構中,由於第一導線與第二導線分別具有第一接墊部與第二接墊部,因此可有效地提高接觸窗與第一導線之間的對準裕度以及接觸窗與第二導線之間的對準裕度。此外,由於第一接墊部朝第二假想延伸部延伸但不與第二假想延伸部相交,且第二接墊部朝第一假想延伸部延伸但不與第一假想延伸部相交,因此可防止因接觸窗同時連接到第一導線與第二導線所產生的短路問題。In addition, in the wire structure proposed by the present invention, since the first wire and the second wire respectively have a first pad portion and a second pad portion, the alignment between the contact window and the first wire can be effectively improved. The margin and the alignment margin between the contact window and the second wire. In addition, since the first pad portion extends toward the second imaginary extension portion but does not intersect the second imaginary extension portion, and the second pad portion extends toward the first imaginary extension portion but does not intersect the first imaginary extension portion, it can be Prevent the short circuit caused by the contact window being connected to the first wire and the second wire at the same time.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.
請參照圖1A與圖2A,提供基底100。基底100可為半導體基底,如矽基底。另外,所屬技術領域具有通常知識者可依照產品需求在基底100上形成半導體元件(如,電晶體)與介電層(未示出),於此省略其說明。1A and 2A, a
接著,在基底100上形成導體層102。導體層102可為單層結構或多層結構。舉例來說,導體層102可為包括導體層104與導體層106的多層結構,但本發明並不以此為限。導體層104例如是摻雜多晶矽。導體層106例如是金屬或金屬化合物,如鎢、氮化鎢、鋁、氮化鈦或銅。Next, a
然後,可在導體層102上形成硬罩幕層108。硬罩幕層108的例如是氮化矽或氧化矽。Then, a
接下來,請參照圖1A至圖1D與圖2A至圖2D,可藉由自對準雙重圖案化(SADP)製程在導體層102上形成矩形環狀間隙壁112a(請參照圖1D與圖2D)。舉例來說,可藉由自對準雙重圖案化將矩形環狀間隙壁112a形成在硬罩幕層108上,說明如下。Next, referring to FIGS. 1A to 1D and FIGS. 2A to 2D, a rectangular ring-
請參照圖1A與圖2A,可在導體層102上形成矩形的芯圖案110。芯圖案110的材料例如是碳、多晶矽、氧化矽或氮化矽。芯圖案110可藉由沉積製程、微影製程與蝕刻製程所形成。1A and 2A, a
請參照圖1B與圖2B,可在芯圖案110上共形地形成間隙壁材料層112。間隙壁材料層112的材料例如是氧化矽或氮化矽。間隙壁材料層112的形成方法例如是化學氣相沉積法或原子層沉積法。Referring to FIGS. 1B and 2B, a
請參照圖1C與圖2C,可對間隙壁材料層112進行蝕刻製程,而形成環繞芯圖案110的側壁的矩形環狀間隙壁112a。矩形環狀間隙壁112a可包括長邊部LP1、長邊部LP2、短邊部SP1與短邊部SP2。短邊部SP1連接於長邊部LP1的一端與長邊部LP2的一端。短邊部SP2連接於長邊部LP1的另一端與長邊部LP2的另一端。上述蝕刻製程例如是乾式蝕刻製程。1C and 2C, the
請參照圖1D與圖2D,可移除芯圖案110。當芯圖案110的材料為碳時,芯圖案110的移除方法例如是灰化法(ashing)。當芯圖案110的材料為多晶矽、氧化矽或氮化矽時,芯圖案110的移除方法例如是濕式蝕刻法。Please refer to FIG. 1D and FIG. 2D, the
此外,雖然自對準雙重圖案化製程是以上述方法為例來進行說明,但本發明並不以此為線。In addition, although the self-aligned double patterning process is described using the above-mentioned method as an example, the present invention does not take this as a line.
請參照圖1E與圖2E,形成圖案化光阻層114。圖案化光阻層114可藉由微影製程所形成。圖案化光阻層114暴露出矩形環狀間隙壁112a的第一部分P1與第二部分P2。第一部分P1與第二部分P2位在矩形環狀間隙壁112a的對角線上的兩個角落處。第一部分P1可包括部分短邊部SP1,且第二部分P2可包括部分短邊部SP2。第一部分P1中的部分短邊部SP1的長度可為短邊部SP1的總長度的三分之一至三分之二,且第二部分P2中的部分短邊部SP2的長度可為短邊部SP2的總長度的三分之一至三分之二。亦即,圖案化光阻層114可暴露出部分短邊部SP1與部分短邊部SP2,但本發明並不以此為限。在另一些實施例,第一部分P1更可包括部分長邊部LP1,且第二部分P2更可包括部分長邊部LP2。亦即,圖案化光阻層114更可暴露出部分長邊部LP1與部分長邊部LP2。Please refer to FIG. 1E and FIG. 2E to form a patterned
請參照圖1F與圖2F,利用圖案化光阻層114作為罩幕,移除第一部分P1與第二部分P2,而形成間隙壁S1與間隙壁S2。間隙壁S1與間隙壁S2為L形。第一部分P1與第二部分P2的移除方法例如是乾式蝕刻法。在一些實施例中,由於位在矩形環狀間隙壁112a上方的圖案化光阻層114的厚度較薄,因此在移除第一部分P1與第二部分P2的過程中,位在矩形環狀間隙壁112a上方的圖案化光阻層114可能會被移除而暴露出矩形環狀間隙壁112a。如此一來,在移除第一部分P1與第二部分P2的過程中,可能會同時移除原本位在圖案化光阻層114下方的部分矩形環狀間隙壁112a,而使得間隙壁S1的高度與間隙壁S2的高度低於矩形環狀間隙壁112a的高度(請參照圖2E與圖2F),但本發明並不以此為限。在另一些實施例中,在移除第一部分P1與第二部分P2的過程中,如果位在矩形環狀間隙壁112a上方的圖案化光阻層114未被移除,則間隙壁S1的高度與間隙壁S2的高度可約等於矩形環狀間隙壁112a的高度。1F and FIG. 2F, using the patterned
接著,移除圖案化光阻層114。圖案化光阻層114的移除方法例如是乾式去光阻法(dry stripping)或濕式去光阻法(wet stripping)。Next, the patterned
請參照圖1G與圖2G,將間隙壁S1的圖案與間隙壁S2的圖案轉移至硬罩幕層108與導體層102,而形成L形的硬罩幕層108a、L形的硬罩幕層108b、L形的導線W1與L形的導線W2。導線W1可包括導體層104a與導體層106a。導線W2可包括導體層104b與導體層106b。將間隙壁S1的圖案與間隙壁S2的圖案轉移至硬罩幕層108與導體層102的方法例如是利用間隙壁S1與間隙壁S2作為罩幕,移除部分硬罩幕層108與部分導體層102。部分硬罩幕層108與部分所述導體層102的移除方法例如是乾式蝕刻法。1G and 2G, the pattern of the spacer S1 and the pattern of the spacer S2 are transferred to the
然後,可移除移除間隙壁S1與間隙壁S2。在一些實施例中,在將間隙壁S1的圖案與間隙壁S2的圖案轉移至硬罩幕層108與導體層102的過程中,間隙壁S1與間隙壁S2可被逐漸消耗而移除,但本發明並不以此無限。在此情況下,硬罩幕層108a與硬罩幕層108b可能會因為作為蝕刻罩幕而被部分移除,而使得硬罩幕層108a的高度與硬罩幕層108b的高度低於硬罩幕層108的高度。舉例來說,硬罩幕層108a的高度與硬罩幕層108b的高度可比硬罩幕層108的高度低20%以下。在另一些實施例中,在將間隙壁S1的圖案與間隙壁S2的圖案轉移至硬罩幕層108與導體層102之後,若仍留有間隙壁S1與間隙壁S2,則可藉由濕式蝕刻法移除間隙壁S1與間隙壁S2。在此情況下,硬罩幕層108a的高度與硬罩幕層108b的高度可約等於硬罩幕層108的高度。Then, the spacer S1 and the spacer S2 can be removed. In some embodiments, in the process of transferring the pattern of the spacer S1 and the pattern of the spacer S2 to the
請參照圖1H與圖2H,可在導線W1與導線W2之間的基底100上形成介電層116。介電層116的材料例如是氧化矽。介電層116的形成方法例如是先形成覆蓋硬罩幕層108a與硬罩幕層108b的介電材料層(未示出),再對介電材料層進行化學機械研磨製程,以暴露出硬罩幕層108a與硬罩幕層108b。1H and FIG. 2H, a
請參照圖1I與圖2I,形成多個接觸窗118。接觸窗118分別電性連接至導線W1與導線W2。接觸窗118的材料例如是金屬材料,如鎢、鋁、銅。接觸窗118可藉由內連線製程所形成。在一些實施例中,更可在接觸窗118與導線W1之間以及接觸窗118與導線W2之間分別形成阻障層(未示出)。Referring to FIG. 1I and FIG. 2I, a plurality of
基於上述實施例可知,在導線結構10(請參照圖1G與圖2G)的製造方法中,藉由自對準雙重圖案化製程、圖案化製程與圖案轉移製程形成L形的導線W1與L形的導線W2,因此可有效地簡化製程,以降低製程複雜性。此外,由上述方法所製作的L形的導線W1與L形的導線W2可增加用來與後續形成的接觸窗118進行電性連接的面積,因此可有效地提高接觸窗118與導線W1之間的對準裕度以及接觸窗118與導線W2之間的對準裕度。此外,藉由上述方法可彈性調整導線W1與導線W2之間的距離,因此可防止因接觸窗118同時連接到導線W1與導線W2所產生的短路問題。Based on the above embodiment, it can be seen that in the manufacturing method of the wire structure 10 (please refer to FIGS. 1G and 2G), L-shaped wires W1 and L-shaped wires are formed by a self-aligned double patterning process, a patterning process, and a pattern transfer process. The wire W2 can effectively simplify the process to reduce the complexity of the process. In addition, the L-shaped wire W1 and the L-shaped wire W2 produced by the above method can increase the area for electrical connection with the
以下,藉由圖1G與圖2G來說明本實施例的導線結構10。在本實施例中,雖然導線結構10的形成方法是以上述方法為例進行說明,但本發明並不以此為限。Hereinafter, the
請參照圖1G與圖2G,導線結構10包括導線W1與導線W2。在本實施例中,導線結構10是以包括多對導線W1與導線W2為例,但本發明並不以此為限。只要導線結構10包括至少一對導線W1與導線W2,即屬於本發明所涵蓋的範圍。導線W2位在導線W1的一側。導線W1與導線W2的形狀可為L形。導線W1與導線W2可為單層結構或多層結構。導線W1可包括導體層104a與導體層106a。導線W2可包括導體層104b與導體層106b。1G and 2G, the
導線W1包括導線部WP1與接墊部EP1。導線部WP1在第一方向D1上延伸,且具有第一端T1與第二端T2。接墊部EP1連接於導線部WP1的第一端T1。接墊部EP1可垂直於導線部WP1。The wire W1 includes a wire portion WP1 and a pad portion EP1. The wire portion WP1 extends in the first direction D1 and has a first end T1 and a second end T2. The pad portion EP1 is connected to the first end T1 of the wire portion WP1. The pad portion EP1 may be perpendicular to the wire portion WP1.
導線W2包括導線部WP2與接墊部EP2。導線部WP2在第二方向D2上延伸,且具有第三端T3與第四端T4。第三端T3鄰近於第一端T1,且第四端T4鄰近於第二端T2。第二方向D2為第一方向D1的相反方向。接墊部EP2連接於導線部WP2的第四端T4。接墊部EP2可垂直於導線部WP2。接墊部EP1可平行於接墊部EP2。The wire W2 includes a wire portion WP2 and a pad portion EP2. The wire portion WP2 extends in the second direction D2 and has a third end T3 and a fourth end T4. The third end T3 is adjacent to the first end T1, and the fourth end T4 is adjacent to the second end T2. The second direction D2 is the opposite direction of the first direction D1. The pad portion EP2 is connected to the fourth end T4 of the wire portion WP2. The pad part EP2 may be perpendicular to the wire part WP2. The pad portion EP1 may be parallel to the pad portion EP2.
假想延伸部IE1從導線部WP1的第二端T2以遠離導線部WP1的第一端T1的方式在第一方向D1上延伸。假想延伸部IE2從導線部WP2的第三端T3以遠離導線部WP2的第四端T4的方式在第二方向D2上延伸。接墊部EP1朝假想延伸部IE2延伸但不與假想延伸部IE2相交。接墊部EP2朝假想延伸部IE1延伸但不與假想延伸部IE1相交。假想延伸部IE1與導線部WP1可具有相同的寬度。假想延伸部IE2與導線部WP2可具有相同的寬度。此外,假想延伸部IE1與假想延伸部IE2為假想的構件,實際上並不存在。假想延伸部IE1的目的是用以描述接墊部EP1與導線W2之間的配置關係,且假想延伸部IE2的目的是用以描述接墊部EP2與導線W1之間的配置關係。The imaginary extension portion IE1 extends in the first direction D1 from the second end T2 of the wire portion WP1 so as to be away from the first end T1 of the wire portion WP1. The imaginary extension portion IE2 extends in the second direction D2 from the third end T3 of the wire portion WP2 so as to be away from the fourth end T4 of the wire portion WP2. The pad portion EP1 extends toward the imaginary extension portion IE2 but does not intersect the imaginary extension portion IE2. The pad portion EP2 extends toward the imaginary extension portion IE1 but does not intersect the imaginary extension portion IE1. The imaginary extension portion IE1 and the wire portion WP1 may have the same width. The imaginary extension portion IE2 and the wire portion WP2 may have the same width. In addition, the imaginary extension portion IE1 and the imaginary extension portion IE2 are imaginary members and do not actually exist. The purpose of the imaginary extension IE1 is to describe the configuration relationship between the pad EP1 and the wire W2, and the purpose of the imaginary extension IE2 is to describe the configuration relationship between the pad EP2 and the wire W1.
此外,導線結構10的各構件的材料、形成方法與配置方式已於上述實施例中進行詳盡地說明,於此不再重複說明。In addition, the materials, forming methods, and configuration methods of the components of the
基於上述實施例可知,在導線結構10中,由於導線W1與導線W2分別具有接墊部EP1與接墊部EP2,因此可有效地提高接觸窗118與導線W1之間的對準裕度以及接觸窗118與導線W2之間的對準裕度。此外,由於接墊部EP1朝假想延伸部IE2延伸但不與假想延伸部IE2相交,且接墊部EP2朝假想延伸部IE1延伸但不與假想延伸部IE1相交,因此可防止因接觸窗118同時連接到導線W1與導線W2所產生的短路問題。Based on the above embodiment, it can be seen that in the
綜上所述,藉由上述實施例的導線結構及其製造方法,可提升接觸窗與導線之間的對準裕度,且可防止在相鄰兩條導線之間產生短路的問題。In summary, with the wire structure and manufacturing method of the above embodiment, the alignment margin between the contact window and the wire can be improved, and the problem of short circuit between two adjacent wires can be prevented.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.
10:導線結構
100:基底
102,104,104a,104b,106,106a,106b:導體層
108,108a,108b:硬罩幕層
110:芯圖案
112:間隙壁材料層
112a:矩形環狀間隙壁
114:圖案化光阻層
116:介電層
118:接觸窗
D1:第一方向
D2:第二方向
EP1,EP2:接墊部
IE1,IE2:假想延伸部
LP1,LP2:長邊部
P1:第一部分
P2:第二部分
S1,S2:間隙壁
SP1,SP2:短邊部
T1:第一端
T2:第二端
T3:第三端
T4:第四端
W1,W2:導線
WP1,WP2:導線部10: Wire structure
100:
圖1A至圖1G為本發明一實施例的導線結構的製造流程上視圖。 圖1H至圖1I為本發明一實施例的接觸窗的製造流程上視圖。 圖2A至圖2I為沿圖1A至圖1I中的I-I’剖面線與II-II’剖面線的剖面圖。 1A to 1G are top views of a manufacturing process of a wire structure according to an embodiment of the present invention. 1H to FIG. 1I are top views of a manufacturing process of a contact window according to an embodiment of the present invention. 2A to 2I are cross-sectional views taken along the I-I' section line and the II-II' section line in FIGS. 1A to 1I.
10:導線結構 10: Wire structure
100:基底 100: base
108a,108b:硬罩幕層 108a, 108b: hard mask layer
D1:第一方向 D1: First direction
D2:第二方向 D2: second direction
EP1,EP2:接墊部 EP1, EP2: Pad part
IE1,IE2:假想延伸部 IE1, IE2: imaginary extension
T1:第一端 T1: first end
T2:第二端 T2: second end
T3:第三端 T3: third end
T4:第四端 T4: Fourth end
W1,W2:導線 W1, W2: Wire
WP1,WP2:導線部 WP1, WP2: Lead wire part
Claims (10)
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| CN114512476A (en) * | 2022-02-17 | 2022-05-17 | 福建省晋华集成电路有限公司 | Semiconductor device and method of forming the same |
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| TWI502386B (en) * | 2009-11-09 | 2015-10-01 | Cadence Design Systems Inc | Method, system, and program product for routing an integrated circuit to be manufactured by sidewall-image transfer |
| TWI509442B (en) * | 2009-07-16 | 2015-11-21 | 卡登斯設計系統股份有限公司 | Method, system, and program product for routing routing of integrated circuits to be double-patterned |
| TW201715651A (en) * | 2015-10-23 | 2017-05-01 | 三星電子股份有限公司 | Logic semiconductor device |
| TWI657534B (en) * | 2016-11-29 | 2019-04-21 | 台灣積體電路製造股份有限公司 | Semiconductor process and method of forming a mask pattern |
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| TWI509442B (en) * | 2009-07-16 | 2015-11-21 | 卡登斯設計系統股份有限公司 | Method, system, and program product for routing routing of integrated circuits to be double-patterned |
| TWI502386B (en) * | 2009-11-09 | 2015-10-01 | Cadence Design Systems Inc | Method, system, and program product for routing an integrated circuit to be manufactured by sidewall-image transfer |
| TW201715651A (en) * | 2015-10-23 | 2017-05-01 | 三星電子股份有限公司 | Logic semiconductor device |
| TWI657534B (en) * | 2016-11-29 | 2019-04-21 | 台灣積體電路製造股份有限公司 | Semiconductor process and method of forming a mask pattern |
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| CN114512476A (en) * | 2022-02-17 | 2022-05-17 | 福建省晋华集成电路有限公司 | Semiconductor device and method of forming the same |
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