TWI641100B - Method for manufacturing semiconductor device - Google Patents

Abstract

A method of fabricating a semiconductor device includes the following steps. A substrate is provided, wherein the substrate has a memory region and a capacitance region. A plurality of word line structures are formed on the substrate of the memory region. A capacitor structure is formed on the substrate of the capacitor region. The word line structure and the capacitor structure each include a first dielectric layer on the substrate, a first conductor layer on the first dielectric layer, a second dielectric layer on the first conductor layer, and a second dielectric layer. a second conductor layer on the layer. Removing a second conductor layer adjacent to an edge of the memory region of the word line structure and simultaneously removing a portion of the second conductor layer of the capacitor structure to form an exposed portion of the second dielectric layer in the second conductor layer of the capacitor structure The groove.

Description

Semiconductor component manufacturing method

The present invention relates to a method of fabricating a semiconductor device.

As the process evolved into the nanometer era, the line width became smaller and smaller. When the line width dimension begins to be smaller than the wavelength of the exposure source, the light of the exposure source passes through the reticle to produce an optical proximity effect (OPE), which causes an error in the patterned photoresist and the pattern on the reticle. In a semiconductor process, when a word line structure is defined by a patterned photoresist, an optical proximity effect causes a width of a portion of an edge adjacent to the memory region to be larger than the rest of each word line structure. width.

The width of the word line structure adjacent to the edge of the memory region is large, so that adjacent word line structures are likely to be close to each other or even connected, causing the word line structures to interfere with each other, or even causing a word line structure to be bridged, and thus A problem with a short circuit. In a conventional process, before or after making other components, such as before making a capacitor structure, an additional mask is used to pattern the word line structures adjacent to the edges of the memory region to remove the word lines. The larger part of the structure. However, the additional etching process described above increases manufacturing costs and process steps.

The invention provides a method for fabricating a semiconductor device, which can avoid the problem that adjacent word line structures interfere with each other and short circuit, and can achieve the effects of saving manufacturing cost and reducing process steps.

A method of fabricating a semiconductor device of the present invention includes the following steps. A substrate is provided, wherein the substrate has a memory region and a capacitance region. A plurality of word line structures are formed on the substrate of the memory region. A capacitor structure is formed on the substrate of the capacitor region. The word line structure and the capacitor structure each include a first dielectric layer on the substrate, a first conductor layer on the first dielectric layer, a second dielectric layer on the first conductor layer, and a second dielectric layer. a second conductor layer on the layer. Removing a second conductor layer adjacent to an edge of the memory region of the word line structure and simultaneously removing a portion of the second conductor layer of the capacitor structure to form an exposed portion of the second dielectric layer in the second conductor layer of the capacitor structure The groove.

A method of fabricating a semiconductor device of the present invention includes the following steps. A substrate is provided having a memory region and a capacitance region. An isolation structure is formed in the substrate to define an active region. A first dielectric layer is formed on the substrate in the active region. A first conductor layer is formed on the first dielectric layer. A second dielectric layer is formed on the substrate. A second conductor layer is formed on the second dielectric layer. Performing a patterning process to remove a portion of the first dielectric layer, a portion of the first conductive layer, a portion of the second dielectric layer, and a portion of the second conductive layer in the memory region and the capacitor region to form a plurality of stripes in the memory region The word line structure and a capacitor structure is formed in the capacitor region. The extending direction of the word line structure is staggered with the extending direction of the isolation structure. Removing a second conductor layer adjacent to an edge of the memory region of the word line structure and simultaneously removing a portion of the second conductor layer of the capacitor structure to form an exposed portion of the second dielectric layer in the second conductor layer of the capacitor structure The groove.

In an embodiment of the invention, the first dielectric layer is, for example, an oxide layer.

In an embodiment of the invention, the first conductor layer is, for example, a polysilicon layer.

In an embodiment of the invention, the second dielectric layer is, for example, a composite layer composed of an oxide layer, a nitride layer and an oxide layer which are sequentially stacked.

In an embodiment of the invention, the second conductor layer is, for example, a polysilicon layer.

In an embodiment of the invention, the second conductor layer of the word line structure adjacent to the edge of the memory region and the portion of the second conductor layer of the capacitor structure are removed in the same etching process.

In an embodiment of the invention, in each of the word line structures described above, the width of the portion adjacent to the edge of the memory region is greater than the width of the remaining portion.

In an embodiment of the invention, in the adjacent word line structure described above, the second conductor layers in the portion adjacent to the edge of the memory region are connected to each other.

Based on the above, the fabrication method of the semiconductor device of the present invention can avoid the problem that adjacent word line structures are too close to each other or even bridge, thereby avoiding the problem that adjacent word line structures interfere with each other or even short circuit. In addition, the reticle for removing the second conductor layer adjacent to the edge of the memory region is integrated with the reticle for forming the trench of the capacitor structure on the same reticle, thereby saving manufacturing costs and process steps.

The above described features and advantages of the invention will be apparent from the following description.

FIG. 1A to FIG. 1D are schematic top views of a method of fabricating a semiconductor device according to an embodiment of the invention. 2A to 2D are schematic cross-sectional views taken along line A-A' of Figs. 1A to 1D, respectively. 3A to 3D are schematic cross-sectional views taken along line B-B' of Figs. 1A to 1D, respectively.

Referring to FIG. 1A, FIG. 2A, FIG. 3A simultaneously, a substrate 100 is provided, wherein the substrate 100 is, for example, a germanium substrate. Further, the substrate 100 has a memory region 100a and a capacitor region 100b. An isolation structure 102 is then formed in the substrate 100 to define the active area AA. The isolation structure 102 is, for example, a shallow trench isolation structure (STI). Next, a first dielectric layer 104 is formed on the substrate 100 in the active region AA. The first dielectric layer 104 is, for example, an oxide layer, and the formation method thereof is, for example, a thermal oxidation method.

Thereafter, a first conductor layer 106 is formed on the first dielectric layer 104. The first conductive layer 106 is, for example, a polysilicon layer, which is formed by, for example, forming a conductive material layer (not shown) covering the isolation structure 102 on the substrate 100 by chemical vapor deposition, and then planarizing the conductive material layer. Until the top surface of the isolation structure 102 is exposed.

Next, referring to FIG. 1B, FIG. 2B, and FIG. 3B, the isolation structure 102 is selectively etched back, and the partial isolation structure 102 is removed, so that the top surface of the isolation structure 102 is lower than the top surface of the first conductor layer 106. . Then, a second dielectric layer 108 is conformally formed on the substrate 100. In the present embodiment, the second dielectric layer 108 is formed by, for example, forming an oxide layer, a nitride layer, and an oxide layer on the substrate 100 by chemical vapor deposition. Moreover, in another embodiment, the second dielectric layer 108 can be a single layer of oxide layer. Then, a second conductor layer 110 is formed on the second dielectric layer 108. The second conductor layer 110 is, for example, a polycrystalline germanium layer, and is formed by, for example, a chemical vapor deposition method.

Next, referring to FIG. 1C, FIG. 2C, and FIG. 3C, a patterning process is performed to remove a portion of the first dielectric layer 104, a portion of the first conductor layer 106, and a portion of the second dielectric layer in the memory region 100a and the capacitor region 100b. The electrical layer 108 and a portion of the second conductor layer 110 form a plurality of word line structures 112 in the memory region 100a, and form a capacitor structure 114 in the capacitor region 100b, wherein the extension direction and isolation structure of the word line structure 112 The extension direction of 102 is staggered.

Furthermore, due to the optical proximity effect, in each word line structure 112 after the patterning process is performed, the width of the portion (end) adjacent to the edge of the memory region 100a is larger than the width of the remaining portion. In the present embodiment, after the patterning process, in the adjacent word line structure 112, there is a gap G between the portions (ends) adjacent to the edge of the memory region 100a, wherein the gap G exposes a portion of the isolation structure 102. When the width of the gap G (the distance between the portions of the adjacent word line structure 112 adjacent to the edge of the memory region 100a) is too small, adjacent word line structures 112 may be caused to interfere with each other. In particular, when the width of the gap G is equal to zero, that is, the portions adjacent to the edges of the memory region 100a in the adjacent word line structures 112 are connected to each other, a problem of short circuit is generated, as shown in FIG.

Next, referring to FIG. 1D, FIG. 2D, and FIG. 3D, the partial word line structure 112 and the partial capacitor structure 114 are etched to remove the second conductor layer of the word line structure 112 adjacent to the edge of the memory region 100a. 110, and at least a portion of the second conductor layer 110 of the capacitor structure 114 is removed to form a trench T exposing a portion of the second dielectric layer 108 in the second conductor layer 110 of the capacitor structure 114. In detail, the etching process removes the second conductor layer 110 adjacent to the edge of the memory region 100a until the second dielectric layer 108 is exposed, and after the etching process, on the isolation structure 102 adjacent to the edge of the memory region 100a. The top surface of the second conductor layer 110 is coplanar with the top surface of the second dielectric layer 108, resulting in the second conductor layer 110 on the isolation structure 102 adjacent the edge of the memory region 100a in the word line structure 112. The second conductor layer 110 is electrically isolated from the other portions of the word line structure 112, so that even if the width of the gap G is too small, the adjacent word line structures 112 do not interfere with each other or even cause a short circuit.

In addition, when the partial word line structure 112 is subjected to an etching process, a portion of the capacitor structure 114 is simultaneously etched to form a trench T in the capacitor structure 114 exposing a portion of the second dielectric layer 108, thereby eliminating the need to use different light. The cover is used to separately form the trench T and remove the end of the word line structure 112, thereby saving manufacturing costs and manufacturing steps. Additionally, forming the exposed portion of the second dielectric layer 108 trench T in the capacitor structure 114 enables the capacitor structure 114 to function to store charge. In the present embodiment, after the etching process of the word line structure 112 and the capacitor structure 114, the semiconductor device of the present invention is completed.

In another embodiment, during the etching process described above, the etch time may be moderately extended to remove all of the second conductor layer 110 in the word line structure 112 adjacent the edge of the memory region 100a. Since the second conductor layers 110 of the adjacent memory regions 100a that are close to each other or even connected in the steps described in FIG. 1C have been completely removed, the adjacent word line structures 112 are not interfered with each other or generated. bridging.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Base
100a‧‧‧ memory area
100b‧‧‧capacitor zone
102‧‧‧Isolation structure
104‧‧‧First dielectric layer
106‧‧‧First conductor layer
108‧‧‧Second dielectric layer
110‧‧‧Second conductor layer
112‧‧‧ character line structure
114‧‧‧Capacitor structure
AA‧‧‧Active Area
G‧‧‧ gap
T‧‧‧ trench

FIG. 1A to FIG. 1D are schematic top views of a method of fabricating a semiconductor device according to an embodiment of the invention. 2A to 2D are schematic cross-sectional views taken along line A-A' of Figs. 1A to 1D, respectively. 3A to 3D are schematic cross-sectional views taken along line B-B' of Figs. 1A to 1D, respectively. 4 is a top plan view of a method of fabricating a semiconductor device in accordance with another embodiment of the present invention.

Claims (10)

A method of fabricating a semiconductor device, comprising: providing a substrate, the substrate having a memory region and a capacitor region; forming a plurality of word line structures on the substrate of the memory region, and Forming a capacitor structure on the substrate, wherein the word line structure and the capacitor structure each include: a first dielectric layer on the substrate; a first conductor layer on the first dielectric layer; a second dielectric layer on the first conductor layer; and a second conductor layer on the second dielectric layer; and removing an edge of the word line structure adjacent to an edge of the memory region Depicting a second conductor layer and simultaneously removing a portion of the second conductor layer of the capacitor structure to form a trench exposing a portion of the second dielectric layer in the second conductor layer of the capacitor structure . The method of fabricating a semiconductor device according to claim 1, wherein the first dielectric layer comprises an oxide layer. The method of fabricating a semiconductor device according to claim 1, wherein the first conductor layer comprises a polysilicon layer. The method of fabricating a semiconductor device according to claim 1, wherein the second dielectric layer comprises a composite layer composed of an oxide layer, a nitride layer and an oxide layer which are sequentially stacked. The method of fabricating a semiconductor device according to claim 1, wherein the second conductor layer comprises a polysilicon layer. The method of fabricating a semiconductor device according to claim 1, wherein the second conductor layer of the word line structure adjacent to an edge of the memory region and the second portion of the capacitor structure are the second The conductor layer is removed in the same etching process. In the method of fabricating the semiconductor device of claim 1, in each of the word line structures, a portion adjacent to an edge of the memory region has a width greater than a width of the remaining portion. The method of fabricating a semiconductor device according to claim 1, wherein in the adjacent word line structure, the second conductor layers in a portion adjacent to an edge of the memory region are not connected to each other . A method of fabricating a semiconductor device, comprising: providing a substrate having a memory region and a capacitor region; forming an isolation structure in the substrate to define an active region; forming a first layer on the substrate in the active region a dielectric layer; a first conductor layer formed on the first dielectric layer; a second dielectric layer formed on the substrate; a second conductor layer formed on the second dielectric layer; and a patterning process Removing a portion of the first dielectric layer, a portion of the first conductor layer, a portion of the second dielectric layer, and a portion of the second conductor layer in the memory region and the capacitor region Forming a plurality of word line structures in the memory region, and forming a capacitor structure in the capacitor region, wherein an extension direction of the word line structure is staggered with an extending direction of the isolation structure; and removing the word a second conductor layer adjacent to an edge of the memory region of the meta-line structure and simultaneously removing a portion of the second conductor layer of the capacitive structure to the second conductor layer of the capacitive structure Forming the exposed portion of the second dielectric Trench. The method of fabricating a semiconductor device according to claim 9, wherein the second conductor layer of the word line structure adjacent to an edge of the memory region and the second portion of the capacitor structure are the second The conductor layer is removed in the same etching process.