TWI744915B - Semiconductor apparatus and readout method - Google Patents

Abstract

A semiconductor apparatus implementing a high speed data output and compensating a reset of a latch circuit is provided. A readout method of a NAND type flash memory includes: a pre-charge step pre-charging a bit line and a NAND string connected to the bit line through a readout node (SNS); a reset step resetting the latch circuit after the pre-charge; and a discharge step discharging the NAND string after the reset.

Description

Semiconductor device and reading method

The present invention relates to a semiconductor device including flash memory and the like, and particularly relates to continuous read operation of pages.

The NAND flash memory is equipped with a continuous read function (burst read function) that continuously reads multiple pages in response to external commands. The page buffer/readout circuit includes, for example, two latches. During continuous readout operation, while the data read from the array is held in one of the latches, the other latch can be output. Documents held by the device (for example, Patent Document 1, Patent Document 2, Patent Document 3, etc.). [Prior Art Literature] [Patent Literature]

[Patent Document 1] Japanese Patent No. 5323170 [Patent Document 2] Japanese Patent No. 5667143 [Patent Document 3] US Patent Application US2014/0104947A1

[The problem to be solved by the invention]

Figure 1 shows the schematic configuration of a NAND-type flash memory equipped with an on-chip error detection and correction (Error Checking and Correction, ECC) function. The flash memory includes: a memory cell array 10 containing NAND strings, a page buffer/readout circuit 20, a data transfer circuit 30, a data transfer circuit 32, and an error detection and correction circuit (hereinafter referred to as ECC circuit) 40, and input/output circuit 50. The page buffer/readout circuit 20 includes two latches L1 and L2 (one latch such as 4KB) that hold the read data or the input data to be programmed. The latch L1 and the latch L2 are respectively Including the first cache memory (cache) C0 and the second cache memory C1 (a cache memory such as 2KB).

Fig. 2 shows a timing chart when continuous reading of multiple pages is performed. Figure 2 shows an example where page P0 is used as the start address. The starting address can be chosen arbitrarily. First, perform an array read of page P0, and hold the data of page P0 in the first cache memory C0 and the second cache memory C1 (P0C0, P0C1) of the latch L1. Then, the data of the first cache memory C0 and the second cache memory C1 of the latch L1 are transferred to the first cache memory C0 and the second cache memory C1 of the latch L2, the first The data in the cache memory C0 and the second cache memory C1 is subjected to the ECC decoding operation in the ECC circuit 40, and when an error is detected, the first cache memory C0 and the second cache memory C0 and the second cache memory of the latch L2 are corrected. Cache the data stored in C1.

In continuous reading, the row address counter is automatically incremented, and the next page P1 is read. The read data is sent to the first cache C0 and the second cache C1 of the latch L1 . During this period, the data of the first cache C0 of the latch L2 is transmitted to the input/output circuit 50, and the data held by the input/output circuit 50 is output in synchronization with the external clock signal ExCLK supplied from the outside. Then, in synchronization with the external clock signal ExCLK, the input/output circuit 50 outputs the data of the second cache memory C1 of the latch L2, during which the data of the first cache memory C0 of the latch L1 is transferred To the latch L2, and the ECC process is executed by the ECC circuit 40.

While the data in the second cache memory C1 of the latch L1 is transferred to the latch L2, and the data in the first cache memory C0 of the latch L2 is output from the input/output circuit 50, the latch L2 The data in the second cache memory C1 of the latch L2 is processed by ECC. Then, while the data in the second cache memory C1 of the latch L2 is output from the input and output circuit 50, the next page P2 is read from the array and is The first cache memory C0 and the second cache memory C1 transferred to the latch L1, and the data of the first cache memory C0 is transferred to the latch L2 for ECC processing.

In this way, the data is output from the latch L2 while continuous reading of the pages of the memory cell array is performed. During the period, the ECC processing of the second cache memory C1 is performed during the period when the data of the first cache memory C0 is output. , ECC processing of the first cache memory C0 is performed during the output of the data of the second cache memory C1.

Here, the readout of the array operates using the internal clock signal according to the determined timing, on the other hand, the data output operates according to the external clock signal ExCLK that is asynchronous with the internal clock signal. Therefore, in the continuous read operation, there is a restriction shown in the following equation (1). tARRAY＋tECC＜tDOUT…（1） Here, tARRAY is the time required to read the selected page from the memory cell array, tECC is the time required to perform ECC processing on 1/2 page, and tDOUT is the time required to output all the data of one page. tARRAY and maximum tECC (the maximum time required for the calculation of ECC decoding and data correction) are fixed times, and tDOUT is calculated based on the frequency of the external clock signal ExCLK.

In order to read a large amount of data in a short time, the frequency of the external clock signal ExCLK needs to be increased. In this case, as shown in equation (1), the time of tARRAY + tECC must be shortened. On the other hand, in the readout operation, the latch L1 needs to be reset in order to more accurately receive the charge from the readout node, and the reset is performed before the precharge period of the bit line. In the continuous read operation, the reset of the latch L1 must be after the data of the latch L1 is transferred to the latch L2. That is, the reset of the latch L1 must be performed after the data of the latch L1 is transferred to the latch L2 and before the precharge period for reading the bit line of the next page. Therefore, if the start timing of tARRAY is to be advanced, it may not be possible to sufficiently ensure the time to reset the latch L1. As shown in FIG. 2, if the data of the second cache C1 of page P2 of the latch L1 is transferred to the latch L2, the time is ts, from the start timing of reading the array of page P3 to the bit The period until the precharging of the line is completed is tp, and the latch L1 must be reset during the period tx. If the read start timing of the next page is advanced, the period tx is further shortened, and it may not be possible to compensate for the reset of the latch L1.

The object of the present invention is to solve the above-mentioned existing problems and provide a semiconductor device and a readout method that realizes high-speed data output and compensates for resetting of a latch circuit. [Technical means to solve the problem]

The reading method of the NAND flash memory of the present invention includes: a precharging step, precharging a bit line and a NAND string connected to the bit line via a read node; and a reset step, after the precharging The node of the latch circuit is electrically connected to the reference potential via the read node, and the latch circuit is reset; and the discharging step is to discharge the NAND string after the reset. Furthermore, the read method of the NAND flash memory of the present invention includes: a precharging step, precharging the bit line and the NAND string connected to the bit line via the read node; and a reset step, in the NAND During the discharge period of the string, the node of the latch circuit is electrically connected to the reference potential via the sense node, and the latch circuit is reset.

In an embodiment of the present invention, the precharging step includes: generating a precharging voltage at a voltage supply node; electrically connecting the voltage supply node to the readout node via a first selection transistor; A transistor electrically connects the read node to a bit line, and the reset step includes: generating the reference voltage at the voltage supply node; electrically connecting the voltage supply node via the first selection transistor In the latch circuit; the read node is electrically isolated via the second transistor.

In an embodiment of the present invention, each of the steps is performed in continuous reading of pages. In an embodiment of the present invention, the continuous reading of the page includes: holding the data read from the selected page of the memory cell array in the latch circuit, and transmitting the data held by the latch circuit to After the other latch circuits, the data read from the next selected page is held in the latch circuit; the data held by the other latch circuits are continuously output to the outside in synchronization with an external clock signal. In an embodiment of the present invention, the continuous readout of the page further includes performing error detection and correction (ECC processing) on the data of the first part of the other latch circuit, removing the second part of the data through the ECC The processed data is output to the outside, and while the ECC processed data of the first part is output to the outside, ECC processing is performed on the second part of the data. In an embodiment of the present invention, it includes: after outputting the ECC processed data of the first part of the other latch circuit to the outside, transmitting the data of the next selected page of the first part of the latch circuit To the first part of the other latch circuit; after outputting the ECC processed data of the second part of the other latch circuit to the outside, the next selection page of the second part of the latch circuit The data is sent to the second part of the other latch circuit. In an embodiment of the present invention, the continuous readout is the first continuous readout with the restriction expressed by tARRAY+tECC<tDOUT (the data in the first part and the second part are 1/2 pages of data, respectively, and tARRAY is read The time required to output the selected page, tECC is the time required to perform ECC processing on 1/2 page, and tDOUT is the time required to output all the data on one page). In an embodiment of the present invention, the continuous readout is a second continuous readout (the data of the first part and the second part are respectively For 1/2 page of data, tARRAY is the time required to read the selected page, tECC is the time required to perform ECC processing on 1/2 page, tDOUT is the time required to output all the data on one page, tDOUT (1/ 2 pages) is the time required to output 1/2 page of data). In one embodiment of the present invention, the second continuous readout has an earlier readout timing of the selected page of the memory cell array than the first continuous readout.

The semiconductor device of the present invention includes: a NAND-type memory cell array; a readout unit for reading out data from the selected page of the memory cell array; and an output unit for outputting the data read by the readout unit to the outside, so The readout unit includes a page buffer/readout circuit connected to the memory cell array via a bit line. When the readout unit performs continuous readout of the page, the readout unit discharges the NAND string during the precharge period of the bit line. During this period, the latch circuit included in the page buffer/readout circuit is reset. Furthermore, the semiconductor device of the present invention includes: a NAND-type memory cell array; a readout unit for reading data from a selected page of the memory cell array; and an output unit for outputting the data read by the readout unit to the outside, The readout unit includes a page buffer/readout circuit connected to the memory cell array via a bit line. The readout unit performs continuous readout of the page and precharges the NAND string on the bit line. The latch circuit included in the page buffer/readout circuit is reset during the discharge period.

In an embodiment of the present invention, the page buffer/readout circuit includes: a voltage supply node, a readout node, a latch circuit, and a first circuit connected between the voltage supply node and the readout node. The selection transistor, the second selection transistor connected between the readout node and the bit line, and the third selection transistor connected between the readout node and the latch circuit, make the The first selection transistor and the third selection transistor are turned on, so that the second selection transistor is non-conductive, and the latch circuit is electrically connected to the reference potential of the voltage supply node, and the latch circuit Perform a reset. In an embodiment of the present invention, the readout unit makes the first selection transistor and the second selection transistor conductive, makes the third selection transistor non-conductive, and supplies the voltage to the node The voltage is precharged to the bit line. In one embodiment of the present invention, when the reading unit performs continuous reading of pages, the output unit continuously outputs the read data in synchronization with an external clock signal. In an embodiment of the present invention, the page buffer/readout circuit further includes another latch circuit that receives the data held by the latch circuit, and the readout unit performs continuous readout when outputting During the data period of the other latch circuit, the data read from the next selected page of the memory cell array is held in the latch circuit. In an embodiment of the present invention, the semiconductor device further includes an ECC circuit that performs error detection and correction of data. When the readout component performs continuous readout, the ECC circuit is used to detect and correct the other latch circuits. During the ECC processing of the data held in the first part, the ECC processed data held in the second part of the other latch circuit is output. [Effects of the invention]

According to the present invention, the latch circuit included in the page buffer/readout circuit is reset between the precharge period of the bit line and the discharge period of the NAND string. Therefore, it is possible to achieve high-speed data output and improve the latch The reset of the circuit is compensated.

Next, the embodiments of the present invention will be described in detail with reference to the drawings. The semiconductor device of the present invention is, for example, a NAND-type flash memory or a microprocessor, microcontroller, logic, application specific integrated circuits (ASIC) embedded in such a flash memory, image or sound Processors for processing, processors for processing signals such as wireless signals, etc. In the following description, a NAND flash memory is exemplified. In one embodiment, in order to achieve compatibility with NOR flash memory, NAND flash memory is equipped with a serial peripheral interface (Serial Peripheral Interface, SPI), which can be synchronized with an external clock signal Continuous readout of multiple pages. [Example]

FIG. 3 is a diagram showing the structure of a NAND flash memory according to an embodiment of the present invention. The flash memory 100 of this embodiment includes: a storage cell array 110 in which a plurality of storage cells are arranged in a matrix; an input and output circuit 120, which is connected to an external input and output terminal, and responds to an external clock signal ExCLK, and reads Data is output to the outside, or taken in from the external input; ECC circuit 130, which performs symbol generation of the data to be programmed or error detection and correction of the read data; address register 140, through the input and output circuit 120 receives address data; the controller 150 controls each part based on the command data received via the input and output circuit 120 or the control signal applied to the terminal; the word line selection circuit 160, The address register 140 receives the row address information Ax, decodes the row address information Ax, and performs block selection or word line selection based on the decoding result; the page buffer/readout circuit 170 holds The data read by the page selected by the free word line selection circuit 160, or the data to be programmed to the selected page is maintained; the column selection circuit 180 receives the column address information Ay from the address register 140, and the column address information Ay decodes, and based on the decoded results, performs column selection in the page buffer/readout circuit 170, etc.; and an internal voltage generating circuit 190 generates various voltages required for data reading, programming, and erasing. (Write voltage Vpgm, pass voltage Vpass, read pass voltage Vread, erase voltage Vers, etc.).

The memory cell array 110 has, for example, m memory blocks BLK(0), BLK(1),..., BLK(m-1) arranged in the column direction. A plurality of NAND strings are formed in one storage block, and the NAND strings are formed by connecting a plurality of storage cells in series. As shown in FIG. 4, one NAND string NU includes a plurality of storage cells MCi (i=0, 1, ..., 31) connected in series, a bit line side selection transistor TD, and a source line side selection transistor TS. The drain of the bit line side selection transistor TD is connected to a corresponding bit line GBL, and the source of the source line side selection transistor TS is connected to the common source line SL. The control gate of the memory cell MCi is connected to the word line WLi, and the gates of the bit line side selection transistor TD and the source line side selection transistor TS are respectively connected to the selection gate line SGD and the selection gate line SGS. The word line selection circuit 160 selects a block or word via the selection gate line SGD, the selection gate line SGS, and the source line side selection transistor TS to drive the bit line side selection transistor TD based on the row address information Ax.

The NAND string can be formed two-dimensionally on the surface of the substrate or three-dimensionally formed on the surface of the substrate. In addition, the storage unit can be either a single level cell (SLC) type that stores one bit (binary data), or a multi-level cell (MLC) type that stores multiple bits.

The configuration of the bit line selection circuit is shown in FIG. 5. FIG. 5 illustrates one page buffer/readout circuit 170 shared by one even bit line GBLe and one odd bit line GBLo, and a bit line selection circuit 200 connected thereto.

The bit line selection circuit 200 includes: a transistor BLSe for selecting an even bit line GBLe, a transistor BLSo for selecting an odd bit line GBLo, and a transistor for connecting the virtual power supply VIRPWR to the even bit line GBLe YBLe, a transistor YBLo used to connect the virtual power supply VIRPWR to the odd bit line GBLo, a NAND string is connected between the even bit line GBLe and the source line SL, and between the odd bit line GBLo and the source line SL There are NAND strings connected between them. For example, in the read operation, mask read is performed, when the even bit line GBLe is selected, the odd bit line GBLo is not selected, and when the odd bit line GBLo is selected, the even bit line GBLe is not selected. The unselected bit line is connected to the ground (Ground, GND) level via the virtual power supply VIRPWR.

The configuration of the page buffer/readout circuit 170 is shown in (A) of FIG. 6. Fig. 6(A) shows a page buffer/readout circuit. For the sake of convenience, it is assumed that the signal applied to the gate of the transistor represents the transistor. The page buffer/readout circuit 170 includes two latches L1 and L2. A transfer gate (transistor CACHE) is connected between the latch L1 and the latch L2, and the transfer gate can be turned on. Perform bidirectional data transmission from the latch L1 to the latch L2 or from the latch L2 to the latch L1.

The latch L1 includes a pair of cross-coupled inverters. The node SLR1 of the latch L1 is connected to the common source/drain (S/D) of the transistor BLCD1 and the transistor DTG, and the node SLS1 is connected to the determination circuit 210 . The determination circuit 210 determines, for example, whether Program Verify or Erase Verification is qualified. In programming verification or the like, when the node SLR1 is selectively charged to Vdd from the voltage supply node V2, or the node SLR1 is selectively discharged to GND, the transistor DTG is turned on. Furthermore, the latch L1 can short-circuit the node SLR1 and the node SLS1 through the transistor EQ.

The node SLR1 and the node SLS1 of the latch L1 are respectively connected to the node SLS2 and the node SLR2 of the latch L2 via the transistor CACHE. The node SLR2 of the latch L2 is connected to the sense node SNS via the transistor BLCD2, and the node SLS2 is connected to the transistor RESET2. When the latch L2 is reset, the transistor RESET2 is turned on. In addition, the node SLS2 and the node SLR2 are connected to the differential sense amplifier SA via the data line DL and the data line /DL, and the output of the differential sense amplifier SA is connected to the input/output circuit 120.

A transistor VG and a transistor REG are connected in series between the voltage supply node V2 and the read node SNS, and the gate of the transistor VG is connected to the S/D of the transistor DTG. The voltage supply node V1 is connected to the sense node SNS via the transistor BLPRE. As described later, the voltage supply node V1 supplies the internal supply voltage Vdd when the bit line is precharged, and supplies the GND potential when the latch L1 is reset. A transistor BLCN and a transistor BLCLAMP are connected in series between the sense node SNS and the node BLS of the bit line selection circuit 200.

The circuit configuration of one inverter constituting the latch L1 is shown in (B) of FIG. 6. The inverter includes four transistors connected in series, namely P-type transistor PT1, P-type transistor PT2, N-type transistor NT1, and N-type transistor NT2. Each gate of NT2 inputs a latch enable signal LAT1 and a latch enable signal /LAT1 respectively, and the voltage of the common gate input node SLS1/SLR1 of the transistor PT2 and the transistor NT1 is input. When the latch enable signal LAT1 is at the H level, the inverter can operate. When the latch enable signal LAT1 is at the L level, the transistor PT2 and the transistor NT1 are in a tri-state state separated from the internal supply voltage Vdd and GND , Can reset the inverter. The reset of the latch L1 is performed by using a current path passing through the sense node SNS, so when the sense node SNS is free, that is, when the sense node SNS is not adversely affected, the reset is performed.

The word line selection circuit 160 and the column selection circuit 180 (refer to FIG. 3) select the reading start position of the data in the page according to the row address information Ax and the column address information Ay, or when the row address and column position are not used In the case of an address, the data is automatically read from the beginning of the page. Furthermore, the word line selection circuit 160 and the column selection circuit 180 may include a row address counter and a column address counter that increment the row address and the column address in response to a clock signal.

In the read operation of the flash memory, a certain positive voltage is applied to the bit line, a certain voltage (for example, 0V) is applied to the selected word line, and the pass voltage Vpass (for example, 4.5V) is applied to the non-selected word line. The selection gate line SGD and the selection gate line SGS are applied with a positive voltage (for example, 4.5V), the bit line side selection transistor TD and the source line side selection transistor TS are turned on, and 0V is applied to the common source line. In the programming operation, a high-voltage programming voltage Vpgm (15V-20V) is applied to the selected word line, an intermediate potential (for example, 10V) is applied to the non-selected word line, and the bit line side selection transistor TD is turned on. The source line side selection transistor TS is turned off, and a potential corresponding to the data of "0" or "1" is supplied to the bit line. In the erasing operation, 0V is applied to the selected word line in the block, and a high voltage (for example, 20V) is applied to the P-well, and the floating gate (floating gate) electrons are extracted to the substrate to erase in units of blocks data.

Next, the continuous read operation of multiple pages of the flash memory according to this embodiment will be described. When the controller 150 receives a page continuous read operation command via the input and output circuit 120, the controller 150 controls the continuous read operation of multiple pages from the start address. When the controller 150 receives the command to end the continuous read operation When commanded, the continuous reading of the page ends at the end address. In the continuous page read operation, as described in FIGS. 1 and 2, while the data is output from the latch L2, the data read from the selected page of the memory cell array is transferred to the latch L1. The data transfer from the latch L1 to the latch L2 is not in units of 1 page, but divided into 1/2 pages (the first cache memory or the second cache memory). While the data in one of the caches of L2 is transmitted to the input/output circuit 120, the ECC circuit 130 processes the data of the other cache of the latch L2. The data transmitted to the input/output circuit 120 is output from the external input/output terminal to the outside in synchronization with the external clock signal ExCLK (for example, rising edge and falling edge). The data reading from the storage cell array and the data transmission from the latch L1 to the latch L2 are based on the internal clock signal. The data transmission between the latch L2 and the input/output circuit 120 comes from the input/output circuit The data output of 120 is based on the external clock signal ExCLK. The data transmission between the latch L2 and the ECC circuit 130 and the operation of the ECC circuit are based on other internal clock signals or the clock obtained by dividing the external clock signal ExCLK. Signal to proceed.

When the selected page of the memory cell array is read, the read node SNS reads the potential of the selected bit line, and then the charge of the read node SNS is transferred to the node SLR1 of the latch L1 via the transistor BLCD1. For the latch L1, if the transferred charge is greater than the threshold value, it is determined as data "1", and if it is less than the threshold value, it is determined as data "0", and the data is retained. The latch L1 resets the potential of the node SLR1 to the GND level in order to correctly reflect the charge transferred from the sense node SNS. When the latch L1 is reset, the voltage supply node V1 is converted to GND, the transistor BLCD1 and the transistor BLPRE are turned on, and the node SLR1 is electrically connected to the voltage supply node V1.

In the continuous reading of the existing flash memory, the reset of the latch L1 is performed before the precharging of the bit line when the next page is read. However, the reset of the latch L1 must be performed after the data of the latch L1 is transferred to the latch L2. As the data output speeds up, it may not be possible to sufficiently secure the time for the reset of the latch L1 . In order to avoid this problem, in the continuous read operation of the page in this embodiment, the reset of the latch L1 is performed after the precharging of the bit line ends and before the discharge of the NAND string cells starts.

Fig. 7 shows a timing chart when the latch L1 is reset. The precharging of the bit line is performed in the same way as in the past, and therefore it is not shown in detail here, but it is performed as follows. First, the voltage supply node V1 is converted into the supply voltage Vdd, the transistor BLPRE is turned on, and the sense node SNS is charged to the Vdd level. In addition, the transistor BLCLAMP and the transistor BLCN are turned on, and the node BLS is charged to VCLMP1. It is in the relationship of Vdd≧VCLMP1. At this time, the transistor BLCD1, the transistor BLCD2, and the transistor REG are made non-conducting. Furthermore, the transistor BLSe is turned on (here, it is assumed that the even-numbered bit line GBLe is selected), and the node BLS is electrically connected to the even-numbered bit line GBLe. The bit line side selection transistor TD of the NAND string connected to the even-numbered bit line GBLe is turned on, the source line side selection transistor TS is turned off, and a pass voltage is applied to the selected page and the non-selected page. Thus, the even-numbered bit line GBLe is precharged with the clamp cell voltage VCLMP1. On the other hand, the non-selected odd-numbered bit line GBLo is electrically connected to the GND of the virtual power supply VIRPWR via the transistor YBLo.

After the precharging of the bit line ends, the latch L1 is reset. During the reset period, the transistor BLPRE, the transistor BLCN, and the transistor BLCLAMP are in a conducting state. As shown in FIG. 7, at time t1, the transistor BLSe is made non-conducting, and the even bit line GBLe is electrically separated from the page buffer/readout circuit 170. Next, at time t2, the voltage supply node V1 is switched to GND. As a result, the sense node SNS drops to the GND level from the supply voltage Vdd, and the nodes TOBL and the node BLS drop to the GND level from the clamp cell voltage VCLMP1.

Next, at time t3, the latch enable signal LAT1 for resetting the latch L1 is converted from the H level to the L level, and the latch L1 is placed in a resettable state. Next, at time t4, the transistor EQ is turned on for a certain period of time, and after the nodes SLR1 and SLS1 are short-circuited at the same potential, at time t5, the transistor BLCD1 is turned on for a certain period of time. As a result, the charge of the node SLR1 is discharged to the GND of the voltage supply node V1 via the sense node SNS, and the resetting of the latch L1 is completed.

After the reset of the latch L1, recovery of the read node SNS and the like is performed. That is, the sense node SNS, the node TOBL, and the node BLS are recharged, and the voltage of these nodes is restored to the precharge state before the reset of the latch L1. At time t6, the voltage supply node V1 is converted from GND to the supply voltage Vdd. As a result, the sense node SNS is recharged to Vdd, and the nodes TOBL and the node BLS are recharged to the clamp cell voltage VCLMP1. Next, at time t7, the transistor BLSe is turned on, and the even-numbered bit line GBLe is electrically connected to the page buffer/readout circuit 170.

The discharging and reading of the NAND string performed after the reset of the latch L1 is performed in the same manner as in the past (not shown in the figure). That is, during the discharge of the NAND string, the transistor BLSe is made non-conductive, the source line side selection transistor TS of the NAND string is made conductive, and the NAND string is electrically connected to the source line SL. Furthermore, the gate voltage for generating the clamp cell voltage VCLMP2 at the node TOBL is applied to the transistor BLCLAMP. VCLMP1>VCLMP2. Then, by turning on the transistor BLSe for a certain period of time, the read node SNS displays the potential corresponding to the data "0" and the data "1" of the selected memory cell. If the memory cell is selected to hold the data "0", the potential of the bit line will not be discharged to the source line SL. Therefore, the potential of the sense node SNS hardly changes. However, if the memory cell is selected to hold the data "1" , The potential of the bit line is discharged to the source line SL, and the potential of the sense node SNS decreases. In this way, the read node SNS senses the charges corresponding to the data "0" and the data "1" of the selected storage cell. Then, the charge sensed by the sense node SNS is transferred to the node SLR1 of the latch L1 via the transistor BLCD1.

In this embodiment, since the reset of the latch L1 is performed between the precharge period of the bit line and the discharge period of the NAND string, the reset of the latch L1 can be guaranteed, and the latch L1 can be improved. The reliability of the data retention. Furthermore, just after the data of the latch L1 is transferred to the latch L2, the array readout can be started immediately.

Next, the continuous reading of the improved page to which the reset of the latch L1 is applied based on the present embodiment will be described. FIG. 8 is a timing chart when continuous reading of an improved page is performed. Fig. 8 shows an example in which page P0 is used as the start address. The starting address can be arbitrarily selected. tp is the period from the start timing of the array read to the completion of the precharging of the bit line, and tx is the period required for resetting the latch L1. As shown in FIG. 8, the substantial continuous reading using the latch L1 and the latch L2 starts from the reading of the page P2, and the start timing of the array reading of the page P2 is earlier than the conventional time shown in FIG. 2. In the continuous read shown in FIG. 2, the start timing of the array read of the page P2 is the time point when the transfer of the data (P1C1) of the page P1 from the latch L1 to the latch L2 ends. That is, after the latch L2 holds the data of the page P1, the data of the next page P2 is transferred to the latch L1.

In contrast, in the improved continuous read, the start timing of the array read of page P2 and the data (P1C0) of page P1 of the first cache memory C0 of the latch L1 are transferred to the latch L2 The timing is equal. In this way, even if the timing of the array read of page P2 is advanced, the array read actually requires a certain amount of time. If the high-speed external clock signal ExCLK is used to speed up the continuous read time, the read from the array At the point in time when the data of page P2 is transferred to the latch L1, the transfer of the data (P1C1) from the latch L1 to the page P1 of the latch L2 has been completed. In addition, since the reset of the latch L1 is performed during the array read period, even if the start timing of the array read is advanced, it will not have any effect on the reset of the latch L1.

In the improved continuous readout, the array readout time tARRAY is defined by the start timing of the array readout and the end timing of the array readout. The end timing of the array read of page P2 is the start timing of the array read of the next page P3. When the pages of page P2, page P3, page P4... are continuously read, the array read time tARRAY is similarly continuous.

By advancing the read start timing of the memory cell array in the improved continuous read operation, the limitation of the equation (1) of the conventional continuous read operation is alleviated as in the equation (2), and the high speed can be used. The frequency of the data output of the external clock signal ExCLK. tARRAY＜tDOUT (1 page) tECC＜tDOUT（1/2 page）…（2）

That is, as long as the following restrictions are met, that is, the time tDOUT to output one page of data is greater than the array read time tARRAY, and the time tDOUT to output 1/2 page of data is greater than the time tECC for ECC processing, it can be achieved compared to the past. Speed up continuous reading. In FIG. 8, the following situation is illustrated: compared with the array read time tARRAY of page P2, the time of outputting the data of the second cache of page P0 and the time of outputting the data of the first cache of page P1 The total output time tDOUT of the page P2 is large, and the array read time tARRAY of the page P2 is from the point in time when the data of the first cache C0 of the page P1 is transferred from the latch L1 to the latch L2 to Start to transfer the data of the first cache memory C0 of the next page P2 from the time point when the latch L1 is transferred to the latch L2; perform ECC with the data of the first cache memory C0 of the latch L2 Compared with the processing time tECC, the time tDOUT for outputting the data of the second cache C1 of the latch L2 is greater.

In the improved continuous read operation, the timing to start the reset of the latch L1 is after the precharging of the bit line is completed. If the period before setting is set to tp, not only equation (2) but also the restriction of equation (3) will be added. That is, the data of the latch L1 needs to be transferred to the latch L2. tDOUT（1/2 page）＜tp…（3）

However, since the precharge period of the bit line is sufficiently long, as long as the equations (2) and (3) are satisfied, the improved continuous reading speed shown in FIG. 8 can be achieved.

In this way, in the improved continuous read operation, the reset of the latch L1 can also be ensured and the speed of the read data can be achieved.

Next, another embodiment of the present invention will be described. In the described embodiment, the reset of the latch L1 is performed between the precharge operation of the bit line and the discharge operation of the NAND string, but in the other embodiment, the resetting of the latch L1 is performed during the discharge operation of the NAND string. Reset of latch L1.

As described above, the reset of the latch L1 can be implemented as long as the sensing node is in a free state that is not affected by others. During the discharge operation period of the NAND string, the transistor BLSe is non-conductive, and the sense node SNS is in a state of being electrically isolated from the bit line. Therefore, the reset operation of the latch L1 shown in time t2 to time t6 shown in FIG. 7 and the discharge operation of the NAND string can be performed in parallel in time.

According to this embodiment, the reset of the latch L1 is performed in parallel during the discharge period of the NAND string, and the reset of the latch L1 is performed between the precharge operation of the bit line and the discharge operation of the NAND string. In comparison, the array readout time tARRAY can be shortened in fact, and continuous readout can be used to achieve high-speed data output.

The preferred embodiments of the present invention have been described in detail, but the present invention is not limited to specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.

10.110: Storage cell array 20, 170: page buffer/readout circuit 30, 32: data transmission circuit 40, 130: ECC circuit 50, 120: input and output circuit 100: Flash memory 140: address register 150: Controller 160: character line selection circuit 180: column selection circuit 190: Internal voltage generating circuit 200: bit line selection circuit 210: Judgment circuit Ax: Row address information Ay: column address information BLCD1, BLCD2, BLCLAMP, BLCN, BLPRE, BLSe, BLSo, CACHE, DTG, EQ, NT1, NT2, PT1, PT2, REG, RESET2, VG, YBLo, YBLe: Transistor BLK(0), BLK(1),..., BLK(m-1): storage block BLS, SLR1, SLR2, SLS1, SLS2, TOBL: Node C0: first cache C1: second cache DL, /DL: data line ExCLK: external clock signal GBLe: Even bit line GBLo: odd bit line L1, L2: latch LAT1, /LAT1: latch enable signal MC0, MC1, MC2,..., MC31: storage unit NU: NAND string P0, P1, P2, P3: Page SA: Differential sense amplifier SGD, SGS: select gate line SL: Shared source line SNS: read node t1～t7: time tARRAY: Array read time TD: Select the transistor on the bit line side tDOUT: output time tECC: Time for ECC processing of data tp: The period from the start timing of the array read to the completion of the precharging of the bit line ts: The time when the data of the second cache C1 of the page P2 of the latch L1 is transferred to the latch L2 TS: source line side selection transistor tx: The period required for the reset of the latch L1 V1, V2: voltage supply node VCLMP1: Clamping cell voltage Vdd: internal supply voltage/supply voltage Vers: erase voltage VIRPWR: virtual power Vpass: pass voltage Vpgm: write voltage/program voltage Vread: Read the pass voltage WL0, WL1, WL2,..., WL31: character line

Fig. 1 is a diagram showing a schematic configuration of a conventional NAND flash memory. FIG. 2 is a timing chart when pages are continuously read in a conventional NAND flash memory. FIG. 3 is a block diagram showing the structure of a NAND flash memory according to an embodiment of the present invention. FIG. 4 is a diagram showing a configuration example of a NAND string of a flash memory according to an embodiment of the present invention. FIG. 5 is a diagram showing the configuration of a bit line selection circuit of a flash memory according to an embodiment of the present invention. FIG. 6 is a diagram showing the configuration of a page buffer/read circuit of a flash memory according to an embodiment of the present invention. FIG. 7 is a timing chart showing the reset operation of the latch circuit of the flash memory according to the embodiment of the present invention. FIG. 8 is a timing chart when the continuous read operation of the page of the embodiment of the present invention is performed.

BP: bit line precharge

L1: Latch

SNS: read node

BLSo, BLSe, BLCD1: Transistor

EQ_EN1: Transistor enable

LAT1: Latch enable signal

BLS, TOBL: Node

GBLe: Even bit line

GBLo: odd bit line

V1: Voltage supply node

VCLMP1: Clamping cell voltage

Vdd: supply voltage

GND: Ground level

t1~t7: time

Claims (17)

A readout method is a readout method for NAND flash memory, including: a precharging step, precharging a bit line and a NAND string connected to the bit line through a read node; resetting; Step of electrically connecting the node of the latch circuit to the reference potential via the sense node after precharging, reset the latch circuit by using the current path passing through the sense node; and the discharging step, Discharge the NAND string after reset. A readout method is a readout method for NAND flash memory, including: a precharging step, precharging a bit line and a NAND string connected to the bit line through a read node; and re In the setting step, during the discharge period of the NAND string, the node of the latch circuit is electrically connected to the reference potential via the sense node, and the latch circuit is reset by the current path passing through the sense node . The readout method according to claim 2, wherein the precharge step includes: generating a precharge voltage at a voltage supply node; electrically connecting the voltage supply node to the readout node via a first selection transistor; The second selection transistor electrically connects the read node to the bit line, The resetting step includes: generating the reference voltage at the voltage supply node; electrically connecting the voltage supply node to the latch circuit via the first selection transistor; connecting the voltage supply node to the latch circuit via the second transistor; The read node is electrically isolated. The reading method according to claim 2 or 3, wherein the steps are implemented in continuous reading of pages. The reading method according to claim 4, wherein the continuous reading of the page includes: holding the data read from the selected page of the memory cell array in the latch circuit, and holding the data held by the latch circuit After the data is transferred to other latch circuits, the data read from the next selected page is held in the latch circuit; the data held by the other latch circuits are continuously output to the outside in synchronization with an external clock signal. The readout method according to claim 5, wherein the continuous readout of the page further includes performing error detection and correction on the data of the first part of the other latch circuit, that is, during the error detection and correction process, the The two parts of the error detection and correction processed data are output to the outside, and while the first part of the error detection and correction processed data is output to the outside, error detection and correction processing is performed on the second part of the data. The readout method according to claim 6, comprising: after outputting the error detection and correction processed data of the first part of the other latch circuit to the outside, the next selection of the first part of the latch circuit The data of the page is sent to the first part of the other latch circuit; After outputting the error detection and correction processed data of the second part of the other latch circuit to the outside, the data of the next selected page of the second part of the latch circuit is sent to the other latch circuit The second part. The readout method according to claim 6 or 7, wherein the continuous readout is a first continuous readout with a limit represented by tARRAY+tECC<tDOUT, wherein the data of the first part and the second part are 1/ For 2 pages of data, tARRAY is the time required to read the selected page, tECC is the time required to perform error detection and correction processing on 1/2 page, and tDOUT is the time required to output all the data of one page. The readout method according to claim 6 or 7, wherein the continuous readout is a second continuous readout with restrictions represented by tARRAY<tDOUT, tECC<tDOUT (1/2 page), wherein the first part and the first part The two parts of the data are 1/2 pages of data, tARRAY is the time required to read the selected page, tECC is the time required to perform error detection and correction processing on 1/2 page, and tDOUT is the time required to output all the data of one page. The required time, tDOUT (1/2 page) is the time required to output 1/2 page of data. The readout method according to claim 9, wherein the second continuous readout has an earlier readout timing of the selected page of the memory cell array than the first continuous readout. A semiconductor device includes: a NAND-type memory cell array; a readout component for reading data from a selection page of the memory cell array; and The output unit outputs the data read by the readout unit to the outside, the readout unit includes a page buffer/readout circuit connected to the memory cell array via a bit line, and the readout unit is performing page During continuous readout, the reset of the latch circuit included in the page buffer/readout circuit is performed between the precharge period of the bit line and the discharge period of the NAND string, and the reset is to reset all the latch circuits through the readout node. The node of the latch circuit is electrically connected to a reference potential so as to use a current path passing through the sense node. A semiconductor device includes: a NAND-type memory cell array; a readout unit for reading data from a selection page of the memory cell array; and an output unit for outputting the data read by the readout unit to the outside, so The readout unit includes a page buffer/readout circuit connected to the memory cell array via a bit line. When the readout unit performs continuous readout of the page, the NAND string after precharging the bit line is performed. During the discharge period of the page buffer/readout circuit, the reset of the latch circuit included in the page buffer/readout circuit is performed, and the reset is to electrically connect the node of the latch circuit to the reference potential through the readout node to utilize the Read the current path of the node. The semiconductor device according to claim 12, wherein the page buffer/readout circuit includes: a voltage supply node, the readout node, the latch circuit, the voltage supply node connected to the voltage supply node, and the readout circuit The first selection transistor between the nodes, the second selection transistor connected between the readout node and the bit line A crystal, and a third selection transistor connected between the sense node and the latch circuit, and make the first selection transistor and the third selection transistor conduct, so that the second selection transistor The transistor is not conductive, and the latch circuit is electrically connected to the reference potential of the voltage supply node to reset the latch circuit. The semiconductor device according to claim 13, wherein the readout unit makes the first selection transistor and the second selection transistor conductive, makes the third selection transistor non-conductive, and reduces the voltage The voltage supplied to the node is precharged to the bit line. The semiconductor device according to claim 12, wherein when the reading section performs continuous reading of pages, the output section continuously outputs the read data in synchronization with an external clock signal. The semiconductor device according to claim 12, wherein the page buffer/readout circuit further includes another latch circuit that receives the data held by the latch circuit, and when the readout section performs continuous readout, During the output of the data of the other latch circuit, the data read from the next selected page of the memory cell array is held in the latch circuit. The semiconductor device according to claim 16, wherein the semiconductor device further includes an error detection and correction circuit that performs data error detection and correction, When the readout unit performs continuous readout, while the error detection and correction circuit performs error detection and correction processing on the data held in the first part of the other latch circuit, the output is output to the other latch circuit The second part of the data kept by error detection and correction processing.

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