TWI741891B - Circuit board structure and manufacturing method thereof - Google Patents

Abstract

A circuit board structure includes at least two sub-circuit boards and at least one connecting component. Each of the sub-circuit boards includes a plurality of carrier units. The connecting component is connected between the sub-circuit boards, and a plurality of stress-relaxation gaps are defined between the sub-circuit boards.

Description

Circuit board structure and manufacturing method thereof

The present invention relates to a circuit board structure and a manufacturing method thereof, and particularly relates to a circuit board structure and a manufacturing method thereof that can avoid warping during reflow.

The selection and placement of light-emitting diodes are related to the flatness of the copper contact pads on the circuit board. If the flatness of the copper contact pads on the circuit board is not good, the bonding yield will be reduced, resulting in yield loss. Furthermore, the reflow temperature and the size of the circuit board will also affect the bonding yield. When the reflow temperature is high, the circuit board with a larger area size cannot be released due to stress, and greater warpage will occur, thereby reducing the assembly yield of the circuit board. If the circuit board is cut into a small-area circuit board in order to avoid warping of a circuit board with a large area, it will reduce the assembly throughput of surface mounting technology (SMT) components, and also It will increase the manufacturing steps of assembling the light-emitting diode to the display.

The present invention provides a circuit board structure, which can avoid or reduce warpage during reflow and can improve the assembly yield of surface mount technology (SMT) components.

The present invention also provides a manufacturing method of the circuit board structure, which is used to manufacture the above-mentioned circuit board structure.

The circuit board structure of the present invention includes at least two sub-circuit boards and at least one connector. Each sub-circuit board includes a plurality of carrier units. The connector is connected between the sub-circuit boards, and a plurality of stress relief gaps are defined between the sub-circuit boards.

In an embodiment of the present invention, each of the aforementioned stress relief gaps is a through hole.

In an embodiment of the present invention, each of the above-mentioned carrier units includes a core substrate, a plurality of conductive adhesive blocks, a first circuit layer and a second circuit layer. The core substrate has an upper surface and a lower surface opposite to each other, and a plurality of through holes penetrating the core substrate and connecting the upper surface and the lower surface. The conductive adhesive blocks are respectively arranged in the through holes of the core substrate. The first circuit layer is disposed on the upper surface of the core substrate and covers the upper surface and a top surface of each conductive rubber block. The second circuit layer is disposed on the lower surface of the core substrate and covers the lower surface and a bottom surface of each conductive adhesive block.

In an embodiment of the present invention, each of the above-mentioned carrier units further includes a first solder resist layer and a second solder resist layer. The first solder mask is disposed on a part of the upper surface exposed by the first circuit layer, and extends to cover a part of the first circuit layer and expose a part of the first circuit layer. The second solder mask is disposed on a part of the lower surface exposed by the second circuit layer, and extends to cover a part of the second circuit layer and expose a part of the second circuit layer.

In an embodiment of the present invention, each of the above-mentioned carrier units further includes a first surface treatment layer and a second surface treatment layer. The first surface treatment layer is configured on the first circuit layer exposed by the first solder mask. The second surface treatment layer is configured on the second circuit layer exposed by the second solder mask.

In an embodiment of the present invention, the aforementioned at least one connecting element includes a plurality of connecting elements, and the connecting elements are located on the same axis.

In an embodiment of the present invention, the aforementioned at least one connecting member includes a plurality of first connecting members and a plurality of second connecting members. The first connecting member is located on a first axis, and the second connecting member is located on a second axis, and the first axis is perpendicular to the second axis.

The manufacturing method of the circuit board structure of the present invention includes the following steps. A circuit substrate is provided, and a plurality of carrier units are formed on the circuit substrate. A plurality of stress relief gaps are formed on the circuit substrate, and the circuit substrate is divided into at least two sub-circuit boards and at least one connector. The connector is connected between the sub-circuit boards, and the sub-circuit boards include a board carrier unit.

In an embodiment of the present invention, the step of forming a stress relief gap on the circuit substrate includes forming a plurality of through holes on the circuit substrate.

In an embodiment of the present invention, the above-mentioned step of forming each carrier unit includes: providing a core substrate, the core substrate having an upper surface and a lower surface opposite to each other and penetrating the core substrate and connecting the upper surface and A plurality of through holes on the lower surface, in which the core substrate is in a B-stage state. A plurality of conductive glue blocks are filled in the through holes of the core substrate, wherein the conductive glue blocks protrude from the upper surface and the lower surface. A first circuit layer and a second circuit layer are respectively formed on the core substrate by pressing, curing and patterning. The core substrate changes from a B-stage state to a C-stage state. The first circuit layer is disposed on the upper surface of the core substrate and covers the upper surface and a top surface of each conductive adhesive block, while the second circuit layer is disposed on the lower surface of the core substrate and covers the lower surface and each A bottom surface of a conductive adhesive block.

Based on the above, in the design of the circuit board structure of the present invention, the connector connected between the sub-circuit boards can define a stress relief gap with the sub-circuit board, thereby releasing the stress generated by the circuit board structure during reflow. . Therefore, the circuit board structure of the present invention can avoid or reduce warpage, thereby improving the assembly yield of surface mount technology (SMT) components assembled on it.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

FIG. 1A is a schematic diagram of a circuit board structure according to an embodiment of the invention. FIG. 1B is a schematic cross-sectional view of a carrier unit in FIG. 1A. 1A, in this embodiment, the circuit board structure 100a includes at least two sub-circuit boards (schematically shows two sub-circuit boards 110a, 110b) and at least one connector (schematically shows three connections) 120). Each sub-circuit board 110a, 110b includes a plurality of carrier units U. The connecting member 120 is connected between the sub-circuit boards 110a and 110b, and a plurality of stress relief gaps are defined between the sub-circuit boards 110a and 110b (four stress relief gaps G are schematically shown). That is, each connecting member 120 is partially connected to the two adjacent side walls 111, 113 of the sub-circuit boards 110a, 110b, and there is a stress relief gap G between the two side walls 111, 113 and the connecting member 120, wherein the stress relief The gap G and the connecting member 120 are alternately arranged. Here, the connecting member 120 is located on the same axis X.

Furthermore, this embodiment first provides a circuit substrate 110 on which a plurality of carrier units U have been formed. After that, a stress relief gap G is formed on the circuit substrate 110, and the circuit substrate 110 is divided into sub-circuit boards 110a, 110b and the connecting member 120. Here, each stress relief gap G is embodied as a through hole, in which, for example, the stress relief gap G is formed by cutting or drilling, but it is not limited to this.

More specifically, referring to FIG. 1B, each carrier unit U includes a core substrate 210, a plurality of conductive adhesive blocks (two conductive adhesive blocks 220 are schematically shown), a first circuit layer 230, and a first circuit layer 230. Two circuit layer 240. The core substrate 210 has an upper surface 212 and a lower surface 214 opposite to each other, and a plurality of through holes (two through holes 216 are schematically shown) penetrating the core substrate 210 and connecting the upper surface 212 and the lower surface 214. The conductive adhesive blocks 220 are respectively disposed in the through holes 216 of the core substrate 210. The first circuit layer 230 is disposed on the upper surface 212 of the core substrate 210 and covers the upper surface 212 and a top surface 222 of each conductive rubber block 220. The second circuit layer 240 is disposed on the lower surface 214 of the core substrate 210 and covers the lower surface 214 and a bottom surface 224 of each conductive adhesive block 220. Here, the first circuit layer 230 and the second circuit layer 240 are respectively a patterned circuit layer, wherein the first circuit layer 230 exposes part of the upper surface 212 of the core substrate 210, and the second circuit layer 240 exposes Part of the lower surface 214 of the core substrate 210.

In the manufacturing process, the step of forming each carrier unit U includes first providing a core substrate 210, wherein the core substrate 210 is in a B-stage state at this time, meaning that it has not been completely cured, and the thickness of the core substrate 210 is, for example, 20 microns to 100 microns. Then, release films can be attached to opposite sides of the core substrate 210, where the material of the release film is, for example, polyester polymer (PET). Next, a drilling process is performed on the core substrate 210 to form a through hole 216. The drilling process is, for example, laser drilling or mechanical drilling, but not limited to this. Next, by printing or injection, a conductive adhesive is filled in the through hole 216 to form a conductive adhesive block 220. After that, the release films attached to the opposite sides of the core substrate 210 are removed, so that the top surface 222 and the bottom surface 224 of the conductive glue block 220 protrude from the upper surface 212 and the bottom surface 214 of the core substrate 210, respectively. Then, when the core substrate 210 is in the B-stage state, press two copper foil layers on the upper surface 212 and the lower surface 214 of the core substrate 210, wherein the copper foil layer covers the upper surface 212 and the lower surface of the core substrate 210 214 and the top surface 222 and bottom surface 224 of the conductive glue block 220. In particular, the surface roughness of the copper foil layer is less than 1 micron, wherein the surface roughness of the opposite sides of the copper foil layer can be different, and the copper foil layer faces the core substrate 210 with the thicker surface. After that, a curing process is performed to fix the copper foil layer on the core substrate 210. At this time, the core substrate 210 will change from the original B-stage state to a C-stage state, which means that it is in a fully cured state. Next, a patterning process is performed on the two copper foil layers to form the first circuit layer 230 on the upper surface 212 of the core substrate 210 and the second circuit layer 240 on the lower surface 214 of the core substrate 210.

Please refer to FIG. 1B again. In this embodiment, each carrier unit U further includes a first solder mask 250 and a second solder mask 260. The first solder mask 250 is disposed on a part of the upper surface 212 exposed by the first circuit layer 230, and extends to cover a part of the first circuit layer 230 and expose a part of the first circuit layer 230. The second solder mask 260 is disposed on a part of the lower surface 214 exposed by the second circuit layer 240, and extends to cover a part of the second circuit layer 240 and expose a part of the second circuit layer 240.

In addition, each carrier unit U of this embodiment further includes a first surface treatment layer 270 and a second surface treatment layer 280. The first surface treatment layer 270 is disposed on the first circuit layer 230 exposed by the first solder mask layer 250, wherein the first surface treatment layer 270 covers the top surface and side surfaces of the first circuit layer 230 relatively far away from the core substrate 210. The second surface treatment layer 280 is disposed on the second circuit layer 240 exposed by the second solder mask layer 260, wherein the second surface treatment layer 280 covers the top surface and side surfaces of the second circuit layer 240 relatively far away from the core substrate 210. Here, the materials of the first surface treatment layer 270 and the second surface treatment layer 280 are, for example, ENIG (Electroless Nickel Immersion Gold), an organic solderability preservatives (OSP) layer, or ENIG (Electroless Nickel Immersion Gold). Nickel Immersion Gold, ENIG), but not limited to this.

In short, in the design of the circuit board structure 100a of this embodiment, the connector 120 connected between the sub-circuit boards 110a and 110b can define a stress relief gap G with the sub-circuit boards 110a and 110b, thereby releasing The stress generated by the circuit board structure 100a during reflow. Therefore, the circuit board structure 100a of the present embodiment can avoid or reduce warpage, thereby improving the assembly yield of surface mount technology (SMT) components assembled thereon.

It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

Fig. 2 is a schematic diagram of a circuit board structure according to another embodiment of the present invention. Please refer to FIG. 2 and FIG. 1A at the same time. The circuit board structure 100b of this embodiment is similar to the above-mentioned circuit board structure 100a. The difference between the two is: this embodiment forms stress relief gaps G1 and G2 on the circuit substrate 110' , And the circuit substrate 110' is divided into sub-circuit boards 110a, 110b, 110c, 110d, and a first connector 120a and a second connector 120b. Here, the first connecting member 120a is located on a first axis X1, and the second connecting member 120b is located on a second axis X2, and the first axis X1 is perpendicular to the second axis X2.

3 is a schematic cross-sectional view of the circuit board structure of FIG. 1A joined to the circuit board and the chip is disposed on the circuit board structure. In terms of application, please refer to FIG. 3. In this embodiment, a plurality of chips 20 can be electrically connected to the circuit board structure 100a through the first bumps 30, and each chip 20 can be provided corresponding to a carrier unit U. The circuit board structure 100 a can be electrically connected to a circuit motherboard 10 through the second bump 40, wherein the size of the second bump 40 is larger than the size of the first bump 30. Thereby, the application range of the circuit board structure 100a can be expanded.

In summary, in the design of the circuit board structure of the present invention, the connectors connected between the sub-circuit boards can define a stress relief gap with the sub-circuit board, thereby releasing the circuit board structure generated during reflow. Stress. Therefore, the circuit board structure of the present invention can avoid or reduce warpage, thereby improving the assembly yield of surface mount technology (SMT) components assembled on it.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

10: Circuit Motherboard 20: chip 30: The first bump 40: second bump 100a, 100b: circuit board structure 110, 110’: Circuit board 110a, 110b, 110c, 110d: daughter board 111, 113: sidewall 120: connecting piece 120a: first connector 120b: second connector 210: core substrate 212: upper surface 214: lower surface 216: Through hole 220: Conductive glue block 222: top surface 224: bottom surface 230: first circuit layer 240: second circuit layer 250: The first solder mask 260: The second solder mask 270: The first surface treatment layer 280: second surface treatment layer G, G1, G2: stress relief gap U: Carrier board unit X: axis X1: the first axis X2: second axis

FIG. 1A is a schematic diagram of a circuit board structure according to an embodiment of the invention. FIG. 1B is a schematic cross-sectional view of a carrier unit in FIG. 1A. Fig. 2 is a schematic diagram of a circuit board structure according to another embodiment of the present invention. 3 is a schematic cross-sectional view of the circuit board structure of FIG. 1A joined to the circuit board and the chip is disposed on the circuit board structure.

100a: circuit board structure

110: Circuit board

110a, 110b: sub-circuit board

111, 113: sidewall

120: connecting piece

G: Stress relief gap

U: Carrier board unit

X: axis

Claims (10)

A circuit board structure, including: At least two sub-circuit boards, each of the sub-circuit boards includes a plurality of carrier units; and At least one connector is connected between the at least two sub-circuit boards, and a plurality of stress relief gaps are defined between the at least two sub-circuit boards. The circuit board structure according to claim 1, wherein each of the stress relief gaps is a through hole. The circuit board structure according to claim 1, wherein each carrier unit includes: A core substrate having an upper surface and a lower surface opposite to each other, and a plurality of through holes penetrating the core substrate and connecting the upper surface and the lower surface; A plurality of conductive adhesive blocks are respectively arranged in the through holes of the core substrate; A first circuit layer disposed on the upper surface of the core substrate and covering the upper surface and a top surface of each conductive adhesive block; and A second circuit layer is disposed on the lower surface of the core substrate and covers the lower surface and a bottom surface of each conductive adhesive block. The circuit board structure according to claim 3, wherein each carrier unit further includes: A first solder mask layer disposed on a part of the upper surface exposed by the first circuit layer, extending to cover a part of the first circuit layer, and exposing a part of the first circuit layer; and A second solder mask layer is disposed on a part of the lower surface exposed by the second circuit layer, and extends to cover a part of the second circuit layer and expose a part of the second circuit layer. The circuit board structure according to claim 4, wherein each carrier unit further includes: A first surface treatment layer disposed on the first circuit layer exposed by the first solder mask; and A second surface treatment layer is disposed on the second circuit layer exposed by the second solder mask. The circuit board structure according to claim 1, wherein the at least one connecting element includes a plurality of connecting elements, and the connecting elements are located on the same axis. The circuit board structure according to claim 1, wherein the at least one connecting member includes a plurality of first connecting members and a plurality of second connecting members, and the first connecting members are located on a first axis, and the first connecting members The two connecting members are located on a second axis, and the first axis is perpendicular to the second axis. A method for manufacturing a circuit board structure includes: Providing a circuit substrate on which a plurality of carrier units are formed; and A plurality of stress relief gaps are formed on the circuit substrate, and the circuit substrate is divided into at least two sub-circuit boards and at least one connector, wherein the at least one connector is connected between the at least two sub-circuit boards, and the at least The two sub-circuit boards include the carrier units. The manufacturing method of the circuit board structure according to claim 8, wherein the step of forming the stress relief gaps on the circuit substrate includes forming a plurality of through holes on the circuit substrates. The manufacturing method of the circuit board structure according to claim 8, wherein the step of forming each carrier board unit includes: A core substrate is provided, the core substrate has an upper surface and a lower surface opposite to each other, and a plurality of through holes penetrating the core substrate and connecting the upper surface and the lower surface, wherein the core substrate is in a B stage state; Filling a plurality of conductive rubber blocks in the through holes of the core substrate, wherein the conductive rubber blocks protrude from the upper surface and the lower surface; and A first circuit layer and a second circuit layer are respectively formed on the core substrate by pressing, curing and patterning, wherein the core substrate is transformed from the B-stage state to a C-stage state, and the first The circuit layer is disposed on the upper surface of the core substrate and covers the upper surface and a top surface of each conductive adhesive block, and the second circuit layer is disposed on the lower surface of the core substrate and covers The bottom surface and a bottom surface of each conductive rubber block.

Images