TWI637371B - Shift register circuit - Google Patents

Abstract

The n-th stage shift register has an input unit, a pull-up unit, a pull-down control unit, and a pull-down unit. The input unit controls the first node voltage according to the (n-i) -th scanning signal. The pull-up unit outputs the n-th scanning signal to the output terminal according to the first clock signal. The pull-down control unit generates a pull-down control signal according to the second clock signal. The pull-down unit adjusts the output terminal voltage according to the pull-down control signal. The pull-up unit includes a voltage coupling unit coupled between the first node and the second node, and a first transistor, and a control terminal thereof is coupled to the first node of the (nj) th stage, and the first terminal receives the first clock The signal and the second terminal are coupled to the second node. The pull-down unit includes a second transistor, a first terminal of which is coupled to a second node, a second terminal of which is coupled to a reference voltage, and a control terminal which receives a pull-down control signal.

Description

Shift register circuit

The present invention relates to a display driving circuit, and more particularly to a display driving circuit using a shift register.

A display driving circuit for a display panel includes a gate driver circuit. The gate driving circuit can sequentially output a plurality of scanning signals by using a plurality of shift registers, and the scanning signals are respectively transmitted to a plurality of display panel. The gate lines drive the pixel array of the panel. With the improvement of the image resolution of the display panel and the increase of the frame rate, how to design a suitable shift register is one of the current issues in the industry.

The invention relates to a shift temporary storage circuit, which can effectively reduce the falling time of the output scanning signal.

According to an aspect of the present invention, a shift register circuit is provided, which includes a multi-stage shift register. The n-th stage shift register includes: an input unit, a pull-up unit, a pull-down control unit, and a pull-down unit. . The input unit controls the voltage level of the first node according to the (n-i) -th scanning signal. The pull-up unit is coupled between the first node and the output terminal, and outputs the n-th scanning signal to the output terminal according to the first clock signal. drop down The control unit is coupled to the first node and generates a pull-down control signal according to the second clock signal. The pull-down unit is coupled to the first node and adjusts the voltage level of the output terminal to the first reference voltage according to the pull-down control signal. The pull-up unit includes a first transistor and a voltage coupling unit. The control terminal of the first transistor is coupled to the first node of the (nj) stage, the first terminal of the first transistor is used to receive the first clock signal, and the second terminal of the first transistor is coupled to a second node . The voltage coupling unit is coupled between the first node and the second node. The pull-down unit includes a second transistor, a first terminal of the second transistor is coupled to the second node, a second terminal of the second transistor is coupled to the first reference voltage, and a control terminal of the second transistor is used to receive the pull-down control signal. Where n, i, j are all positive integers.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are described in detail below in conjunction with the accompanying drawings:

1‧‧‧shift temporary storage circuit

101‧‧‧input unit

102, 102 ' ‧‧‧ Pull-up unit

103‧‧‧pull-down control unit

104,104 '‧‧‧ down unit

105‧‧‧Voltage coupling unit

106‧‧‧Reset unit

A (n) ‧‧‧pull-down control signal

D2U‧‧‧Reverse scan control signal

G (1), G (2), G (3), G (4), G (ni), G (n), G (n-2), G (n-1), G (n + 2) ‧‧‧ Output

HC1, HC2, HC3, HC4‧‧‧ clock signal

M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15‧‧‧ transistor

Q (n), Q (n-j), Q (n-1) ‧‧‧ first node

R1‧‧‧ resistance

RST‧‧‧ reset signal

SR (1), SR (2), SR (3), SR (4), SR (n) ‧‧‧ shift register

ST (n) ‧‧‧Second Node

t1, t2, t3, t4, t5, t6, t7, t8

U2D‧‧‧ Forward Scan Control Signal

VGH‧‧‧second reference voltage

VGL‧‧‧first reference voltage

FIG. 1 is a schematic diagram of a shift register circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram of an n-th stage shift register according to the first embodiment of the present invention.

FIG. 3 is a schematic diagram of a pull-up unit according to the first embodiment of the present invention.

FIG. 4 is a schematic diagram of a pull-down unit according to the first embodiment of the present invention.

FIG. 5 shows a timing diagram of signals corresponding to the circuit of FIG. 2.

FIG. 6 is a schematic diagram of an n-th stage shift register including a reset unit according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram of the n-th stage shift register for unidirectional scanning according to the first embodiment of the present invention.

FIG. 8 is a circuit diagram of an n-th stage shift register for bidirectional scanning according to the first embodiment of the present invention.

FIG. 9 shows a signal timing diagram corresponding to the circuit in FIG. 8 during a reverse scanning operation.

The following will clearly illustrate the spirit of the present disclosure with diagrams and detailed descriptions. Any person with ordinary knowledge in the technical field who understands the embodiments of the present disclosure can be changed and modified by the techniques taught in the present disclosure. It does not depart from the spirit and scope of this disclosure.

Regarding the "first", "second", ..., etc. used herein, it does not mean a specific order or order, nor is it used to limit the present invention, which is only for distinguishing elements or operations described in the same technical terms.

As used in this article, "electrical coupling" can mean that two or more components make direct physical or electrical contact with each other, or indirectly make physical or electrical contact with each other, and "electrical coupling" can also mean Two or more elements operate or act on each other.

The terms "including", "including", "having", "containing" and the like used in this article are all open terms, which means including but not limited to.

As used herein, "and / or" includes any and all combinations of the stated matters.

Terms used in this article, unless otherwise specified In addition, it usually has the ordinary meaning of each word used in this field, in the content disclosed here, and in special content. Certain terms used to describe this disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art on the description of this disclosure.

FIG. 1 is a schematic diagram of a shift register circuit 1 according to a first embodiment of the present invention. The shift register circuit 1 includes multi-stage shift registers SR (1), SR (2), SR (3), SR (4), and so on. Although FIG. 1 shows a four-stage shift register, However, it should be understood that the number of shift registers included in the shift register circuit 1 is not limited to four stages, and the number may be related to the number of gate lines of the display panel. The multiple shift registers SR (1) ~ SR (4) are connected in series, and the scanning signals are output to the gate lines of the display panel at the respective output terminals G (1) ~ G (4).

FIG. 1 is a simplified schematic diagram showing the connection of a plurality of shift registers, and the signal transmission between the shift registers is not limited to the method of FIG. 1. Taking forward scanning as an example, the shift register SR (2) can receive signals from the shift register SR (1), such as the scan signal at the output G (1) or the shift Other signals in the register SR (1) cause the shift register SR (2) to generate a scanning signal at the output terminal G (2). The shift register SR (3) can receive signals from the shift register SR (1) and / or the shift register SR (2) to generate a scanning signal at the output terminal G (3). That is, the signals received by each shift register are not limited to the shift register from the previous stage, but can also come from the shift registers of the first two stages. Taking reverse scanning as an example, the shift register SR (1) can receive data from the shift register. The signals of the register SR (2) and / or the shift register SR (3) are used to generate the scanning signal of the output terminal G (1). The invention is not limited to this.

In addition, each shift register SR (1) ~ SR (4) can receive the same or different clock signals. For example, if the first clock signal and the second clock signal of two phases are used in the shift register circuit 1, and the first clock signal and the second clock signal have a phase offset, then The shift registers SR (1) and SR (3) can generate the scanning signals of the output terminals G (1) and G (3) according to the first clock signal, and the shift registers SR (2) and SR (4) ) The scan signals of the output terminals G (2) and G (4) can be generated according to the second clock signal. If four-phase (multi-phase) clock signals are used, the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal have phase differences from each other, the shift is temporarily The register SR (1) can generate the scanning signal of the output terminal G (1) according to the first clock signal, and the shift register SR (2) can generate the scanning signal of the output terminal G (2) according to the second clock signal. The shift register SR (3) can generate the scanning signal of the output terminal G (3) according to the third clock signal, and the shift register SR (4) can generate the output terminal G (4) of the fourth clock signal. ) Scan signal. When the shift register circuit 1 is connected with more stages of shift registers in series, the operation of the remaining shift registers can be deduced by analogy according to the above content, and the details are not repeated here.

Please refer to FIG. 2, which illustrates a schematic diagram of an n-th stage shift register according to the first embodiment of the present invention. The n-th stage shift register SR (n) includes an input unit 101, a pull-up unit 102, a pull-down control unit 103, and a pull-down unit 104. The input unit 101 may be coupled to the output terminal G (ni) of the (ni) th stage shift register, and control the voltage level of the first node Q (n) according to the (ni) th stage scanning signal, where i is a positive integer . example For example, when i = 1, the input unit 101 receives the (n-1) th stage scanning signal provided by the (n-1) th stage shift register SR (n-1) output terminal G (n-1); when When i = 2, the input unit 101 receives the (n-2) th stage scanning signal provided by the output terminal G (n-2) of the (n-2) th stage shift register SR (n-2). The pull-up unit 102 is coupled between the first node Q (n) and the output terminal G (n). The pull-up unit 102 outputs an n-th stage scanning signal to the output terminal G (n) according to the clock signal HC1. The pull-down control unit 103 is coupled to the first node Q (n), and the pull-down control unit 103 generates a pull-down control signal A (n) according to the clock signal HC3. The pull-down unit 104 is coupled to the first node Q (n). The pull-down unit 104 adjusts the voltage level of the output terminal G (n) to the first reference voltage VGL according to the pull-down control signal A (n), such as a low reference voltage. The phase difference between the clock signal HC1 and the clock signal HC3 is, for example, 180 degrees. Where n is a positive integer.

The voltage level of the first node Q (n) in the shift register SR (n) is related to the operation mode of the shift register SR (n), for example, when the first node Q (n) is at a low voltage level , The shift register SR (n) is in a non-operation state, and the output terminal G (n) maintains a low voltage level; when the first node Q (n) is a high voltage level, it means that the corresponding gate line is to be driven The shift register SR (n) is in an operating state, and the output terminal G (n) will provide a scanning signal at a high voltage level.

The pull-up unit 102 may increase the voltage level of the output terminal G (n), and the pull-down unit 104 may cause the voltage level of the output terminal G (n) to decrease. The pull-up unit 102 includes a transistor M1 and a voltage coupling unit 105. The control terminal of the transistor M1 is coupled to the first node Q (n-j) of the (n-j) stage, where j is a positive integer. For example, the (n-j) th stage shift register SR (n-j) has the same result as the nth stage shift register SR (n). Structure, there is also a first node Q (nj) inside the (nj) -stage shift register SR (nj), and the position is the same as that in the n-stage shift register SR (n) shown in FIG. 2 The position of a node Q (n). The control terminal of the transistor M1 of the n-th stage shift register SR (n) is coupled to the first node Q (n-j) of the (n-j) -stage shift register SR (n-j). The first terminal of the transistor M1 is used to receive the clock signal HC1, and the second terminal of the transistor M1 is coupled to the second node ST (n). The voltage coupling unit 105 is coupled between the first node Q (n) and the second node ST (n). The voltage coupling unit 105 may be, for example, a capacitor.

The pull-down unit 104 is coupled to a first node Q (n), a second node ST (n), and an output terminal G (n). The pull-down unit 104 includes a transistor M2, a first terminal of the transistor M2 is coupled to the second node ST (n), a second terminal of the transistor M2 is coupled to a first reference voltage VGL, and a control terminal of the transistor M2 is used for receiving Pull-down control signal A (n). In the embodiment shown in FIG. 2, the transistors are all using n-type thin-film transistors (hereinafter referred to as N-type transistors) as examples, but it should be understood that the transistors shown in the figure Other types of transistors can also be used instead, and the driving mode should be changed adaptively. In this description, N-type transistors will be used as an example to keep the description consistent and easy to understand.

FIG. 3 is a schematic diagram of a pull-up unit according to the first embodiment of the present invention. In an embodiment disclosed by the present invention, the pull-up unit 102 includes a transistor M3, the control terminal of the transistor M3 is coupled to the first node Q (n), and the first terminal of the transistor M3 is used to receive the first clock signal HC1 The second terminal of the transistor M3 is coupled to the output terminal G (n) for outputting the n-th scanning signal. As shown in FIG. 3, the transistor M3 can be used as a pull-up transistor at the output terminal G (n). When the first node Q (n) is at a high voltage level, the transistor M3 When the transistor M3 is turned on, the voltage level of the output terminal G (n) can be pulled up to a high voltage level close to the clock signal HC1 by using the timing of the clock signal HC1 to output the n-th scanning signal. It should be noted that FIG. 3 shows only one embodiment of the pull-up unit 102, and the transistor M3 can also be replaced by a combination of multiple transistors, which is not limited in the present invention.

FIG. 4 is a schematic diagram of a pull-down unit according to the first embodiment of the present invention. In an embodiment disclosed by the present invention, the pull-down unit 104 has a transistor M4 and a transistor M5, wherein each transistor has a first terminal, a second terminal, and a control terminal. The control terminals of transistor M2, transistor M4, and transistor M5 are all coupled to the pull-down control signal A (n). The first terminal of transistor M5 is coupled to the first node Q (n) as the first node Q ( n) a pull-down transistor, the first terminal of transistor M2 is coupled to the second node ST (n) as a pull-down transistor of the second node ST (n), and the first terminal of transistor M4 is coupled to the output terminal G (n) is a pull-down transistor as the output terminal G (n). FIG. 4 shows only an embodiment of the pull-down unit 104, and the pull-down transistors of each node can also be replaced by a combination of multiple transistors, which is not limited in the present invention.

The operation mode of the n-th stage shift register SR (n) will be described below. Please refer to FIG. 5. FIG. 5 shows a signal timing diagram corresponding to the circuit of FIG. 2. The pull-up unit 102 can refer to FIG. The drawing and pull-down unit 104 can refer to FIG. 4. In this example, the clock signals HC1, HC2, HC3, and HC4 with four phases are used, and the phase difference between them is 90 degrees. The voltage level improvement of the first node Q (n) (from the time point t3 to the time point t6) can be divided into three stages, and each stage is described below. In the following In the examples, i = 2 and j = 2 are used as examples. However, the present invention is not limited to this, and may be coupled to different front-stage shift registers in different embodiments.

In the first stage: from time point t3 to time point t5, the voltage of the first node Q (n) is the first voltage provided by the input unit 101 according to the (n-2) th stage shift register output terminal G (n-2). (n-2) level scanning signals. The voltage of the scan signal at the output terminal G (n-2) rises at time point t3, so that the voltage of the first node Q (n) rises at time point t3.

In the second stage: from time point t5 to time point t6, the clock signal HC1 rises to a high voltage level at time point t5, at this time the first node Q (n-1) of the (n-1) th stage is still At high voltage, the transistor M1 is turned on, and the clock signal HC1 is transmitted to the second node ST (n). Through the coupling effect of the voltage coupling unit 105 and the coupling effect of the transistor M3, the clock signal HC1 whose voltage rises at the time point t5 will cause the voltage of the first node Q (n) to rise further. As shown in Fig. 5, the voltage of the first node Q (n) in the second stage is higher than that in the first stage.

In the third stage: from time point t6 to time point t7, the voltage of the clock signal HC1 decreases and the voltage of the first node Q (n-1) of the (n-1) th stage decreases. At this time, the first node Q (n) The voltage will be lower than the second stage. However, the voltage of the first node Q (n) in the third stage will be higher than the voltage in the first stage, as described in detail below.

Please first observe the voltage change at the first node Q (n-1) of the (n-1) th stage. At the time point t5, the voltage of the clock signal HC1 rises, via the coupling effect of the transistor M1 as shown in FIG. 3, The voltage of the first node Q (n-1) of the (n-1) th stage can be increased slightly. Similarly, in the (n + 1) -th stage shift register SR (n + 1), the voltage of the clock signal HC2 at time point t6 rises and passes through the (n + 1) -stage shift register SR (n + 1) Internal The coupling effect of the transistor M1 can slightly increase the voltage of the first node Q (n) of the n-th stage.

As mentioned above, with the transistor M1, the voltage level of the first node Q (n) in the third stage can be increased, so that the voltage difference between the gate and the source of the transistor M3 is increased, and the equivalent is reduced. The resistance value of the transistor M3 can increase the current flowing through the transistor M3. At this time, the transistor M4 pulls down the voltage level of the output terminal G (n) to the first reference voltage VGL. As the current becomes larger and the discharge speed becomes faster, the fall time of the scanning signal at the output terminal G (n) can be reduced ( fall time) for faster operations. That is, the voltage at the third stage of the first node Q (n) can correspond to the speed of the voltage drop at the output terminal G (n). By increasing the voltage at the third stage of the first node Q (n), the operation of the circuit can be improved. speed.

At time point t7, the voltage of the clock signal HC3 rises, and the voltage of the pull-down control signal A (n) generated by the pull-down control unit 103 rises accordingly. The pull-down unit 104 is started to operate, and the first node Q (n) can be controlled by the transistor M5. The voltage is pulled down. Transistor M2 can provide voltage stabilization. During the non-operation period of the shift register SR (n), that is, when the first node Q (n) maintains a low voltage level, the second node ST (n ) Discharge, so that the second node ST (n) can be stably maintained at a low voltage level, and the charge stored in the voltage coupling unit 105 is cleared.

Several embodiments of the shift register SR (n) are described below. FIG. 6 is a schematic diagram of an n-th stage shift register including a reset unit according to the first embodiment of the present invention. Compared to FIG. 2, the embodiment shown in FIG. 6 further includes a reset unit 106. The reset unit 106 can adjust the voltage level of the pull-down control signal A (n) according to the reset signal RST. When the reset is performed (for example, the reset signal RST is at a high voltage level), the pull-down control signal A (n) can be made at a high voltage level. As shown in FIG. 4, the transistors M5, M2, and M4 are respectively Pull down the voltage levels of the first node Q (n), the second node ST (n), and the output terminal G (n). The reset unit 106 includes a transistor M9. The first terminal of the transistor M9 is coupled to the control terminal of the transistor M9 to receive a reset signal RST. The second terminal of the transistor M9 is coupled to the pull-down control unit 103. Output terminal to adjust the voltage level of the pull-down control signal A (n).

FIG. 7 shows a circuit diagram of the n-th stage shift register for unidirectional scanning according to the first embodiment of the present invention. FIG. 7 shows an exemplary circuit implementation of each unit as shown in FIG. 6. In this example, i = 2, j = 1, but the present invention is not limited to this value.

In an embodiment disclosed by the present invention, the shift register SR (n) may further include a transistor M8, a first terminal of the transistor M8 is coupled to the input unit 101, and a second terminal of the transistor M8 is coupled to the first node. Q (n), the control terminal of the transistor M8 is coupled to the second reference voltage VGH, such as a high reference voltage. Since the control terminal of the transistor M8 is connected to the DC second reference voltage VGH, it can be regarded as a switching element that maintains conduction. The first and second terminals of the transistor M8 can be regarded as having substantially equal voltage levels, so The transistor M8 is optional, and the transistor M8 is not included in the embodiments of FIG. 2 and FIG. 6. The function of the transistor M8 is to make the circuit load (RC loading) of the shift register SR (n) seen by the input unit 101 not too great.

The shift register SR (n) may further include a transistor M7, the first terminal of the transistor M7 is coupled to the input unit 101, the second terminal of the transistor M7 is coupled to the output terminal G (n), and the control of the transistor M7 The terminal is coupled to the output terminal G (n). Since the transistor is There may still be a leakage current when turned off. In order to prevent the voltage of the first node Q (n) from leaking through the path composed of transistor M8 and transistor M5, a transistor M7 coupled to the output terminal G (n) can be set to The effect of preventing electric leakage. Transistor M7 is also selectively arranged. In the foregoing embodiment of FIG. 2 and FIG. 6, the transistor M7 is not included.

The input unit 101 includes a transistor M12. When the (n-2) th stage scanning signal is at a high voltage level, the transistor M12 is turned on to raise the voltage level of the first node Q (n). The reset unit 106 includes a transistor M9, which is a diode-connected transistor. When the reset signal RST is at a high voltage level, the voltage level of the pull-down control signal A (n) is raised. .

The pull-down control unit 103 includes a transistor M10, a transistor M11, and a resistor R1. The control terminal of the transistor M10 is coupled to the clock signal HC3, and the control terminal of the transistor M11 is coupled to the first node Q (n). When the shift register SR (n) is in the operation stage, that is, when the first node Q (n) is at a high voltage level, the pull-down control signal A (n) is at a low voltage level. The pull-down control can be ensured by setting the resistor R1 The voltage level of the control signal A (n) is sufficiently low, and the resistor R1 is selectively settable. When the voltage of the clock signal HC3 rises, the transistor M10 is turned on, so that the voltage of the pull-down control signal A (n) rises, and then the pull-down unit 104 starts the pull-down voltage of multiple nodes.

In an embodiment disclosed in the present invention, the voltage coupling unit 105 in the pull-up unit 102 may be an equivalent capacitor formed by a transistor M6. The control terminal of the transistor M6 is coupled to the first node Q (n) and the transistor M6. Both the first and second terminals are coupled to the second node ST (n), so the transistor M6 functions as a capacitor.

In an embodiment disclosed by the present invention, the pull-down unit 104 includes a transistor M13 in addition to the transistors M5, M2, and M4 as shown in FIG. The control terminal of the transistor M13 is used to receive the (n + 2) th stage scanning signal. The first terminal of the transistor M13 is coupled to the output terminal G (n), and the second terminal of the transistor M13 is coupled to the first reference voltage. VGL. The example used here is i = 2, i can also be other positive integer, then the control terminal of transistor M12 is used to receive the (ni) th level scanning signal, and the control terminal of transistor M13 is used to receive the (n + i) th Level scan signal. The transistor M13 and the transistor M4 are coupled between the first reference voltage VGL and the output terminal G (n) to increase the pull-down strength of the output terminal G (n). The pull-down unit 104 is controlled by the pull-down control signal A ( n) and the subsequent scanning signal G (n + i), the transistor M13 is selectively settable.

In an embodiment disclosed by the present invention, the gate driving circuit of the display panel can support a bidirectional scanning function, for example, it can sequentially scan from the top of the panel to the forward scanning below the panel, or it can sequentially scan from the bottom of the panel to the top of the panel. Scan in reverse. Please refer to FIG. 8. FIG. 8 is a circuit diagram of an n-th stage shift register for bidirectional scanning according to the first embodiment of the present invention. The difference from the embodiment shown in FIG. 7 includes an input unit 101 and a pull-up unit 102.

In the embodiment shown in FIG. 8, the input unit 101 includes a transistor M12 and a transistor M14. The control terminal of the transistor M12 receives the (n-2) th level of the scanning signal, and the control terminal of the transistor M14 receives the (n +2) level scan signal. The use example here is i = 2, i can also be other positive integers. The input unit 101 is based on the (ni) th scan signal, the (n + i) th scan signal, the forward scan control signal U2D, and the reverse scan. The control signal D2U adjusts the voltage level of the first node Q (n). The control signal U2D and the reverse scanning control signal D2U may be two signals with complementary phases, or two signals with opposite voltage levels, which is not limited in the present invention.

Compared with FIG. 7, the pull-up unit 102 ′ shown in the embodiment of FIG. 8 further includes a transistor M15, and the control terminal of the transistor M15 is coupled to the first node of the (n + j) stage (the node used in FIG. The example is j = 1). The first terminal of the transistor M15 is used to receive the first clock signal HC1, and the second terminal of the transistor M15 is coupled to the second node ST (n).

When the display panel performs forward scanning (from top to bottom), the forward scanning control signal U2D is at a high voltage level, and the reverse scanning control signal D2U is at a low voltage level. The clock signal HC1 can be increased through the transistor M1. The voltage level of the first node Q (n-1) of the stage shift register SR (n-1) in the third stage; when the display panel performs reverse scanning (from bottom to top), forward scanning control The signal U2D is at a low voltage level, and the reverse scanning control signal D2U is at a high voltage level. The clock signal HC1 can increase the first node Q (n) of the previous-stage shift register SR (n + 1) through the transistor M15. +1) the voltage level in the third stage.

FIG. 9 shows a signal timing diagram corresponding to the circuit in FIG. 8 during a reverse scanning operation. The operating principle is similar to that described in Figure 5, except that it is changed to scan from bottom to top. The voltage level increase of the first node Q (n) can also be divided into three stages. The first stage: from the time point t3 to the time point t5, the voltage of the first node Q (n) is the first ((+2)) stage shift register output terminal G (n + 2) provided by the input unit 101 ( n + 2) level scanning signals. The second stage: from time point t5 to time point t6, the clock signal HC1 whose voltage rises at time point t5 will cause the voltage of the first node Q (n) to rise further. The third stage: from time point t6 to time point t7, the clock signal HC2 is at time point t6 The voltage rise of the transistor n through the coupling effect of the transistor M15 in the (n-1) th stage shift register SR (n-1) can increase the first node Q (n) of the nth stage in the third stage. Voltage.

According to the shift register circuit provided by the embodiment of the present invention, the voltage level of the first node in the shift register in the third stage can be increased by setting the appropriate transistor in the pull-up unit and the pull-down unit, and It can shorten the falling time of the falling edge of the scan signal at the output of the shift register and improve the circuit operation speed, so it can be applied to a variety of high-speed applications, such as game applications, high-resolution, and high-screen-update display panels. .

In summary, although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (11)

A shift register circuit includes a complex-stage shift register. An n-stage shift register of the complex-stage shift register includes: an input unit according to a (ni) -stage scan signal. Controlling a voltage level of a first node; a pull-up unit coupled between the first node and an output terminal, and outputting an n-level scanning signal to the output terminal according to a first clock signal; The control unit is coupled to the first node and generates a pull-down control signal based on a second clock signal; and the pull-down unit is coupled to the first node and adjusts the voltage level of the output terminal to one according to the pull-down control signal. A first reference voltage; wherein the pull-up unit includes: a first transistor, a control terminal of the first transistor is coupled to a first node of the (nj) th stage, and the first terminal of the first transistor is used for After receiving the first clock signal, the second terminal of the first transistor is coupled to a second node; and a voltage coupling unit is coupled between the first node and the second node; wherein the pull-down unit includes : A second transistor, the first of the second transistor Coupled to the second node, the second terminal of the second transistor is coupled to the first reference voltage, and the control terminal of the second transistor is used to receive the pull-down control signal; where n, i, j are all positive Integer. The shift register circuit according to item 1 of the patent application scope, wherein the pull-up unit of the n-stage shift register further includes a third transistor, and a control terminal of the third transistor is coupled The first node, a first terminal of the third transistor is used to receive the first clock signal, and a second terminal of the third transistor is coupled to the output terminal to output the n-th scanning signal. The shift register circuit according to item 1 of the patent application scope, wherein the pull-down unit of the n-th stage shift register further includes a fourth transistor, and a control terminal of the fourth transistor is used to receive A (n + i) th stage scanning signal, a first terminal of the fourth transistor is coupled to the output terminal, and a second terminal of the fourth transistor is coupled to the first reference voltage. The shift register circuit according to item 1 of the patent application scope, wherein the pull-up unit of the n-th stage shift register further includes a fifth transistor, and a control terminal of the fifth transistor is coupled A first node of the (n + j) stage, a first terminal of the fifth transistor is used to receive the first clock signal, and a second terminal of the fifth transistor is coupled to the second node. The shift register circuit according to item 4 of the scope of patent application, wherein the input unit of the n-th stage shift register is based on the (ni) -th scan signal and a (n + i) -th scan signal. A forward scan control signal and a reverse scan control signal to adjust the voltage level of the first node, wherein the forward scan control signal and the reverse scan control signal are two signals with opposite voltage levels. The shift temporary storage circuit according to item 1 of the patent application scope, wherein the voltage coupling unit includes a sixth transistor, and a control terminal of the sixth transistor is coupled to the first node, and the sixth transistor is connected to the first node. One end and the second end are coupled to the second node. The shift register circuit according to item 1 of the patent application scope, wherein the n-stage shift register further includes: a reset unit that adjusts the voltage level of the pull-down control signal according to a reset signal. The shift register circuit according to item 1 of the scope of patent application, wherein the n-stage shift register further includes: a seventh transistor, a first terminal of the seventh transistor is coupled to the input unit, A second terminal of the seventh transistor is coupled to the output terminal, and a control terminal of the seventh transistor is coupled to the output terminal. The shift register circuit according to item 1 of the scope of patent application, wherein the n-stage shift register further includes: an eighth transistor, a first terminal of the eighth transistor is coupled to the input unit, A second terminal of the eighth transistor is coupled to the first node, and a control terminal of the eighth transistor is coupled to a second reference voltage. The shift temporary storage circuit as described in item 1 of the scope of patent application, where i = 2 and j = 1. The shift temporary storage circuit according to item 1 of the patent application scope, wherein the pull-down unit is coupled to the first node, the second node, and the output terminal.