TWI635478B - Driving device of automatically adjusting frame rate for active matrix electrophoretic display and driving method thereof - Google Patents

Abstract

The invention provides a driving device for automatically adjusting a frame rate of an active matrix electrophoretic display and a driving method thereof, the driving method comprising a phase signal generating step, a phase signal processing step, a union step and an output step, wherein The phase signal generating step is for generating a plurality of phase signals, the phase signal processing step is for processing the Nth phase signal and the N+1th phase signal, and the outputting step is for outputting at least one driving voltage selection signal , a latch signal and at least one gate control signal. Thereby, it is judged that the frame rate of the electrophoretic display is maintained or lowered, thereby achieving the effect of reducing power consumption.

Description

Driving device for automatically adjusting frame rate of active matrix electrophoretic display and driving method thereof

The present invention relates to a driving device for a display and a driving method thereof, and more particularly to a driving device for automatically adjusting a frame rate of an active matrix electrophoretic display and a driving method thereof.

The general electro-optical display (EPD) technology is controlled by charged pigments to achieve a paper-like reading experience, and has a bistable characteristic, only when updating the screen. Only need to consume power, the screen can be maintained in the original state without updating, and it is a reflective display, which is not easy to make eyes tired and easy to read under strong light, and is suitable for use in book reading, product labeling and the like. That is to say, the driving principle of the electrophoretic display technology is to give different driving voltage waveforms for different screen states, including a front display screen (OLD Data) and an update display screen (NEW Data), for the front display screen. Different drive voltage signals are required to change to all combinations of the updated display. However, the application of the electrophoretic display technology pays more attention to the power consumption of the picture update. Therefore, if the power consumption during the picture update can be reduced, the number of updates at the same power amount can be increased, which is an increase for the application of the electronic product label. The number of years of use. Current electrophoretic display The picture update action is a method of using a fixed frame rate, and the frame rate affects the power consumption, the lower frame rate has a smaller power consumption; but the higher frame rate has a better display effect (more High contrast, more distinct graphics), but the power consumption is also large. Power consumption and display effects cannot be met at the same time.

Therefore, it is necessary to provide an improved driving device for automatically adjusting the frame rate of an active matrix electrophoretic display and a driving method thereof to solve the problems of the conventional technology.

The main object of the present invention is to provide a driving device for automatically adjusting a frame rate of an active matrix electrophoretic display and a driving method thereof, and processing the Nth phase signal and the N+1th phase signal by using a phase signal processor As a result of the processing, it is judged that the frame rate of the electrophoretic display is maintained or lowered, thereby achieving the effect of reducing power consumption.

To achieve the above objective, the present invention provides a driving apparatus for automatically adjusting a frame rate of an active matrix electrophoretic display, comprising a driving voltage signal storage, a phase generator, a phase signal processor, and a picture data storage unit. a timing control unit, a source driver, a gate driver and a latch signal generator; the driving voltage signal storage device stores at least one driving voltage signal, wherein the driving voltage signal is used to drive an electrophoretic display to display at least a color, and each of the plurality of signal segments of the driving voltage signal is divided by a plurality of frames; the phase generator is electrically connected to the driving voltage signal storage device for reading the driving voltage signals, and respectively The signal segment sequentially generates corresponding plurality of phase signals; the phase signal processor is electrically connected to the phase generator for receiving the phase signals, and the Nth phase signals and the N+ of the phase signals are 1 phase signal is processed to generate a processing result, where N is a positive integer; the picture data storage unit is used to store a picture Information; The timing control unit Electrically connecting the picture data storage unit, the phase generator and the phase signal processor for receiving the picture data, the phase signals and a final frame rate control signal, and calculating and outputting at least one driving voltage selection signal, a latching signal and at least one gate control signal; the source driver is electrically connected to the timing control unit, and the latching signal triggers an output voltage conversion to charge a pixel capacitor; the gate driver, the electrical Connecting the timing control unit, and controlling outputting a voltage to the active matrix type electrophoretic display according to the gate control signal; wherein the phase signal processor generates a frame rate for maintaining or decreasing the electrophoretic display according to the processing result A control signal.

In an embodiment of the invention, the phase signal processor compares whether the Nth phase signal and the N+1th phase signal of the phase signals are the same, and the processing result is generated.

In an embodiment of the present invention, the phase signal processor detects whether the Nth phase signal and the N+1th phase signal of the phase signals belong to the same driving voltage setting, and the processing result is generated. The driving voltage setting includes a set voltage and a frame number maintained by the set voltage.

In an embodiment of the present invention, the driving device for automatically adjusting the frame rate further includes a coupling circuit for combining a plurality of control signals generated by the plurality of driving voltage signals, and the operation is performed to obtain the final Frame rate control signal.

In an embodiment of the present invention, the driving device for automatically adjusting the frame rate further includes an intersection circuit for intersecting a plurality of control signals generated by the plurality of driving voltage signals, and calculating the final frame rate. Control signal.

In an embodiment of the invention, the latch signal generator is configured to output a latch signal to the source driver through the timing control unit.

In an embodiment of the present invention, the timing control unit is a single timing mode, and the control signal is used to control an existing frame rate for maintaining the timing mode, or reduce the existing frame rate of the timing mode by reducing the number of frames. .

In an embodiment of the invention, the timing control unit is a dual timing mode, and the control signal is used to control the replacement of the two timings.

To achieve the above objective, the present invention provides a driving method for automatically adjusting a frame rate of an active matrix electrophoretic display, comprising a phase signal generating step, a phase signal processing step, and an output step; the phase signal generating step is reading Taking a plurality of driving voltage signals, and sequentially generating corresponding plurality of phase signals for each of the plurality of signal segments of each driving voltage signal, wherein the signal segments are distinguished by a plurality of frames; the phase signal processing step is to receive the An equal phase signal, and processing the Nth phase signal and the N+1th phase signal of the phase signals to generate a processing result, and generating, according to the processing result, a one for maintaining or decreasing the electrophoretic display a control signal of the frame rate, wherein N is a positive integer; the outputting step is to receive a picture data, the phase signals, and the final frame rate control signal, and output at least one driving voltage selection signal, a latch signal, and at least one Gate control signal.

In an embodiment of the present invention, in the phase signal processing step, whether the Nth phase signal and the N+1th phase signal are the same are compared to generate the processing result.

In an embodiment of the present invention, the phase signal processing step is to detect whether the Nth phase signal and the N+1th phase signal of the phase signals belong to the same drive. The processing result is generated by the dynamic voltage setting, wherein the driving voltage setting includes a set voltage and a frame number maintained by the set voltage.

In an embodiment of the present invention, after the step of the phase signal processing, a step of combining is performed to combine the plurality of control signals generated by the plurality of the driving voltage signals to obtain the final frame. Rate control signal.

In an embodiment of the present invention, after the phase signal processing step, an intersection step is further included for intersecting a plurality of control signals generated by the plurality of the driving voltage signals, and the final frame rate control is obtained by the operation. Signal.

In an embodiment of the invention, in the phase signal processing step, reducing the frame rate of the electrophoretic display by 1/2 to 1/16 of the frame rate of the electrophoretic display.

As described above, the phase signal processor processes the Nth phase signal and the N+1th phase signal according to the phase signals corresponding to the signal segments of each driving voltage signal, and determines to maintain or lower the phase signal. The frame rate of the electrophoretic display and the reduction of the frame rate can reduce the number of conversions of the output voltage of the source driver and the gate driver, thereby achieving the effect of reducing power consumption.

100‧‧‧Automatically adjust frame rate drive

2‧‧‧Drive voltage signal storage

3‧‧‧Phase generator

4‧‧‧ phase signal processor

5‧‧‧Screen data storage unit

6‧‧‧Sequence Control Unit

71‧‧‧Source Driver

72‧‧‧gate driver

8‧‧‧Join circuit

8'‧‧‧Intersection circuit

9‧‧‧Latch signal generator

S201‧‧‧ Phase signal generation steps

S202‧‧‧ Phase signal processing steps

S203‧‧‧ joint steps

S203’‧‧‧ Intersection steps

S204‧‧‧Output steps

VCOM‧‧‧First drive voltage signal

VCOM-Ctrl‧‧‧ first control signal

White‧‧‧Second drive voltage signal

White-Ctrl‧‧‧second control signal

Black‧‧‧third drive voltage signal

Black-Ctrl‧‧‧ third control signal

Red‧‧‧fourth drive voltage signal

Red-Ctrl‧‧‧ fourth control signal

FrameRate-Ctrl‧‧‧ final frame rate control signal

1 is a schematic diagram of a preferred embodiment of a driving apparatus for automatically adjusting a frame rate of an active matrix type electrophoretic display according to the present invention; and FIG. 2 is an automatic adjustment frame rate of an active matrix type electrophoretic display according to the present invention. A flow chart of a preferred embodiment of the driving method; 3 is a schematic diagram of another preferred embodiment of a driving apparatus for automatically adjusting a frame rate of an active matrix type electrophoretic display according to the present invention; and FIG. 4 is an automatic adjustment frame rate of an active matrix type electrophoretic display of the present invention. A flow chart of another preferred embodiment of the driving method; FIGS. 5-8 are schematic diagrams showing driving voltage signals and control signals for driving the automatic frame rate of the active matrix type electrophoretic display; FIG. 9 is a schematic diagram of the control signal and the final frame rate control signal of the driving method for automatically adjusting the frame rate of the active matrix type electrophoretic display according to the present invention.

The above and other objects, features and advantages of the present invention will become more <RTIgt; Furthermore, the directional terms mentioned in the present invention, such as upper, lower, top, bottom, front, rear, left, right, inner, outer, side, surrounding, central, horizontal, horizontal, vertical, longitudinal, axial, Radial, uppermost or lowermost, etc., only refer to the direction of the additional schema. Therefore, the directional terminology used is for the purpose of illustration and understanding of the invention.

Referring to FIG. 1 , a preferred embodiment of the driving device 100 for automatically adjusting the frame rate of the active matrix electrophoretic display of the present invention is used to drive an active matrix electrophoretic display (not shown). The driving device 100 includes a driving voltage signal storage device 2, a phase generator 3, a phase signal processor 4, a picture data storage unit 5, a timing control unit 6, a source driver 71, and a gate driver. 72. A joint circuit 8 and a latch signal generator 9. The detailed construction, assembly relationship, and operation principle of each element will be described in detail below.

Referring to FIG. 1 , the driving voltage signal storage 2 stores a plurality of driving voltage signals, wherein each of the driving voltage signals is used to drive the electrophoretic display to display a color. For example, a first driving voltage signal is transmitted to the common driving electrode; a second driving voltage signal is used to drive the electrophoretic display to display white; a third driving voltage signal is used to drive the electrophoretic display to display black; and a fourth The driving voltage signal is used to drive the electrophoretic display to display red. In this embodiment, the plurality of signal segments of each driving voltage signal are distinguished by a plurality of frames.

Referring to FIG. 1 , the phase generator 3 is electrically connected to the driving voltage signal storage device 2 , and the phase generator 3 is configured to read the driving voltage signals of the driving voltage signal storage device 2 , and The corresponding plurality of phase signals are sequentially generated for each of the signal segments of each of the driving voltage signals.

Referring to FIG. 1 , the phase signal processor 4 is electrically connected to the phase generator 3, and the phase signal processor 4 is configured to receive the phase signals generated by the phase generator 3, and according to each of the driving signals. The phase signals corresponding to the signal segments of the voltage signal compare whether the Nth phase signal and the N+1th phase signal in the phase signals are the same, thereby generating a processing result. For example, generating a first processing result according to the first driving voltage signal, generating a second processing result according to the second driving voltage signal, generating a third processing result according to the third driving voltage signal, and according to the fourth driving The voltage signal produces a fourth processing result. The above N is a positive integer of one or more, and is, for example, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, and the like.

In addition, in other embodiments, the phase signal processor 4 may also detect whether the Nth phase signal and the N+1th phase signal of the phase signals belong to the same driving voltage setting, and generate the processing. As a result, the driving voltage setting includes a set voltage and a frame number maintained by the set voltage.

It should be noted that the content storage format of the driving voltage signal storage 2 can be divided into three types. The first type is all expanded voltage settings, and each driving voltage setting represents an output voltage setting of one frame, for example: +11V, +11V, +11V, -11V, -11V, -11V, -11V...; the second is set for each driving voltage, each driving voltage is set to include a set voltage, and one of the set voltages needs to be maintained. The number of frames, for example: (+11V, 3 Frames), (-11V, 4 Frames), (+11V, 3 Frames)...; the third is for each form of driving voltage setting, each driving voltage The setting includes a set voltage, a frame number to be maintained by the set voltage, and a repetition number of the group of the driving voltage setting, for example: {(+11V, 3 Frames), (-11V, 4 Frames), Repeat 2 times }. The content storage format of the first to third types of the driving voltage signal storage 2 can be generated by comparing whether the Nth phase signal and the N+1th phase signal of the phase signals are the same; The content storage format of the second and third types of the driving voltage signal storage 2 can be generated by detecting whether the Nth phase signal and the N+1th phase signal of the phase signals belong to the same driving voltage setting. The result of this processing.

Referring to FIG. 1 , the phase signal processor 4 then calculates a control signal for maintaining or decreasing a frame rate of the electrophoretic display according to each processing result, wherein the combination circuit 8 is And a plurality of control signals generated by the plurality of the driving voltage signals are combined to obtain a final frame rate control signal, wherein a high level of the final frame rate control signal represents a sustained frame rate; the final frame rate The low level of the control signal represents a reduction in the frame rate. For example, calculating a first control signal according to the first processing result; calculating a second control signal according to the second processing result; calculating a third control signal according to the third processing result; and according to the fourth processing As a result, a fourth control signal is calculated. Then, the first control signal, the second The control signal, the third control signal and the fourth control signal are combined to obtain the final frame rate control signal.

In another preferred embodiment, as shown in FIG. 3, an intersection circuit 8' of the automatic adjustment frame rate driving device 100 is configured to perform a plurality of control signals generated by a plurality of the driving voltage signals. The intersection is obtained to obtain a final frame rate control signal, wherein the high level of the final frame rate control signal represents a reduced frame rate; the low level of the final frame rate control signal represents a sustained frame rate.

Referring to FIG. 1 , the screen data storage unit 5 is configured to store a screen data. In the embodiment, the screen data storage unit 5 is a display RAM for storing the image to be displayed. Screen data of the electrophoretic display.

The timing control unit 6 is electrically connected to the picture data storage unit 5, the phase generator 3 and the phase signal processor 4, and the timing control unit 6 is configured to receive the picture data. The equal phase signal and the final frame rate control signal are operated to output at least one driving voltage selection signal, a latch signal and at least one gate control signal. In addition, the latch signal generator 9 is configured to output a latch signal (Source Latch) to the source driver 71 through the timing control unit 6. In this embodiment, the timing control unit 6 is a single timing mode, and the control signal is used to control an existing frame rate for maintaining the timing mode, or to reduce the existing frame rate of the timing mode by reducing the number of frames; The control unit 6 is in a dual timing mode, and the control signal is used to control the replacement of the two timings.

Referring to FIG. 1 , the source driver 71 is electrically connected to the timing control unit 6 , and the source driver 71 is configured to receive the driving voltage selection signal, and trigger an output voltage conversion by the latch signal. And charge a pixel capacitor (not shown). The gate driver 72 The timing control unit 6 is electrically connected, and outputs a voltage to the active matrix electrophoretic display according to the gate control signal.

According to the above structure, the phase generator 3 sequentially generates corresponding plurality of phase signals for each of the plurality of signal segments of the driving voltage signal; and then the phase signal processor 4 uses the phase signal processor 4 according to each of the driving voltage signals. The phase signal corresponding to the signal segment processes the Nth phase signal and the N+1th phase signal to generate the processing results; and then calculates the processing result generated by each driving voltage signal to maintain or The control signal for reducing the frame rate of the electrophoretic display; finally, the combination circuit 8 is used to combine a plurality of control signals generated by the plurality of driving voltage signals to obtain a final frame rate control signal. The waveform of each driving voltage signal is reduced without any change, thereby achieving the effect of reducing power consumption.

With the above design, the phase signal processor 4 processes the Nth phase signal and the N+1th phase signal according to the phase signals corresponding to the signal segments of each driving voltage signal, and determines to maintain Or reducing the frame rate of the electrophoretic display can reduce the number of conversions of the output voltage of the source driver 71 and the gate driver 72, thereby achieving the effect of reducing power consumption.

Referring to FIG. 2 and FIG. 1 , a preferred embodiment of the method for automatically adjusting the frame rate of the active matrix electrophoretic display according to the present invention is the driving device 100 for automatically adjusting the frame rate. The display driving of the electrophoretic display comprises a phase signal generating step S201, a phase signal processing step S202, a union step S203 and an output step S204. The operation of each step will be described in detail below.

Referring to FIG. 2 and in conjunction with FIG. 1, in the phase signal generating step S201, a plurality of driving voltage signals of a driving voltage signal storage 2 are read by a phase generator 3, and respectively driven for each driving. The plurality of signal segments of the voltage signal sequentially generate corresponding plurality of phase signals, wherein the signal segments are distinguished by a plurality of frames.

With reference to FIG. 2 and in conjunction with FIG. 1, in the phase signal processing step S202, the phase signal processor 4 receives the phase signals of the phase generator 3, and according to each of the driving voltage signals, The phase signal corresponding to the signal segment compares whether the Nth phase signal and the N+1th phase signal are the same, thereby generating a processing result. Then, a control signal for maintaining or decreasing a frame rate of the electrophoretic display is calculated according to the processing result generated by each driving voltage signal. For example, as shown in FIG. 5, a first control signal VCOM-Ctrl is calculated according to a first processing result generated by a first driving voltage signal VCOM; as shown in FIG. 6, according to a second driving voltage signal A second control result generated by White calculates a second control signal White-Ctrl; as shown in FIG. 7, a third control signal is calculated according to a third processing result generated by a third driving voltage signal Black. Black-Ctrl; and as shown in FIG. 8, a fourth control signal Red-Ctrl is calculated according to a fourth processing result generated by a fourth driving voltage signal Red, wherein the frame rate of the electrophoretic display is lowered to maintain The frame rate of the electrophoretic display is 1/2 to 1/16, wherein the control signals maintain the original frame rate at a high level, and the control signals are at a low level to reduce the frame rate.

In addition, in other embodiments, the phase signal processing step S202 may also detect whether the Nth phase signal and the N+1th phase signal in the phase signals belong to the same driving voltage setting, and generate the processing result. The driving voltage setting includes a set voltage and a number of frames maintained by the voltage setting.

Referring to FIG. 2 and FIG. 1 together, in the association step S203, a plurality of control signals generated by the plurality of driving voltage signals are combined by a combination circuit 8 to obtain a final result. The frame rate control signal, wherein the high level of the final frame rate control signal represents a sustained frame rate; the low level of the final frame rate control signal represents a reduced frame rate. For example, as shown in FIG. 9, the first control signal VCOM-Ctrl, the second control signal White-Ctrl, the third control signal Black-Ctrl, and the fourth control signal Red-Ctrl are combined to obtain the final Frame rate control signal FrameRate-Ctrl.

In another preferred embodiment, referring to FIG. 4 and in conjunction with FIG. 3, an intersection step S203' of the method for automatically adjusting the frame rate is performed after the phase signal processing step S202, using an intersection circuit. 8' combines a plurality of control signals generated by the plurality of driving voltage signals to obtain a final frame rate control signal, wherein a high level of the final frame rate control signal represents a reduced frame rate; the final frame rate The low level of the control signal represents the maintenance of the frame rate.

Referring to FIG. 2 and FIG. 1 , in the output step S204 , a screen data, the phase signals, and the final frame rate control signal FrameRate-Ctrl are received, and at least one driving voltage selection signal is outputted. Latch signal and at least one gate control signal.

As described above, the phase signal processor 4 processes the Nth phase signal and the N+1th phase signal according to the phase signals corresponding to the signal segments of each of the driving voltage signals, and determines whether to maintain or By reducing the frame rate of the electrophoretic display, the number of conversions of the output voltages of the source driver 71 and the gate driver 72 can be reduced, and the power consumption can be reduced.

Although the present invention has been disclosed in its preferred embodiments, it is not intended to limit the invention, and any person skilled in the art can make it without departing from the spirit and scope of the invention. Various changes and modifications are intended to be included within the scope of the appended claims.

Claims (8)

The driving device for automatically adjusting the frame rate of the active matrix electrophoretic display comprises: a driving voltage signal storage device for storing at least one driving voltage signal, wherein the driving voltage signal is used for driving an electrophoretic display to display at least one color, And each of the plurality of signal segments of the driving voltage signal is divided by a plurality of frames; a phase generator is electrically connected to the driving voltage signal storage for reading the driving voltage signal, and respectively corresponding to the signal segments And generating a corresponding plurality of phase signals; a phase signal processor electrically connected to the phase generator for receiving the phase signals, and the Nth phase signals and the N+1th of the phase signals The phase signal is processed to generate a processing result, wherein N is a positive integer, wherein the phase signal processor detects whether the Nth phase signal and the N+1th phase signal of the phase signals belong to the same driving voltage. Setting, and generating the processing result, wherein the driving voltage setting includes a set voltage and a frame number maintained by the set voltage; And a timing control unit electrically connected to the picture data storage unit, the phase generator and the phase signal processor for receiving the picture data, the phase signals and a final frame rate Controlling the signal, and calculating and outputting at least one driving voltage selection signal, a latching signal and at least one gate control signal; a source driver electrically connected to the timing control unit, and the latch signal triggers an output voltage conversion to charge a pixel capacitor; and a gate driver electrically connected to the timing control unit, and according to the The gate control signal controls a voltage output to the active matrix type electrophoretic display; wherein the phase signal processor generates a control signal for maintaining or decreasing a frame rate of the electrophoretic display according to the processing result. The driving device for automatically adjusting the frame rate of the active matrix type electrophoretic display according to claim 1, further comprising a coupling circuit for generating a plurality of control signals generated by the plurality of driving voltage signals The union is performed, and the final frame rate control signal is obtained by the operation. The driving device for automatically adjusting the frame rate of the active matrix electrophoretic display according to claim 1, further comprising an intersection circuit for performing a plurality of control signals generated by the plurality of driving voltage signals Intersection, and the operation obtains the final frame rate control signal. The driving device for automatically adjusting the frame rate of the active matrix electrophoretic display comprises: a driving voltage signal storage device for storing at least one driving voltage signal, wherein the driving voltage signal is used for driving an electrophoretic display to display at least one color, And each of the plurality of signal segments of the driving voltage signal is divided by a plurality of frames; a phase generator is electrically connected to the driving voltage signal storage for reading the driving voltage signal, and respectively corresponding to the signal segments Generating a corresponding plurality of phase signals; a phase signal processor electrically connected to the phase generator for receiving the phase signals, and processing the Nth phase signal and the N+1th phase signal of the phase signals to generate a processing result Where N is a positive integer, wherein the phase signal processor compares whether the Nth phase signal and the N+1th phase signal in the phase signals are the same, and the processing result is generated; a picture data storage unit, For storing a picture data; a timing control unit electrically connecting the picture data storage unit, the phase generator and the phase signal processor for receiving the picture data, the phase signals and a final frame rate control signal And outputting at least one driving voltage selection signal, a latching signal and at least one gate control signal, wherein the timing control unit is a single timing mode, wherein the control signal is used to control an existing frame rate for maintaining the timing mode, or Reducing the existing frame rate of the timing mode by reducing the number of frames; a source driver electrically connected to the timing control unit and being touched by the latch signal An output voltage is converted to charge a pixel capacitor; and a gate driver is electrically connected to the timing control unit, and outputs a voltage to the active matrix type electrophoretic display according to the gate control signal; wherein the phase signal The processor generates a control signal for maintaining or decreasing a frame rate of the electrophoretic display according to the processing result. A driving device for automatically adjusting a frame rate of an active matrix electrophoretic display, comprising: a driving voltage signal storage device stores at least one driving voltage signal, wherein the driving voltage signal is used to drive an electrophoretic display to display at least one color, and each of the plurality of signal segments driving the voltage signal is distinguished by a plurality of frames; The phase generator is electrically connected to the driving voltage signal storage device for reading the driving voltage signal, and sequentially generating corresponding plurality of phase signals for the signal segments respectively; a phase signal processor electrically connecting the signal a phase generator for receiving the phase signals, and processing the Nth phase signal and the N+1th phase signal of the phase signals to generate a processing result, where N is a positive integer, where The phase signal processor compares whether the Nth phase signal and the N+1th phase signal of the phase signals are the same, and generates the processing result; a picture data storage unit for storing a picture data; and a timing control The unit is electrically connected to the picture data storage unit, the phase generator and the phase signal processor for receiving the picture data and the phase signals a final frame rate control signal, and an output of at least one driving voltage selection signal, a latch signal, and at least one gate control signal. The timing control unit is a dual timing mode, and the control signal is used to control the two timings. Replacement; a source driver electrically connected to the timing control unit, and the latch signal triggers an output voltage conversion to charge a pixel capacitor; and a gate driver electrically connected to the timing control unit, and Controlling outputting a voltage to the active matrix electrophoretic display according to the gate control signal; The phase signal processor generates a control signal for maintaining or decreasing a frame rate of the electrophoretic display according to the processing result. A driving method for automatically adjusting a frame rate of an active matrix electrophoretic display comprises: a phase signal generating step of reading at least one driving voltage signal, and sequentially generating corresponding signals for the plurality of signal segments of the driving voltage signal a plurality of phase signals, wherein the signal segments are distinguished by a plurality of frames; a phase signal processing step of receiving the phase signals and the Nth phase signals and the N+1th phase signals of the phase signals Processing, generating a processing result, and generating a control signal for maintaining or decreasing a frame rate of the electrophoretic display according to the processing result, wherein N is a positive integer, and detecting in the phase signal processing step Whether the Nth phase signal and the N+1th phase signal of the phase signals belong to the same driving voltage setting, and the processing result is generated, wherein the driving voltage setting includes a set voltage and a frame number maintained by the set voltage And an output step of receiving a picture data, the phase signals, and a final frame rate control signal to output at least one driving voltage selection signal At least one latch signal and a gate control signal. A driving method for automatically adjusting a frame rate of an active matrix electrophoretic display, comprising: a phase signal generating step of reading at least one driving voltage signal and sequentially generating a plurality of corresponding phase signals for the plurality of signal segments of the driving voltage signal, wherein the signal segments are distinguished by a plurality of frames; a signal processing step of receiving the phase signals, and processing the Nth phase signal and the N+1th phase signal of the phase signals to generate a processing result, and generating, according to the processing result, a control signal for reducing a frame rate of the electrophoretic display, wherein N is a positive integer, and in the phase signal processing step, comparing whether the Nth phase signal and the N+1th phase signal are the same, the processing is generated. a result, a union step of combining a plurality of control signals generated by the plurality of the driving voltage signals to obtain the final frame rate control signal; and an outputting step of receiving a picture data, the first The phase signal and a final frame rate control signal output at least one driving voltage selection signal, a latch signal, and at least one gate control signal. A driving method for automatically adjusting a frame rate of an active matrix electrophoretic display comprises: a phase signal generating step of reading at least one driving voltage signal, and sequentially generating corresponding signals for the plurality of signal segments of the driving voltage signal a plurality of phase signals, wherein the signal segments are distinguished by a plurality of frames; a phase signal processing step of receiving the phase signals and the Nth phase signals and the N+1th phase signals of the phase signals Processing to generate a processing result, which is generated according to the processing result to maintain or reduce the a control signal of a frame rate of the electrophoretic display, wherein N is a positive integer, and in the phase signal processing step, comparing whether the Nth phase signal and the N+1th phase signal are the same, the processing result is generated; An intersection step of intersecting a plurality of control signals generated by the plurality of the driving voltage signals to obtain the final frame rate control signal; and an outputting step of receiving a picture data, the phase signals, and a The final frame rate control signal outputs at least one driving voltage selection signal, a latch signal, and at least one gate control signal.