TWI633822B - Circuit board unit and method for manufacturing the same - Google Patents

Abstract

A circuit board unit includes first and second dielectric layers, first, second, and third circuit layers and a plurality of first and second via holes. The first dielectric layer has a top surface and a first side surface. The first circuit layer is disposed in the first dielectric layer. The second dielectric layer is disposed on the top surface of the first dielectric layer, wherein the second dielectric layer has a bottom surface and a second side surface, the bottom surface directly contacting the top surface of the first dielectric layer, and the top surface and the first side There is a spacing between a joint and a second joint of the bottom surface and the second side. The second circuit layer is disposed on the top surface of the first dielectric layer and the second dielectric layer. The third circuit layer is disposed on the second dielectric layer. The first via hole is disposed in the first dielectric layer and connects the first and second circuit layers. The second via hole is disposed in the second dielectric layer and connects the second and third circuit layers.

Description

Circuit board unit and manufacturing method thereof

The present invention relates to a circuit board unit and a method of fabricating the same.

With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional, high-performance research and development. In order to meet the requirements of high integration and miniaturization of semiconductor components, the requirements for circuit boards are becoming higher and higher. For example, the track pitch (Pitch) requirements on the board are getting smaller and smaller, the board thickness requirements are getting thinner, and the outer edge shape of the board must match the other design of the product.

In order to further improve the characteristics of the circuit board, the related fields are not intensively developed. How to provide a circuit board with better characteristics is one of the current important research and development topics, and it has become an urgent target for improvement in related fields.

One aspect of the present invention provides a circuit board unit and a method of fabricating the same to reduce process error or reduce manufacturing cost. In addition, the outer edge shape of the board unit may be a regular or irregular shape.

According to an embodiment of the invention, a method of fabricating a circuit board unit includes the following steps. First, a wiring layer is formed on the carrier board. Then, a first dielectric layer is formed on the wiring layer and the carrier board. Then, a plurality of first openings and a plurality of first isolation channels are formed in the first dielectric layer, wherein the first openings expose the circuit layers, and the first isolation channels expose the carrier. Then, a plurality of first via holes are formed on the first circuit layer and the first dielectric layer, and a second circuit layer is formed on the first dielectric layer and the first via hole. Then, a second dielectric layer is formed on the second circuit layer and the first dielectric layer. Then, a plurality of second openings and a plurality of second isolation channels are formed in the second dielectric layer, wherein the second openings expose the second circuit layer, and the second isolation channels communicate with the first isolation channels, thereby exposing the carrier. Then, a plurality of second via holes are formed on the second circuit layer and the second dielectric layer, and a third circuit layer is formed on the second dielectric layer and the second via hole. Finally, the carrier board is removed, and a plurality of circuit board units are formed by dividing the first isolation track and the second isolation track.

In one or more embodiments of the present invention, in the step of removing the carrier, the release film disposed between the carrier and the first dielectric layer is irradiated with ultraviolet light, thereby disengaging the circuit board unit. Carrier board.

In one or more embodiments of the invention, in the step of removing the carrier plate, the ultraviolet laser is illuminated from a side of the carrier plate relative to the circuit board unit.

In one or more embodiments of the invention, the carrier plate is made of glass or quartz glass.

In one or more embodiments of the present invention, the material of the first dielectric layer is a photosensitive dielectric material.

In one or more embodiments of the invention, the first isolation track is formed by exposure development.

In one or more embodiments of the present invention, the method further includes baking the first dielectric layer after the first opening is formed with the first isolation trench.

In one or more embodiments of the present invention, the following steps are included in the step of forming the first via and the second wiring layer. First, a photoresist is formed on the first dielectric layer, wherein the photoresist covers the first isolation track. Then, a plurality of third openings are formed in the photoresist, wherein a portion of the third openings exposes the first dielectric layer, and a portion of the third openings communicates with the first openings, thereby exposing the first circuit layer. Next, a first via hole is formed in the first opening, and a second wiring layer is formed in the third opening. Finally, the photoresist layer is removed.

According to another embodiment of the present invention, a circuit board unit includes a first dielectric layer, a first circuit layer, a second dielectric layer, a second circuit layer, a third circuit layer, a plurality of first vias, and a plurality of Two vias. The first dielectric layer has at least one top surface and at least one first side surface. The first circuit layer is disposed in the first dielectric layer. The second dielectric layer is disposed on the top surface of the first dielectric layer, wherein the second dielectric layer has at least one bottom surface and at least one second side surface, the bottom surface directly contacting the top surface of the first dielectric layer, the first dielectric layer There is a spacing between the top surface of the layer and the first junction of the first side and the second junction of the second dielectric layer and the second side. The second circuit layer is disposed on the top surface of the first dielectric layer and the second dielectric layer. The third circuit layer is disposed on the second dielectric layer. The first via hole is disposed in the first dielectric layer and connects the first circuit layer and the second circuit layer. The second via hole is disposed in the second dielectric layer and connects the second circuit layer and the third circuit layer.

In one or more embodiments of the invention, the first side and the second side are not interconnected.

Separating a plurality of circuit board units by forming a first isolation track and a second isolation track, because the shapes of the first isolation track and the second isolation track can be determined according to the definition of the mask, so if the first isolation path and the first isolation path are The first isolation track and the second isolation track are viewed above or below the two isolation channels. The shapes of the first isolation track and the second isolation track may be irregular shapes formed by straight lines and/or curved lines. Thus, if the circuit board unit is viewed from above or below the circuit board unit, the outer edge shape of the circuit board unit may be a regular shape (for example, a rectangular shape) or an irregular shape (for example, a shape of a maple leaf), and thus may conform to some special shapes. Claim.

Further, if a milling cutter process is used to cut and form a circuit board unit, since the milling cutter body wears during cutting, an error occurs in cutting. By forming the isolation track by means of exposure development, since the precision of exposure development is high, the error can be effectively reduced, so that the overall error is less than ±10 μm or ±20 μm. In addition, the manner in which the plurality of circuit board units are separated by forming the first isolation track and the second isolation track can effectively reduce the cost compared to the method of cutting using the laser ablation process.

100‧‧‧PCB unit

101‧‧‧Loading board

102‧‧‧ release film

103‧‧‧ seed layer

111, 112, 113‧‧‧ circuit layer

121, 122‧‧‧ dielectric layer

121c, 122c‧‧‧ joints

121i, 122i‧‧‧ isolation road

121o, 122o, 901o, 902o‧‧

121s, 122s‧‧‧ side

121t‧‧‧ top surface

122b‧‧‧ bottom

131, 132‧‧‧through holes

901, 902‧‧‧ photoresist

903‧‧‧UV laser

G‧‧‧ spacing

1A to 1N are cross-sectional views showing respective steps of a process of a circuit board unit according to an embodiment of the present invention.

The embodiments of the present invention are disclosed in the following drawings, and the details of However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.

In addition, relative terms such as "lower" or "bottom" and "upper" or "top" are used to describe the relationship of one element to another in the figures. Relative vocabulary is used to describe different orientations of the device other than those described in the drawings. For example, if the device in one of the figures is turned over, the elements will be described as being located on the "lower" side of the other elements. The exemplary vocabulary "below" may include both "lower" and "upper" orientations depending on the particular orientation of the drawings. Similarly, if the device in one of the figures is turned over, the element will be described as being "below" or "below" the other elements. The exemplary vocabulary "below" or "below" can include both "upper" and "upper" orientations.

1A to 1N are cross-sectional views showing respective steps of a process of the circuit board unit 100 according to an embodiment of the present invention. First, as shown in FIG. 1A, a carrier board 101 is provided. Specifically, the material of the carrier plate 101 may be glass or quartz glass.

Then, a release film 102 is formed on the carrier sheet 101. Specifically, the material of the release film 102 may be PE, PET, OPP or a composite release film such as Cyclohexanone/Gamma-Butyrolactone (GBL, γ-butyrolactone) or Formyldiethylamine (2B). The release film 102 can be formed by coating or lamination. The form of the release film 102 can be formed by lamination or lapy glycol glycol monomethyl ether acetate (PGMEA, propylene glycol methyl ether acetate).

As shown in FIG. 1B, a seed layer 103 is formed on the release film 102 (above the carrier plate 101). Specifically, the material of the seed layer 103 may be titanium/copper. Specifically, the seed layer 103 may be formed by sputtering.

As shown in FIG. 1C, a photoresist 901 is formed on the seed layer 103 (above the carrier plate 101). In the present embodiment, the photoresist 901 may be a dry film, but is not limited thereto. In other embodiments, the photoresist 901 can be a Wet Film.

As shown in FIG. 1D, a plurality of openings 901o are formed in the photoresist 901. The seed layer 103 is exposed to the opening 901o. Specifically, the formation of the opening 901o is exposure development.

As shown in FIG. 1E, the wiring layer 111 is formed in the opening 901o, thereby forming the wiring layer 111 on the seed layer 103 (above the carrier plate 101). Specifically, the material of the circuit layer 111 may be copper. The formation method of the wiring layer 111 may be electroplating.

As shown in FIG. 1F, the photoresist 901 is removed. Then, as depicted in FIG. 1G, the seed layer 103 not covered by the wiring layer 111 is removed.

As shown in FIG. 1H, a dielectric layer 121 is formed on the wiring layer 111 and the release film 102 (above the carrier plate 101). Specifically, the material of the dielectric layer 121 is a Photoimageable Dielectric (PID). The dielectric layer 121 can be formed in a lamination manner.

As shown in FIG. 1I, a plurality of openings 121o and a plurality of isolated tracks 121i are formed in the dielectric layer 121. The opening 121o exposes the wiring layer 111, and the isolation track 121i exposes the release film 102 (or the bare carrier plate 101). In other words, the isolation track 121i penetrates the dielectric layer 121, and the isolation track 121i separates the dielectric layer 121 into different portions that are not connected to each other. Specifically, the formation of the opening 121o and the isolation track 121i is exposure development. In addition, after the opening 121o and the isolation track 121i are formed, the dielectric layer 121 is baked to harden the dielectric layer 121.

The width of the isolation track 121i can be from about 30 microns to about 80 microns. Alternatively, the isolation track 121i may have a width of from about 80 microns to about 100 microns. Alternatively, the isolation track 121i may have a width of from about 100 microns to about 120 microns. The alignment accuracy of the isolation track 121i can be about ± 2 microns. It should be understood that the specific embodiments of the above-mentioned isolation channel 121i are merely illustrative and are not intended to limit the present invention. Those having ordinary knowledge in the technical field of the present invention should flexibly select the specific implementation of the isolation channel 121i according to actual needs. the way.

As shown in FIG. 1J, a photoresist 902 is formed on the dielectric layer 121, wherein the photoresist 902 covers the isolation track 121i. In the present embodiment, the photoresist 902 can be a dry film, and thus the photoresist 902 does not substantially fall into the isolation track 121i, but is not limited thereto. In other embodiments, the photoresist 902 can be a wet film.

Then, a plurality of openings 902o are formed in the photoresist 902, wherein a portion of the openings 902o exposes the dielectric layer 121, and a portion of the openings 902o communicates with the openings 121o, thereby exposing the wiring layer 111.

As shown in FIG. 1J and FIG. 1K, the via hole 131 is formed in the opening 121o, and the wiring layer 112 is formed in the opening 902o. Then, the photoresist 902 is removed. Specifically, the material of the circuit layer 112 and the via hole 131 may be copper. The method of forming the wiring layer 111 and the via hole 131 may be electroplating, and the wiring layer 111 and the via hole 131 may be formed in the same electroplating process. In addition, it should be noted that a seed layer (not shown) may be formed before the formation of the circuit layer 112 and the via hole 131, and then the seed layer not covered by the circuit layer 112 is removed after the photoresist 902 is removed (not drawn) Show).

As shown in FIG. 1L, a dielectric layer 122 is formed on the wiring layer 112 and the dielectric layer 121. Specifically, the material of the dielectric layer 122 is a photosensitive dielectric material. The dielectric layer 122 can be formed by lamination.

Then, a plurality of openings 122o and a plurality of isolation channels 122i are formed in the dielectric layer 121, wherein the openings 122o expose the circuit layer 112, and the isolation channels 122i communicate with the isolation tracks 121i, thereby exposing the release film 102 (or the bare carrier plate 101). In other words, the isolation track 121i and the isolation track 122i penetrate the dielectric layer 121 and the dielectric layer 122, and the isolation track 121i and the isolation track 122i separate the dielectric layer 121 from the dielectric layer 122 into different portions that are not connected to each other. Specifically, the formation of the opening 122o and the isolation track 122i is exposure development. In addition, after the opening 122o and the isolation track 122i are formed, the dielectric layer 122 is baked to harden the dielectric layer 122.

The isolation track 122i can have a width of from about 30 microns to about 80 microns. Alternatively, the isolation track 122i can have a width of from about 80 microns to about 100 microns. Alternatively, the isolation track 122i can have a width of from about 100 microns to about 120 microns. The alignment accuracy of the isolation track 122i can be about ± 2 microns. It should be understood that the specific embodiments of the above-mentioned isolation channel 122i are merely illustrative and are not intended to limit the present invention. Those having ordinary knowledge in the technical field of the present invention should flexibly select the specific implementation of the isolation channel 122i according to actual needs. the way.

It should be noted that the isolated tracks 121i, 122i are not fully aligned. Further, the width of the isolation tracks 121i, 122i may be approximately the same. Alternatively, the width of the isolation track 121i is greater than the width of the isolation track 122i. Alternatively, the width of the isolation track 122i is greater than the width of the isolation track 121i.

In addition, since the isolation tracks 121i, 122i are formed by two different exposure development processes, a discontinuous phenomenon can be observed in the material state between the side surface of the isolation track 121i and the side surface of the isolation track 122i. Further, the material state of the side surfaces of the isolation tracks 121i, 122i is relatively smooth compared to the material state of the side surface of the isolation track formed by the laser ablation process or the milling process.

Then, a plurality of via holes 132 are formed on the circuit layer 112 and the dielectric layer 122 (in the opening 122o), and a wiring layer 113 is formed on the dielectric layer 122 and the via hole 132. Specifically, the material of the wiring layer 113 and the via hole 132 may be copper. The circuit layer 113 and the via hole 132 may be formed by electroplating, and the wiring layer 113 and the via hole 132 may be formed in the same electroplating process. In addition, it should be noted that the method of forming the wiring layer 113 and the via hole 132 is basically the same as the method of forming the wiring layer 112 and the via hole 131. with. Specifically, a seed layer (not shown) may be formed first. Then, a photoresist (not shown) is formed on the dielectric layer 122, wherein a photoresist (not shown) covers the isolation track 122i. Then, a plurality of openings (not shown) are formed in the photoresist (not shown), wherein a portion of the opening (not shown) exposes the dielectric layer 122, and a portion of the opening (not shown) communicates with the opening 122o, thereby exposing the exposed line. Layer 112. Next, the via hole 132 and the wiring layer 113 are formed. After that, the photoresist is removed (not shown). Finally, the seed layer (not shown) that is not covered by the circuit layer 113 is removed.

As shown in FIG. 1M and FIG. 1N , the release film 102 disposed between the carrier plate 101 and the dielectric layer 121 is irradiated with the ultraviolet light ray 903 , thereby being disposed on the release film 102 relative to the carrier plate 101 . All of the components on one side are detached from the carrier plate 101. Then, the carrier board 101 is removed, and all the elements disposed on one side of the release film 102 with respect to the carrier board 101 are divided by the isolation tracks 121i, 122i to form a plurality of circuit board units 100. More specifically, the ultraviolet light laser 903 is irradiated from the side of the carrier board 101 with respect to the circuit board unit 100.

It should be noted that the material of the carrier plate 101 does not necessarily need to be glass or quartz glass, and the material transparent to the ultraviolet laser 903 may be the material of the carrier plate 101.

As shown in FIG. 1J, in embodiments where the photoresist 902 is a wet film, there may be a small portion of the photoresist 902 trapped in the isolation track 121i, but after development, substantially all of the light trapped in the isolation track 121i Block 902 will be removed. Similarly, in the step of forming the isolation track 122i, if the photoresist is a wet film, almost all of the photoresist trapped in the isolation track 122i is removed.

After the photoresist is removed, there may still be traces of photoresist remaining in the isolation tracks 121i, 122i. However, as shown in FIG. 1M, when the ultraviolet laser 903 irradiates the release film 102, the ultraviolet laser 903 ablates the trace photoresist remaining in the isolation paths 121i, 122i. Thus, there will be no photoresist remaining in the isolation tracks 121i, 122i.

In addition, it should be noted that the number of dielectric layers and circuit layers may vary according to the actual needs of the circuit board unit 100, and is not necessarily limited to the description of the foregoing embodiments.

The plurality of circuit board units 100 are separated by forming the isolated tracks 121i, 122i. Since the shapes of the isolated tracks 121i, 122i can be determined according to the definition of the mask, if the isolation track 121i is viewed from above or below the isolation tracks 121i, 122i The shape of the isolation tracks 121i, 122i may be an irregular shape composed of a straight line and/or a curved line. Thus, if the circuit board unit 100 is viewed from above or below the circuit board unit 100, the outer edge shape of the circuit board unit 100 may be a regular shape (for example, a rectangular shape) or an irregular shape (for example, a shape of a maple leaf), and thus may conform to some Special shape requirements.

Further, if a milling cutter process is used to cut and form a circuit board unit, since the milling cutter body wears during cutting, an error occurs in cutting. By forming the isolation tracks 121i, 122i by means of exposure development, since the precision of exposure development is high, the error can be effectively reduced, so that the overall error is less than ±10 μm or ±20 μm. In addition, the isolation track 121i is formed by using a method of cutting using a laser ablation process. The manner in which the plurality of circuit board units 100 are separated by 122i can effectively reduce the cost.

Another embodiment of the present invention provides a circuit board unit 100. As shown in FIG. 1N, the circuit board unit 100 includes dielectric layers 121 and 122, circuit layers 111, 112, and 113, a plurality of via holes 131, and a plurality of via holes 132. The dielectric layer 121 has at least one top surface 121t and at least one side surface 121s. The wiring layer 111 is disposed in the dielectric layer 121. The dielectric layer 122 is disposed on the top surface 121t of the dielectric layer 121. The dielectric layer 122 has at least one bottom surface 122b and at least one side surface 122s. The bottom surface 122b directly contacts the top surface 121t of the dielectric layer 121. The dielectric layer 121 There is a gap G between the connection 121c of the top surface 121t and the side surface 121s and the connection portion 122c of the bottom surface 122b of the dielectric layer 122 and the side surface 122s. The circuit layer 112 is disposed on the top surface 121t of the dielectric layer 121 and the dielectric layer 122. The wiring layer 113 is disposed on the dielectric layer 122. The via hole 131 is disposed in the dielectric layer 121 and connects the wiring layer 111 and the wiring layer 112. The via hole 132 is disposed in the dielectric layer 122 and connects the wiring layer 112 and the wiring layer 113.

The side surface 121s and the side surface 122s are not connected to each other. Further, a discontinuous phenomenon can be observed in the material state between the side surface 121s and the side surface 122s. In addition, the material state of the side surface 121s and the side surface 122s is relatively smooth compared to the material state of the side surface formed by the laser ablation process or the milling cutter process.

The material of the dielectric layers 121 and 122 is a photosensitive dielectric material. It should be understood that the materials of the dielectric layers 121 and 122 mentioned above are merely examples, and It is not intended to limit the present invention. Those having ordinary knowledge in the technical field of the present invention should flexibly select the materials of the dielectric layers 121 and 122 according to actual needs.

Separating a plurality of circuit board units by forming an isolation track, since the shape of the isolation track can be determined according to the definition of the mask, so if the isolation track is viewed from above or below the isolation track, the shape of the isolation track can be straight and/or The irregular shape of the curve. Thus, if the circuit board unit is viewed from above or below the circuit board unit, the outer edge shape of the circuit board unit may be a regular shape (for example, a rectangular shape) or an irregular shape (for example, a shape of a maple leaf), and thus may conform to some special shapes. Claim.

Further, if a milling cutter process is used to cut and form a circuit board unit, since the milling cutter body wears during cutting, an error occurs in cutting. By forming the isolation track by means of exposure development, since the precision of exposure development is high, the error can be effectively reduced, so that the overall error is less than ±10 μm or ±20 μm. In addition, the manner in which a plurality of circuit board units are separated by forming an isolation track can be effectively reduced in cost compared to the method of cutting using a laser ablation process.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

Claims (9)

A method for fabricating a circuit board unit includes: forming a first circuit layer on a carrier board; forming a first dielectric layer on the first circuit layer and the carrier board; forming in the first dielectric layer a plurality of first openings and a plurality of first isolation channels, wherein the first openings expose the first circuit layer, the first isolation channels expose the carrier board; and the first dielectric layer and the first dielectric layer Forming a plurality of first via holes in the layer, and forming a second circuit layer on the first dielectric layer and the first via holes, wherein the first via holes and the second circuit layer are formed The step of: forming a photoresist on the first dielectric layer, wherein the photoresist covers the first isolation tracks; forming a plurality of third openings in the photoresist, wherein some of the third openings are exposed The first dielectric layer, the third openings are connected to the first openings, thereby exposing the first circuit layer; the first via holes are formed in the first openings, and the third openings are formed in the first openings Forming the second circuit layer; and removing the photoresist layer; and the second line Forming a second dielectric layer on the first dielectric layer; forming a plurality of second openings and a plurality of second isolation channels in the second dielectric layer, wherein the second openings expose the second line a layer, the second isolation channels are connected to the first isolation channels, thereby exposing the carrier plate; Forming a plurality of second via holes on the second circuit layer and the second dielectric layer, and forming a third circuit layer on the second dielectric layer and the second via holes; and removing The carrier board forms a plurality of circuit board units by dividing the first isolation channels and the second isolation channels. The method of claim 1, wherein in the step of removing the carrier, an ultraviolet film is irradiated to a release film disposed between the carrier and the first dielectric layer, thereby The circuit board units are detached from the carrier board. The method of claim 2, wherein in the step of removing the carrier, the ultraviolet light is irradiated from a side of the carrier relative to the circuit board units. The method of claim 1, wherein the carrier plate is made of glass or quartz glass. The method of claim 1, wherein the material of the first dielectric layer is a photosensitive dielectric material. The method of claim 1, wherein the first isolation tracks are formed by exposure development. The method of claim 1, further comprising: baking the first dielectric layer after the first openings and the first isolation tracks are formed. A circuit board unit comprising: a first dielectric layer having at least one top surface and at least one first side; a first circuit layer disposed in the first dielectric layer; and a second dielectric layer disposed On the top surface of the first dielectric layer, the second dielectric layer has at least one bottom surface and at least one second side, the bottom surface directly contacting the top surface of the first dielectric layer, the first dielectric layer a distance between the top surface of the electrical layer and a first connection of the first side and a second connection of the bottom surface of the second dielectric layer and the second side, wherein the second dielectric The bottom surface of the layer protrudes outwardly from the top surface of the first dielectric layer; a second circuit layer is disposed on the top surface of the first dielectric layer and the second dielectric layer; a circuit layer disposed on the second dielectric layer; a plurality of first via holes disposed in the first dielectric layer and connecting the first circuit layer and the second circuit layer; and a plurality of second via holes And disposed in the second dielectric layer and connecting the second circuit layer and the third circuit layer. The circuit board unit of claim 8, wherein the first side and the second side are not interconnected.