TWI484886B - Multilayer circuit board manufacturing method - Google Patents

Description

Multilayer circuit board manufacturing method

The present invention relates to a method of fabricating a circuit board, and more particularly to a method of fabricating a multilayer circuit board.

As the integration of electronic products is getting higher and higher, the circuit boards used in high-accumulation electronic products have also changed from single layer and 2 layers to 6 layers, 8 layers, and even 10 Above the layer, the electronic components can be more densely mounted on the printed circuit board. In general, the most common circuit board process is a lamination process. When a circuit board is fabricated by a lamination method, the alignment accuracy between each circuit layer and the insulating layer must be well controlled. Therefore, in the circuit board process, usually, a plurality of alignment targets are formed by the lithography process in the previous stack, and after the layers are further added, the alignment targets of the previous stack are found by X-ray and milled. The target process is to form another alignment target for subsequent processes.

However, since the alignment target of the previous stack is formed by the lithography process, there is already a process error in itself, and when the X-ray is used for milling the target, an error in the milling target process is also generated. Thus, the alignment error generated by the alignment targets of each layer Will continue to accumulate. If the number of circuit layers of the board increases, the error accumulated by these alignment targets also increases, causing the interlayer alignment to be excessively shifted and the design of the via holes and the underlying pads cannot be miniaturized.

The invention provides a manufacturing method of a multilayer circuit board, which can improve the interlayer alignment precision of the multilayer circuit board, improve the wiring density and capability of the circuit layer, and the design of the via hole and the bottom layer pad is improved due to the alignment accuracy. It can be miniaturized, and it can make pattern designs with unilateral alignment less than 50μm.

A method of fabricating a multilayer circuit board of the present invention comprises the steps of: first, pressing two core layers to form a substrate. The substrate has opposite surfaces. Next, a first through hole is formed which communicates both surfaces. Then, the first through holes are used as the alignment targets to form the first patterned circuit layer on both surfaces. Each of the first patterned circuit layers includes a first concentric pattern surrounding the first via. Next, each of the first stacked layers is formed on both surfaces, and includes a first dielectric layer and a first wiring layer covering the first dielectric layer. Next, a first through hole is formed which is projected through the first concentric circle pattern from the center to the inner diameter of the first concentric circle to the first stacked layer and the region of the substrate. Then, a second stacked layer is formed on each of the first stacked layers. Each of the second stacked layers includes a second dielectric layer and a second wiring layer covering the second dielectric layer. Thereafter, a second through hole is formed which is projected from the inner diameter of the second concentric circle to the second stacked layer, the first stacked layer and the region of the substrate through the first concentric pattern.

Based on the above, the method for fabricating the multilayer circuit board of the present invention is to first use two cores. The core laminates a substrate by forming a concentric pattern on the surface of the substrate, and the subsequent stacked layers are aligned with the concentric pattern on the innermost substrate to form a corresponding alignment. The holes are then subjected to subsequent processes of the corresponding stacked layers by the opposite holes of the respective layers. Moreover, after the substrate is repeatedly layered to have a certain structural strength, the two core layers of the substrate can be separated from each other to form two independent multilayer circuit boards, and then the two independent multilayer circuit boards are respectively separated. Carry out the subsequent layering process. Therefore, the manufacturing method of the present invention can form two independent multilayer circuit boards at a time, and can reduce the accumulation of alignment errors between layers of the conventional multilayer circuit board, and can reduce the problem of layering of the conventional multilayer circuit board. produce. Therefore, the present invention can improve the wiring density and capability of the circuit layer, and the design of the via hole and the underlying pad can be miniaturized due to the improvement of the alignment accuracy, and the pattern design with a single side alignment of less than 50 μm can be produced. .

The above described features and advantages of the invention will be apparent from the following description.

100a, 100b‧‧‧ multilayer board

110‧‧‧Substrate

110a, 110b‧‧‧ core layer

111‧‧‧The surrounding area

112, 114‧‧‧ surface

113‧‧‧ core area

113a‧‧‧ core area substrate

116‧‧‧First through hole

118‧‧‧Second through hole

119‧‧‧Combined materials

120‧‧‧First patterned circuit layer

122‧‧‧First concentric pattern

122a, 124a‧‧‧ first concentric circle

122b, 124b‧‧‧Second concentric circle

124‧‧‧Second concentric pattern

130‧‧‧First stacking layer

132‧‧‧First dielectric layer

134‧‧‧First line layer

134a‧‧‧first opening

140‧‧‧first through hole

150‧‧‧Second stacking layer

152‧‧‧Second dielectric layer

154‧‧‧Second circuit layer

154a‧‧‧second opening

160‧‧‧second through hole

170‧‧‧ sixth stacking layer

172‧‧‧ sixth dielectric layer

174‧‧‧ sixth circuit layer

174a, 194a‧‧

180‧‧‧six through hole

182‧‧‧Blind hole

190‧‧‧ seventh stack

192‧‧‧ seventh dielectric layer

194‧‧‧ seventh circuit layer

195‧‧‧ seventh through hole

D1‧‧‧through hole outer diameter

D2‧‧‧ concentric pattern outer diameter

G1‧‧‧ spacing

1A-1N are schematic flow diagrams of a method of fabricating a multilayer circuit board in accordance with an embodiment of the invention.

2 is a top plan view of the substrate and the first patterned circuit layer of FIG. 1D and a partial enlarged view of the region A thereof.

3 is a top plan view of the first concentric pattern of FIG. 1G.

4 is a top plan view of the first concentric pattern of FIG. 1I.

5 is a top plan view of the substrate and the first patterned circuit layer of FIG. 1D and a partial enlarged view of the region B thereof.

6 is a cross-sectional view of a multilayer circuit board and a partially enlarged schematic view thereof in accordance with an embodiment of the present invention.

1A-1N are schematic flow diagrams of a method of fabricating a multilayer circuit board in accordance with an embodiment of the invention. 2 is a top plan view of the substrate and the first patterned circuit layer of FIG. 1D and a partial enlarged view of the region A thereof. It should be noted that the manufacturing process illustrated in FIG. 1A to FIG. 1J is a cross-sectional view of the manufacturing process of the area A in FIG. 2 . The manufacturing method of the multilayer circuit board of this embodiment includes the following steps. First, referring to FIG. 1A and FIG. 1B, the two core layers 110a and 110b are pressed together to form a substrate 110. Substrate 110 includes opposing surfaces 112, 114 as shown in FIG. 1B. In the present embodiment, the core layers 110a, 110b each have a thickness of less than about 50 micrometers (μm). Next, as shown in FIG. 1C , a first through hole 116 is formed, and the first through hole 116 penetrates through the substrate 110 .

In the present embodiment, the method of pressing the two core layers 110a, 110b is, for example, pressing a bonding material 119 between the two core layers 110a, 110b to bond the two core layers 110a, 110b to form the substrate 110. The material of the bonding material 119 is, for example, a resin, and the first through holes 116 penetrate the substrate 110 and the bonding material 119, respectively. It should be noted that the first via hole 116 of the embodiment is formed on the core layer 110a, 110b through the junction. The joint of the composite material 119 is combined to prevent the first through hole 116 from breaking the airtight state between the two core layers 110a, 110b, or the chemical liquid causing the wet process to seep through the first through hole 116 to the two Between the core layers 110a, 110b. In the present embodiment, the outer diameter of the first through hole 116 is substantially between 0.5 mm and 0.8 mm.

Referring to FIG. 1D and FIG. 2 simultaneously, the metal layers on the two surfaces 112, 114 are respectively patterned by using the first via holes 116 as alignment targets to form the first patterned circuit layer 120 on the surfaces 112, 114, respectively. on. In the present embodiment, as shown in FIG. 2, the outer diameter D1 of the first through hole 116 is substantially between 0.5 mm (mm) and 0.8 mm. The first patterned circuit layer 120 has a first concentric pattern 122 surrounding the first via 116 as shown in FIG. The first concentric circle pattern 122 includes a plurality of concentric circles, and the distance G1 between the concentric circles is substantially between 50 micrometers (μm) and 100 micrometers. Of course, the invention is not limited thereto, and the field generally has Knowledgers can make adjustments according to the actual product design and layout requirements.

Next, as shown in FIG. 1E, a first stacked layer 130 is formed on the two surfaces 112, 114, respectively, wherein the first stacked layer 130 includes a first dielectric layer 132 and a first wiring layer 134, and the first circuit layer 134 covers the first dielectric layer 132. Thereafter, referring to FIG. 1F and FIG. 1G simultaneously, the first through hole 140 is formed by, for example, drilling with a CO ₂ laser. The first uniform hole 140 is orthographically projected from the center to the inner diameter of the first concentric circle 122a through the first concentric circle pattern 122 as shown in FIG. 1G to the region of the first stacked layer 130 and the substrate 110. FIG. 3 is a plan view showing the first concentric pattern 122 penetrated by the first through hole 140.

In the embodiment, the first patterned circuit layer 120 and the first circuit layer 134 The material is copper. Since copper has a higher absorption rate in the short-wavelength region below the ultraviolet region (<0.3 μm), and the carbon dioxide laser has a longer wavelength of light (about 10 micrometers or more), it belongs to the infrared region. Copper is ablated into holes without being absorbed by copper. Therefore, the concentric pattern 122 of copper material can be regarded as a copper mask of the carbon dioxide laser to limit the range in which the carbon dioxide laser cuts the first stacked layer 130 and the substrate 110. That is to say, by drilling a hole outward from the center by using a carbon dioxide laser, the first through hole 140 formed by drilling the inner diameter of the first concentric circle 122a is drilled. It should be noted that if the first through hole 140 is formed by using a carbon dioxide laser, a first opening 134a as shown in FIG. 1F is first formed on the first circuit layer 134, so that the first opening 134a exposes the first concentric circle. The pattern 122 is projected onto the area of the first dielectric layer 132 for subsequent drilling procedures.

Of course, the invention is not limited thereto. In other embodiments of the present invention, the first through hole 140 may also be formed by direct laser drilling (DLD). If the first through hole 140 is formed by direct laser drilling, the first opening 134a as shown in FIG. 1F does not need to be formed, and the laser drilling process can be directly performed to form the first through hole 140. In the present embodiment, the first through holes 140 may be formed by, for example, simultaneously drilling the outer surfaces of the first stacked layers 130 on both sides of the substrate 110 toward the substrate 110.

After that, the first through hole 140 can be used as a registration target to perform subsequent processing on the first stacked layer 130, for example, the first through hole 140 is used as a aligning target of the lithography process, and the first circuit layer 134 is patterned. Forming a second patterned circuit layer of the multilayer circuit board, or forming the first via hole with the first through hole 140 as an alignment target. Stacked on layer 130.

Thereafter, as shown in FIG. 1H, a second stacked layer 150 is formed on the corresponding first stacked layer 130, respectively. Each of the second stacked layers 150 includes a second dielectric layer 152 and a second wiring layer 154 , and the second wiring layer 154 covers the second dielectric layer 152 . Thereafter, a second through hole 160 is formed as shown in FIG. 1I, and the second through hole 160 is projected through the first concentric circle pattern 120 from the center to the inner diameter of the second concentric circle 122b to the second stacked layer 150, The first stacked layer 130 and the region of the substrate 110. FIG. 4 is a plan view showing the first concentric pattern 122 penetrated by the second through hole 160.

As described in the method of forming the first through hole, the second through hole 160 may also be formed by means of carbon dioxide laser drilling. That is, after the carbon dioxide laser is bored outward from the center to ablate the substrate 110 between the first concentric circle 122a and the second concentric circle 122b as shown in FIG. 3, the first concentric circle 122a The self-concentric pattern 120 can be peeled off to form a second through hole 160 as shown in FIG. Similarly, if a carbon dioxide laser is used to form the second through hole 160, a second opening 154a as shown in FIG. 1H is formed to expose the second opening 154a to expose the first concentric pattern 122 to the second dielectric. The area of layer 152 is followed by a subsequent laser drilling procedure.

Of course, in other embodiments of the present invention, the second through hole 160 may be formed by using a direct laser Drill (DLD), so that the second opening 154a as shown in FIG. 1H does not need to be formed. A direct laser drilling can be performed immediately to form a second through hole 160. In the present embodiment, the method of forming the second through holes 160 may be simultaneously drilled into the direction of the substrate 110 by the outer surfaces of the second stacked layers 150 on both sides of the substrate 110.

After that, the second through hole 160 can be used as a registration target to perform subsequent processing on the second stacked layer 150, for example, the second through hole 160 is used as an alignment target of the lithography process, and the second circuit layer 154 is patterned. Forming a third patterned circuit layer of the multilayer circuit board, or forming a second via hole on the second stacked layer 150 by using the second through hole 160 as an alignment target, wherein the second via hole is connected to the first The first via holes on the stacked layer 130.

Of course, the present invention does not limit the number of layers of the stacked layer, the wiring layer, and the number of concentric circles of the concentric pattern. Those skilled in the art can continue to stack other stacked layers on the second stacked layer according to the foregoing fabrication method, and form the alignment holes of the layers by using the concentric pattern 122 as the alignment target, and then the alignment of the layers. The through holes are respectively subjected to a subsequent alignment process to form patterned circuit layers and/or via holes of the respective layers.

After the number of times of layering of the multi-layer circuit board is greater than a predetermined value (for example, equal to or greater than 5 times), so that it has a certain structural strength, the action of removing the board can be performed, that is, the layer is repeatedly layered on the substrate 110 to have After a certain structural strength, the two core layers 110a, 110b of the substrate 110 are separated from each other as shown in FIG. 1J to form two independent multilayer circuit boards 100a, 100b, and then the multilayer circuit boards 100a, 100b are respectively followed. The layering process. In this embodiment, based on the maximum size limit readable by the image capturing window of the image sensor (CCD) of the production device, the maximum outer diameter D2 of the first concentric pattern 122 should be substantially less than or Is equal to 3.175 mm (mm). The stacked layers formed thereafter can be aligned by, for example, using another concentric pattern as an alignment target.

Thus, the first patterned circuit layer 120 needs to be packaged as shown in FIG. 2 and FIG. The two concentric patterns 122 and 124 are included, and the substrate 210 may have a second through hole 118 penetrating through the substrate 110 in addition to the first through hole 116. Then, the first through-holes 116 and the second vias 118 are used as alignment targets to form the first patterned circuit layer 120 on the surfaces 112 and 114 as shown in FIGS. 2 and 5, respectively. Each of the first patterned circuit layers 120 includes, in addition to the first concentric circle pattern 122 surrounding the first through holes 116 as shown in FIG. 2, a second concentric circle surrounding the second through holes 118 as shown in FIG. Pattern 124. In this embodiment, the substrate 110 can include a peripheral region 111 and a core region 113 as shown in FIG. 2 and FIG. 5, wherein the peripheral region 111 surrounds and connects the core region 113, the first through hole 116 and the second through hole. 118 is disposed in the peripheral area 111 and the core area 113, respectively. In this way, after the first concentric pattern 122 is used as the alignment target to perform the layering process to have a certain structural strength, the stripping action can be performed, and the peripheral region 111 of the substrate 110 is removed to form a figure. The core area substrate 113a shown in FIG. 5 is further subjected to a subsequent layer build-up process of the core area substrate 113a by using the second concentric pattern 124 as an alignment target.

Since the first concentric pattern 122 and the second concentric pattern 124 are formed by the same patterning process, the accumulation error of the multi-pass patterning process can be avoided. In this way, the stacked layers formed on the multilayer circuit boards 100a and 100b after the board is removed can be used as the alignment target by the second concentric pattern 124 for subsequent alignment process. The manufacturing process can be referred to FIG. 1K to FIG. 1N. . It should be noted that the manufacturing process illustrated in FIG. 1K to FIG. 1N is an example of the multi-layer circuit board 100a after the board is removed, and is a cross-sectional view of the manufacturing process of the area B in FIG.

Referring to FIG. 1K, the number of times of layering on the multilayer circuit board is greater than a predetermined value (example) If M is greater than 2, and M is a positive integer greater than 2, after having a certain structural strength, the Mth stacked layer may be formed over the second stacked layer 150 as shown in FIG. 1K. In this embodiment, M is, for example, 6, that is, the multi-layer circuit board has sequentially formed the first to fifth stacked layers by using the first concentric pattern 122 as the alignment target before the board is removed, and the sixth stack Layer 170 (ie, the Mth stack) corresponds to a sixth dielectric layer 172 and a sixth wiring layer 174 that covers the sixth dielectric layer 172. Next, as shown in FIG. 5 and FIG. 1L, a sixth through hole 180 is formed which is projected through the second concentric circle pattern 124 from the center to the inner diameter of the first concentric circle 124a to the first to the multilayer circuit board 100a. The sixth stacked layer and the region of the substrate 110.

It should be noted that, when the first concentric pattern 122 is used as the alignment target to form the through holes of the dielectric layers (for example, the first to fifth stacked layers), the second concentric pattern 124 may be respectively The two through holes 118 are projected onto the corresponding dielectric layer to form the blind holes 182, that is, the blind holes are respectively formed at the positions of the respective dielectric layers (for example, the first to fifth stacked layers) corresponding to the second through holes 118. 182, wherein the outer diameter of the blind hole 182 is smaller than the inner diameter of the first concentric circle 124a. In this way, since the stacked layers have been previously formed with blind holes, the total thickness of the dielectric layer is reduced. Therefore, in the subsequent process, the laser can form the sixth through hole without burning through the dielectric layer having a thick total thickness at one time. 180.

After that, the sixth through hole 180 can be used as a registration target to perform subsequent processing on the sixth stacked layer 170, for example, the sixth through hole 180 is used as a aligning target of the lithography process, and the sixth circuit layer 174 is patterned. The patterning circuit layer is formed to form a multilayer circuit board, or the sixth via hole is formed on the sixth stacked layer 170 by using the sixth through hole 180 as an alignment target.

Referring to FIG. 1M, a seventh stacked layer 190 (that is, an M+1 stacked layer) is formed on the sixth stacked layer 170. The seventh stacked layer 190 includes a seventh dielectric layer 192 and a seventh wiring layer 194 covering the seventh dielectric layer 192. Then, as shown in FIG. 5 and FIG. 1N, a seventh through hole 195 is formed which is projected through the second concentric circle pattern 124 from the center to the inner diameter of the second concentric circle 124b to the first to seventh stacks. The layer and the area of the substrate 110.

After that, the seventh via 195 can be used as a aligning target to perform the subsequent processing on the seventh stacked layer 190, for example, the seventh through hole 195 is used as a aligning target of the lithography process, and the seventh circuit layer 194 is patterned. Forming a patterned circuit layer of the multilayer circuit board, or forming a seventh via hole on the seventh stacked layer 190 by using the seventh through hole 195 as an alignment target, wherein the seventh via hole is connected to the sixth stacked layer The sixth via hole on the 170, and the via holes of each layer are connected to each other to turn on the stacked layers of the various layers of the multilayer circuit board.

As described above, the sixth through hole 180 and the seventh through hole 195 can also be formed by means of carbon dioxide laser drilling or direct laser drilling. Similarly, if a carbon dioxide laser is used to form the sixth through hole 180 and the seventh through hole 195, openings 174a and 194a as shown in FIGS. 6A and 6C are formed to expose the second concentric pattern 124, respectively. The area is projected to the sixth dielectric layer 172 and the second dielectric layer 192, and the drilling process is performed. If direct laser drilling is used, it is not necessary to form openings 174a, 194a, and direct laser drilling can be performed immediately.

6 is a cross-sectional view of a multilayer circuit board and a partially enlarged schematic view thereof in accordance with an embodiment of the present invention. Please refer to FIG. 6 , it should be noted that the embodiment is The bonding material 119 of the multi-layer circuit board is disposed on the peripheral regions of the two core layers 110a, 110b to join the two core layers 110a, 110b, and form a close-up region on the periphery of the two core layers 110a, 110b, so that the two core layers 110a 110b is temporarily joined together to prevent the agent used in the subsequent process from infiltrating between the two core layers 110a, 110b. The first concentric pattern 122 and the second concentric pattern (such as the second concentric pattern 124 shown in FIG. 2) may be disposed corresponding to the bonding material 119, so that the first through hole 116 may be formed as shown in FIG. 6. The adhesion region is formed in a region between the adhesion region and the outer edge of the multilayer circuit board to prevent the first through hole 116 from breaking the airtight state between the two core layers 110a and 110b, and even causing the process liquid to pass through the first A through hole 116 seeps between the two core layers 110a, 110b.

In summary, the method for fabricating a multilayer circuit board of the present invention is to first laminate a substrate by two cores, and form a concentric pattern on the surface of the substrate, and then the stacked layers of each layer are the innermost layer. The concentric circles on the material are used as alignment targets to form corresponding pairs of through holes, and then the corresponding layers of the respective layers are respectively subjected to subsequent processes of the stacked layers, for example, the layers are formed by using the alignment holes as the alignment reference. Patterned circuit layers, vias, and the like. Moreover, after the substrate is repeatedly layered to have a certain structural strength, the two core layers of the substrate can be separated from each other to form two independent multilayer circuit boards, and then the two independent multilayer circuit boards are respectively separated. Carry out the subsequent layering process. Therefore, the manufacturing method of the present invention can form two independent multilayer circuit boards at a time, and can reduce the accumulation of alignment errors between layers of the conventional multilayer circuit board, and can reduce the problem of layering of the conventional multilayer circuit board. produce. In addition, since the via holes of each layer are formed by a concentric pattern formed by the same lithography process, they are shaped as alignment targets. In this way, it is possible to reduce the situation in which the via holes are displaced due to the accumulation error of the interlayers, and the via holes are not even connected to each other. Therefore, the present invention can improve the wiring density and capability of the circuit layer, and the design of the via hole and the underlying pad can be miniaturized due to the improvement of the alignment accuracy, and the pattern design with a single side alignment of less than 50 μm can be produced. .

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

110‧‧‧Substrate

111‧‧‧The surrounding area

113‧‧‧ core area

116‧‧‧First through hole

118‧‧‧Second through hole

120‧‧‧First patterned circuit layer

122‧‧‧First concentric pattern

122a‧‧‧The first concentric circle

122b‧‧‧Second concentric circle

124‧‧‧Second concentric pattern

D1‧‧‧through hole outer diameter

D2‧‧‧ concentric pattern outer diameter

G1‧‧‧ spacing

Claims (16)

A method for fabricating a multi-layer circuit board, comprising: pressing two core layers to form a substrate, the substrate having opposite surfaces; forming a first through hole, the first through hole communicating the two surfaces; a through hole is formed on the two surfaces of the alignment target each of the first patterned circuit layer, each of the first patterned circuit layers includes a first concentric pattern surrounding the first through hole; each forming a first a stacked layer on the two surfaces, comprising a first dielectric layer and a first circuit layer covering the first dielectric layer; forming a first through hole, the first through hole penetrating the first concentric circle Forming an inner diameter of the first concentric circle from the center to the first stacked layer and the region of the substrate; forming a second stacked layer on each of the first stacked layers, each of the second stacked The layer includes a second dielectric layer and a second circuit layer covering the second dielectric layer; and a second through hole extending through the first concentric pattern from the center to the second The inner diameter of the concentric circles is projected onto the second stacked layers, the first stacked layers, and the base Area. The method for fabricating a multilayer circuit board according to claim 1, wherein the step of pressing the two core layers further comprises: pressing a bonding material between the two core layers. The method for fabricating a multilayer circuit board according to claim 2, wherein the first through hole penetrates the substrate and the bonding material, respectively. The method for fabricating a multilayer circuit board according to claim 2, wherein the material of the bonding material comprises a resin. The method for fabricating a multilayer circuit board according to claim 1, further comprising: after forming the first through hole, respectively patterning the first circuit layers by using the first through hole as an alignment target; After the second through holes are formed, the second through holes are respectively patterned by using the second through holes as alignment targets. The method for fabricating a multilayer circuit board according to the first aspect of the invention, further comprising: forming the first through hole, forming a first via hole in the first through hole as a corresponding target hole in the corresponding first And forming a second via hole, wherein the second via hole is formed as a second via hole on the corresponding second stacked layer, and each of the second via holes is connected The first via hole. The method of fabricating a multilayer circuit board according to claim 1, wherein the method of forming the first through hole and the second through hole comprises carbon dioxide laser drilling. The method of fabricating the multi-layer circuit board of claim 7, further comprising: forming a first opening on the corresponding first circuit layer before forming the first through hole, the first opening being exposed The first concentric pattern is orthographically projected to the first medium a region of the electrical layer; and forming a second opening on the corresponding second circuit layer before forming the second through hole, the first opening exposing the first concentric pattern to the second dielectric The area of the layer. The method for fabricating a multilayer circuit board according to claim 7, wherein the method of forming the first through hole comprises drilling an outer surface of the first stacked layer toward the substrate simultaneously, and forming the The method of the second through hole includes drilling the outer surface of the second stacked layers simultaneously into the direction of the substrate. The method of fabricating a multilayer circuit board according to claim 1, wherein the method of forming the first through hole and the second through hole comprises Direct Laser Drilling (DLD). The method for fabricating a multilayer circuit board according to claim 10, wherein the method of forming the first through hole comprises drilling an outer surface of the first stacked layer toward the substrate simultaneously to form the first The method of two-holes includes drilling the outer surfaces of the second stacked layers simultaneously into the direction of the substrate. The method for fabricating a multilayer circuit board according to claim 1, further comprising: after forming the second through hole, separating the two core layers of the substrate from each other to form two independent multilayer circuit boards. . The method of fabricating a multilayer circuit board according to claim 12, wherein the substrate further comprises a second through hole penetrating the substrate, the first patterned circuit layer further comprising a second through hole. a second concentric pattern, the multilayer circuit The method further includes: forming an M-th stack layer on one of the plurality of multi-layer circuit boards, and located above the second stack layer of the multi-layer circuit board, the M-th stack layer includes an M-th dielectric layer And an Mth circuit layer covering the Mth dielectric layer, wherein M is a positive integer greater than 2; forming an Mth through hole, the Mth through hole extending through the center from the center to the first The inner diameter of the concentric circle is projected onto the first to the Mth stacked layer of the multilayer circuit board and the area of the core layer; forming an M+1th stacked layer on the Mth stacked layer, the M+1 The stacked layer includes an M+1 dielectric layer and an M+1 circuit layer covering the M+1 dielectric layer; and forming an M+1 through hole, the M+1 through hole penetrating the first The two concentric pattern is projected from the center to the inner diameter of the second concentric circle to the region of the first to the M+1 stacked layers of the multilayer circuit board and the core layer. The method for fabricating a multilayer circuit board according to claim 13 , further comprising: after forming the M through hole, patterning the Mth circuit layer with the M through hole as an alignment target; and forming the After the M+1 through hole, the M+1th line layer is patterned by using the M+1 through hole as a registration target. The method for manufacturing the multilayer circuit board according to claim 13 of the patent application, further comprising: After forming the M through hole, forming an Mth via hole on the Mth stacked layer by using the M through hole as an alignment target; and forming the M+1 through hole, the M+ The through hole is an aligning target forming an M+1 via hole on the M+1 stacked layer, and the M+1 conductive via is connected to the Mth via hole. The method of fabricating a multilayer circuit board according to claim 13, wherein M is substantially equal to or greater than 5.