TWI625833B - Package structure - Google Patents
Package structure Download PDFInfo
- Publication number
- TWI625833B TWI625833B TW105112755A TW105112755A TWI625833B TW I625833 B TWI625833 B TW I625833B TW 105112755 A TW105112755 A TW 105112755A TW 105112755 A TW105112755 A TW 105112755A TW I625833 B TWI625833 B TW I625833B
- Authority
- TW
- Taiwan
- Prior art keywords
- lead frame
- thickness
- chip
- package structure
- recessed
- Prior art date
Links
Classifications
-
- H10W70/40—
-
- H10W70/461—
-
- H10W76/12—
-
- H10W74/00—
-
- H10W74/142—
-
- H10W90/726—
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
一種封裝結構，包含導線架、第一晶片以及封裝材。導線架具有相對之第一面與第二面，且具有位於第二面上的第一凹陷區域。第一晶片具有相對之第一面與第二面，其中第一晶片的第一面固定於導線架的第一凹陷區域。封裝材包覆導線架與第一晶片，其中第一晶片的第二面與導線架的第一面自封裝材裸露。A packaging structure includes a lead frame, a first chip, and a packaging material. The lead frame has a first surface and a second surface opposite to each other, and has a first recessed area on the second surface. The first wafer has a first surface and a second surface opposite to each other, wherein the first surface of the first wafer is fixed to the first recessed area of the lead frame. The packaging material covers the lead frame and the first chip, wherein the second surface of the first chip and the first surface of the lead frame are exposed from the packaging material.
Description
本發明是有關於一種封裝結構。The invention relates to a packaging structure.
導線架通常為用於封裝膠體所包覆的結構中，此結構亦被稱為封裝結構。導線架可由例如銅的金屬製造，且通常包含位於導線架中央且固定於支架的接合墊。導線架亦包含固定於支架的多個導線。在一些裸露式封裝結構中，導線架的接合墊的底部可能為裸露，用以接合印刷電路板的接合墊。The lead frame is usually used in the structure covered by the encapsulation gel. This structure is also called the encapsulation structure. The lead frame may be made of metal such as copper, and typically includes a bonding pad located in the center of the lead frame and fixed to the bracket. The lead frame also includes a plurality of wires fixed to the bracket. In some bare-type packaging structures, the bottom of the bonding pads of the lead frame may be bare for bonding pads of a printed circuit board.
為了進一步改善封裝結構的各項特性，相關領域莫不費盡心思開發。如何能提供一種具有較佳特性的封裝結構，實屬當前重要研發課題之一，亦成爲當前相關領域亟需改進的目標。In order to further improve the various characteristics of the package structure, the related fields have been developed with great care. How to provide a package structure with better characteristics is really one of the important R & D topics at present, and it has become an urgent need for improvement in related fields.
本發明之一技術態樣是在提供一種具有良好散熱能力的封裝結構。One aspect of the present invention is to provide a packaging structure with good heat dissipation capability.
根據本發明一實施方式，一種封裝結構，包含導線架、第一晶片以及封裝材。導線架具有相對之第一面與第二面，且具有位於第二面上的第一凹陷區域。第一晶片具有相對之第一面與第二面，其中第一晶片的第一面固定於導線架的第一凹陷區域。封裝材包覆導線架與第一晶片，其中第一晶片的第二面與導線架的第一面自封裝材裸露。According to an embodiment of the present invention, a packaging structure includes a lead frame, a first chip, and a packaging material. The lead frame has a first surface and a second surface opposite to each other, and has a first recessed area on the second surface. The first wafer has a first surface and a second surface opposite to each other, wherein the first surface of the first wafer is fixed to the first recessed area of the lead frame. The packaging material covers the lead frame and the first chip, wherein the second surface of the first chip and the first surface of the lead frame are exposed from the packaging material.
於本發明之一或多個實施方式中，封裝結構更包含第二凹陷區域與第二晶片。第二凹陷區域位於導線架的第二面上。第二晶片具有相對之第一面與第二面，其中第二晶片的第一面固定於導線架的第二凹陷區域上，封裝材更包覆第二晶片，且第二晶片的第二面自封裝材裸露。In one or more embodiments of the present invention, the packaging structure further includes a second recessed region and a second wafer. The second recessed area is located on the second side of the lead frame. The second wafer has a first surface and a second surface opposite to each other, wherein the first surface of the second wafer is fixed on the second recessed area of the lead frame, the packaging material further covers the second wafer, and the second surface of the second wafer Exposed self-sealing material.
根據本發明另一實施方式，一種封裝結構，包含導線架、第一晶片、散熱件以及封裝材。導線架具有相對之第一面與第二面，且具有位於第二面上的第一凹陷區域。第一晶片具有相對之第一面與第二面，其中第一晶片的第一面固定於導線架的第一凹陷區域上。散熱件具有相對之第一面與第二面，其中散熱件的第一面熱接觸第一晶片的第二面。封裝材包覆導線架、第一晶片與散熱件，其中散熱件的第二面與導線架的第一面自封裝材裸露。According to another embodiment of the present invention, a packaging structure includes a lead frame, a first chip, a heat sink, and a packaging material. The lead frame has a first surface and a second surface opposite to each other, and has a first recessed area on the second surface. The first wafer has opposite first and second faces, wherein the first face of the first wafer is fixed on the first recessed area of the lead frame. The heat sink has opposite first and second faces, wherein the first face of the heat sink is in thermal contact with the second face of the first wafer. The packaging material covers the lead frame, the first chip and the heat sink, wherein the second surface of the heat sink and the first surface of the lead frame are exposed from the packaging material.
於本發明之一或多個實施方式中，封裝材沒有包覆導線架的第一面。In one or more embodiments of the present invention, the packaging material does not cover the first surface of the lead frame.
於本發明之一或多個實施方式中，封裝結構更包含第二凹陷區域與第二晶片。第二凹陷區域位於導線架的第二面上。第二晶片具有相對之第一面與第二面，其中第二晶片的第一面固定於導線架的第二凹陷區域上，封裝材更包覆第二晶片。In one or more embodiments of the present invention, the packaging structure further includes a second recessed region and a second wafer. The second recessed area is located on the second side of the lead frame. The second wafer has a first surface and a second surface opposite to each other, wherein the first surface of the second wafer is fixed on the second recessed area of the lead frame, and the packaging material further covers the second wafer.
於本發明之一或多個實施方式中，導線架的第一凹陷區域的厚度與第二凹陷區域的厚度大致相同。In one or more embodiments of the present invention, the thickness of the first recessed area of the lead frame is substantially the same as the thickness of the second recessed area.
於本發明之一或多個實施方式中，導線架的第一凹陷區域的厚度與第二凹陷區域的厚度不同。In one or more embodiments of the present invention, the thickness of the first recessed area of the lead frame is different from the thickness of the second recessed area.
於本發明之一或多個實施方式中，導線架的第一凹陷區域更區分為第一區塊與第二區塊，第一區塊與第二區塊不直接接觸，第一晶片的第一面電性接觸第一區塊與第二區塊。In one or more embodiments of the present invention, the first recessed area of the lead frame is further divided into a first block and a second block, and the first block and the second block are not in direct contact with each other. One side is in electrical contact with the first block and the second block.
於本發明之一或多個實施方式中，導線架具有相對於第一凹陷區域的平坦區域，平坦區域的厚度大於第一凹陷區域的厚度。In one or more embodiments of the present invention, the lead frame has a flat area relative to the first recessed area, and the thickness of the flat area is greater than the thickness of the first recessed area.
於本發明之一或多個實施方式中，第一晶片的厚度大致等於導線架的平坦區域的厚度。In one or more embodiments of the present invention, the thickness of the first wafer is substantially equal to the thickness of the flat area of the lead frame.
於本發明之一或多個實施方式中，第一晶片的厚度大於導線架的第一凹陷區域的厚度。In one or more embodiments of the present invention, the thickness of the first wafer is greater than the thickness of the first recessed region of the lead frame.
於本發明之一或多個實施方式中，導線架的第一面為平面。In one or more embodiments of the present invention, the first surface of the lead frame is a flat surface.
在本發明上述實施方式中，因為第一晶片的第二面與導線架的第一面自封裝材裸露，且第一晶片為固定於導線架的第一凹陷區域上，第一晶片可以藉由導線架的第一面及第一晶片的第二面有效地散熱。於是，封裝結構的散熱能力得以有效提升。In the above embodiment of the present invention, because the second surface of the first chip and the first surface of the lead frame are exposed from the packaging material, and the first chip is fixed on the first recessed area of the lead frame, the first chip can be obtained by The first surface of the lead frame and the second surface of the first chip effectively dissipate heat. Therefore, the heat dissipation capability of the packaging structure can be effectively improved.
以下將以圖式揭露本發明之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。In the following, a plurality of embodiments of the present invention will be disclosed graphically. For the sake of clarity, many practical details will be described in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventional structures and components will be shown in the drawings in a simple and schematic manner.
第1圖繪示依照本發明一實施方式之封裝結構的立體圖。第2圖繪示沿第1圖之切線2的剖面圖。如第1圖與第2圖所繪示，本發明之一實施方式提供一種封裝結構100。封裝結構100包含導線架110、第一晶片120以及封裝材130。FIG. 1 is a perspective view of a package structure according to an embodiment of the present invention. Fig. 2 is a cross-sectional view taken along the tangent line 2 of Fig. 1. As shown in FIG. 1 and FIG. 2, an embodiment of the present invention provides a packaging structure 100. The package structure 100 includes a lead frame 110, a first chip 120 and a packaging material 130.
導線架110具有相對之第一面111與第二面113，且具有位於第二面113上的第一凹陷區域115。第一晶片120具有相對之第一面121與第二面123，其中第一晶片120的第一面121固定於第一凹陷區域115，且第一晶片120的第一面121與至少部份第一凹陷區域115電性連接。封裝材130包覆導線架110與第一晶片120，其中第一晶片120的第二面123與導線架110的第一面111自封裝材130裸露。換句話說，封裝材130沒有包覆(覆蓋)導線架110的第一面111。The lead frame 110 has a first surface 111 and a second surface 113 opposite to each other, and has a first recessed area 115 on the second surface 113. The first wafer 120 has a first surface 121 and a second surface 123 opposite to each other. The first surface 121 of the first wafer 120 is fixed to the first recessed area 115, and the first surface 121 of the first wafer 120 and at least part of the first A recessed area 115 is electrically connected. The packaging material 130 covers the lead frame 110 and the first chip 120. The second surface 123 of the first chip 120 and the first surface 111 of the lead frame 110 are exposed from the packaging material 130. In other words, the packaging material 130 does not cover (cover) the first surface 111 of the lead frame 110.
因為封裝材130沒有包覆導線架110的第一面111，第一晶片120的第二面123自封裝材130裸露，且第一晶片120為固定於第一凹陷區域115上，故第一晶片120可以藉由導線架110的第一面111及/或第一晶片120的第二面123有效地散熱。於是，封裝結構100的散熱能力得以有效提升。Because the packaging material 130 does not cover the first surface 111 of the lead frame 110, the second surface 123 of the first chip 120 is exposed from the packaging material 130, and the first chip 120 is fixed on the first recessed area 115, so the first chip 120 can effectively dissipate heat through the first surface 111 of the lead frame 110 and / or the second surface 123 of the first chip 120. Therefore, the heat dissipation capability of the packaging structure 100 can be effectively improved.
具體而言，導線架110的第一面111為平面。因為導線架110的第一面111為平面，封裝結構100可以在封裝材130沒有包覆導線架110的第一面111的情況下維持整體性(也就是說，封裝結構100的形狀可為長方體)。應了解到，以上所舉之導線架110的具體實施方式僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇導線架110的具體實施方式。Specifically, the first surface 111 of the lead frame 110 is a flat surface. Because the first surface 111 of the lead frame 110 is a plane, the packaging structure 100 can maintain the integrity without the encapsulation material 130 covering the first surface 111 of the lead frame 110 (that is, the shape of the packaging structure 100 may be a rectangular parallelepiped ). It should be understood that the specific implementations of the lead frame 110 mentioned above are merely examples and are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains should flexibly select the specific implementation of the lead frame 110 according to actual needs. the way.
導線架110具有相對於第一凹陷區域115的平坦區域118，平坦區域118的厚度大於第一凹陷區域115的厚度。具體而言，在一些實施方式中，第一凹陷區域115可以藉由蝕刻導線架110的第二面113而形成。The lead frame 110 has a flat region 118 opposite to the first recessed region 115, and the thickness of the flat region 118 is greater than the thickness of the first recessed region 115. Specifically, in some embodiments, the first recessed region 115 may be formed by etching the second surface 113 of the lead frame 110.
具體而言，第一晶片120所產生之熱能為先傳遞至導線架110的第一凹陷區域115，接著再傳遞至導線架110的第一面111而將熱能傳遞至空氣中。因為第一凹陷區域115的厚度小於平坦區域118的厚度，相較於藉由導線架110的平坦區域118傳遞第一晶片120所產生之熱能，第一凹陷區域115將能較容易將熱能傳遞至空氣中。Specifically, the thermal energy generated by the first wafer 120 is first transferred to the first recessed region 115 of the lead frame 110, and then transferred to the first surface 111 of the lead frame 110 to transfer the thermal energy to the air. Because the thickness of the first recessed region 115 is smaller than the thickness of the flat region 118, the first recessed region 115 can more easily transfer the thermal energy to the first recessed region 115 than the heat generated by the first wafer 120 is transferred through the flat region 118 of the lead frame 110. in the air.
在此同時，因為平坦區域118的厚度大於第一凹陷區域115的厚度，封裝結構100將會具有足夠的整體結構強度。具體而言，封裝結構100的整體結構主要由導線架110與第一晶片120所支持。在第一凹陷區域115附近的區域，封裝結構100主要是由第一晶片120與第一凹陷區域115的結構所支持；在平坦區域118附近的區域，封裝結構100主要是由平坦區域118的結構所支持。因為第一晶片120與第一凹陷區域115的總厚度與平坦區域118的厚度皆夠大，因此無論是在第一凹陷區域115附近的區域或是在平坦區域118附近的區域，封裝結構100皆具有足夠的結構強度。At the same time, because the thickness of the flat area 118 is greater than the thickness of the first recessed area 115, the package structure 100 will have sufficient overall structural strength. Specifically, the overall structure of the package structure 100 is mainly supported by the lead frame 110 and the first chip 120. In the area near the first recessed area 115, the package structure 100 is mainly supported by the structure of the first wafer 120 and the first recessed area 115; in the area near the flat area 118, the package structure 100 is mainly a structure with the flat area 118 Supported. Because the total thickness of the first wafer 120 and the first recessed region 115 and the thickness of the flat region 118 are sufficiently large, the package structure 100 is the same in both the region near the first recessed region 115 and the region near the flat region 118. With sufficient structural strength.
第一晶片120的厚度可大致等於導線架110的平坦區域118的厚度。第一晶片120的厚度可大於導線架110的第一凹陷區域115的厚度。The thickness of the first wafer 120 may be substantially equal to the thickness of the flat area 118 of the lead frame 110. The thickness of the first wafer 120 may be greater than the thickness of the first recessed region 115 of the lead frame 110.
平坦區域118的厚度可為約100微米至約250微米。第一凹陷區域115的厚度可為約50微米至約100微米。第一晶片120的厚度可為約100微米至約300微米。封裝結構100的總厚度可為約400微米至1000微米。應了解到，以上所舉之封裝結構100、第一凹陷區域115、平坦區域118與第一晶片120的具體實施方式僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇封裝結構100、第一凹陷區域115、平坦區域118與第一晶片120的具體實施方式。The thickness of the flat region 118 may be about 100 microns to about 250 microns. The thickness of the first recessed region 115 may be about 50 micrometers to about 100 micrometers. The thickness of the first wafer 120 may be about 100 micrometers to about 300 micrometers. The total thickness of the packaging structure 100 may be about 400 micrometers to 1000 micrometers. It should be understood that the specific implementations of the package structure 100, the first recessed area 115, the flat area 118, and the first wafer 120 mentioned above are merely examples, and are not intended to limit the present invention, which has general knowledge in the technical field to which the present invention belongs According to actual needs, specific implementations of the packaging structure 100, the first recessed area 115, the flat area 118, and the first wafer 120 should be selected flexibly.
第一晶片120的基板之材質可為例如銅的金屬。封裝材130之材質可為封裝膠體。應了解到，以上所舉之第一晶片120的基板與封裝材130之材質僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇第一晶片120的基板與封裝材130之材質。The material of the substrate of the first wafer 120 may be a metal such as copper. The material of the packaging material 130 may be a packaging gel. It should be understood that the materials of the substrate and the packaging material 130 of the first wafer 120 mentioned above are merely examples and are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should flexibly choose The material of the substrate of a wafer 120 and the packaging material 130.
具體而言，第一晶片120適用於覆晶(Flip-Chip)製程。換句話說，第一晶片120的第一面121為覆晶接置於第一凹陷區域115，其中第一面121可具有主動層。第一晶片120的第一面121與導線架110的第一凹陷區域115可藉由使用例如設置於第一晶片120的第一面121上的小焊料球陣列(未繪示)形成電性連結。Specifically, the first wafer 120 is suitable for a flip-chip process. In other words, the first surface 121 of the first wafer 120 is a flip-chip connection and is placed in the first recessed area 115, wherein the first surface 121 may have an active layer. The first surface 121 of the first chip 120 and the first recessed area 115 of the lead frame 110 may be electrically connected by using, for example, a small solder ball array (not shown) disposed on the first surface 121 of the first chip 120. .
第3圖繪示依照本發明一實施方式之不具有封裝材的封裝結構的立體圖。如第2圖與第3圖所繪示，導線架110的第一凹陷區域115更區分為第一區塊116與第二區塊117，第一區塊116與第二區塊117不直接接觸，第一晶片120的第一面121電性接觸第一區塊116與第二區塊117。於是，藉由將第一區塊116與第二區塊117分別電性連接其他不同的電子元件，第一晶片120將可以電性連接於不同的電子元件。FIG. 3 is a perspective view of a packaging structure without a packaging material according to an embodiment of the present invention. As shown in FIG. 2 and FIG. 3, the first recessed area 115 of the lead frame 110 is further divided into a first block 116 and a second block 117, and the first block 116 and the second block 117 do not directly contact each other. The first surface 121 of the first chip 120 is in electrical contact with the first block 116 and the second block 117. Therefore, by electrically connecting the first block 116 and the second block 117 with other different electronic components, the first chip 120 can be electrically connected with different electronic components.
第一凹陷區域115可區分為更多區塊。舉例來說，在本實施方式中，第一凹陷區域115進一步區分為第一區塊116、第二區塊117與第三區塊116b。第三區塊116b不與第一區塊116、第二區塊117直接接觸。The first recessed area 115 may be divided into more blocks. For example, in this embodiment, the first recessed area 115 is further divided into a first block 116, a second block 117, and a third block 116b. The third block 116b is not in direct contact with the first block 116 and the second block 117.
第4圖繪示依照本發明另一實施方式之封裝結構的剖面圖。如第4圖所繪示，本實施方式之封裝結構100與第1圖、第2圖與第3圖的封裝結構100大致相同，以下主要描述其相異處。FIG. 4 is a cross-sectional view of a package structure according to another embodiment of the present invention. As shown in FIG. 4, the package structure 100 of this embodiment is substantially the same as the package structure 100 of FIGS. 1, 2, and 3. The differences are mainly described below.
本實施方式之封裝結構100更包含第二凹陷區域119與第二晶片140。第二凹陷區域119位於導線架110的第二面113上，但不與前述第一凹陷區域115重疊處。第二晶片140具有相對之第一面141與第二面143，其中第二晶片140的第一面141固定於導線架110的第二凹陷區域119上，且第二晶片140的第一面141與至少部份第二凹陷區域119電性連接。封裝材130更包覆第二晶片140，且第二晶片140的第二面143自封裝材130裸露。The package structure 100 of this embodiment further includes a second recessed region 119 and a second chip 140. The second recessed area 119 is located on the second surface 113 of the lead frame 110, but does not overlap the aforementioned first recessed area 115. The second chip 140 has a first surface 141 and a second surface 143 opposite to each other, wherein the first surface 141 of the second chip 140 is fixed on the second recessed area 119 of the lead frame 110, and the first surface 141 of the second chip 140 Is electrically connected to at least part of the second recessed area 119. The packaging material 130 further covers the second chip 140, and the second surface 143 of the second chip 140 is exposed from the packaging material 130.
具體而言，導線架110的第一凹陷區域115的厚度與導線架110的第二凹陷區域119的厚度大致相同。Specifically, the thickness of the first recessed area 115 of the lead frame 110 is substantially the same as the thickness of the second recessed area 119 of the lead frame 110.
第5圖繪示依照本發明另一實施方式之封裝結構的剖面圖。如第5圖所繪示，本實施方式之封裝結構100與第4圖的封裝結構100大致相同，主要相異處在於，導線架110的第一凹陷區域115的厚度與導線架110的第二凹陷區域119的厚度不同。在本實施方式中，第一凹陷區域115的厚度小於第二凹陷區域119的厚度。應了解到，以上所舉之第一凹陷區域115、第二凹陷區域119的厚度僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇第一凹陷區域115、第二凹陷區域119的厚度。FIG. 5 is a cross-sectional view of a package structure according to another embodiment of the present invention. As shown in FIG. 5, the package structure 100 of this embodiment is substantially the same as the package structure 100 of FIG. 4. The main difference is that the thickness of the first recessed area 115 of the lead frame 110 is the same as that of the lead frame 110. The thickness of the recessed area 119 is different. In this embodiment, the thickness of the first recessed region 115 is smaller than the thickness of the second recessed region 119. It should be understood that the thicknesses of the first recessed area 115 and the second recessed area 119 mentioned above are merely examples, and are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should flexibly choose according to actual needs. The thickness of the first recessed region 115 and the second recessed region 119.
於是，如第4圖與第5圖所繪示，第一凹陷區域115與第二凹陷區域119的厚度可以分別依照第一晶片120與第二晶片140的厚度調整，以使封裝結構100的形狀可以維持整體性及表面平整度。此外，依照實際的情況與需求，封裝結構100可更進一步包含更多晶片，同時導線架110亦可更進一步包含更多凹陷區域。Therefore, as shown in FIGS. 4 and 5, the thicknesses of the first recessed region 115 and the second recessed region 119 can be adjusted according to the thicknesses of the first wafer 120 and the second wafer 140, respectively, so as to make the shape of the package structure 100. Can maintain integrity and surface flatness. In addition, according to actual conditions and requirements, the package structure 100 may further include more chips, and the lead frame 110 may further include more recessed areas.
第6圖繪示依照本發明另一實施方式之封裝結構的立體圖。第7圖繪示沿第6圖之切線7的剖面圖。如第6圖與第7圖所繪示，本實施方式之封裝結構100與第1圖、第2圖與第3圖的封裝結構100大致相同，以下主要描述其相異處。FIG. 6 is a perspective view of a packaging structure according to another embodiment of the present invention. FIG. 7 is a cross-sectional view taken along a tangent line 7 in FIG. 6. As shown in FIG. 6 and FIG. 7, the package structure 100 of this embodiment is substantially the same as the package structure 100 of FIG. 1, FIG. 2, and FIG. 3, and the differences are mainly described below.
封裝結構100更包含散熱件150。散熱件150具有相對之第一面151與第二面153，其中散熱件150的第一面151熱接觸並覆蓋第一晶片120的第二面123。封裝材130包覆導線架110、第一晶片120與散熱件150，其中散熱件150的第二面153自封裝材130裸露。The package structure 100 further includes a heat sink 150. The heat sink 150 has a first surface 151 and a second face 153 opposite to each other. The first surface 151 of the heat sink 150 thermally contacts and covers the second surface 123 of the first wafer 120. The packaging material 130 covers the lead frame 110, the first chip 120 and the heat sink 150, wherein the second surface 153 of the heat sink 150 is exposed from the packaging material 130.
具體而言，散熱件150的厚度可為150微米至250微米。應了解到，以上所舉之散熱件150的厚度僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇散熱件150的厚度。Specifically, the thickness of the heat sink 150 may be 150 μm to 250 μm. It should be understood that the thickness of the heat dissipation member 150 mentioned above is merely an example and is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should elastically select the thickness of the heat dissipation member 150 according to actual needs.
第8圖繪示依照本發明另一實施方式之封裝結構的剖面圖。如第8圖所繪示，本實施方式之封裝結構100與第6圖與第7圖的封裝結構100大致相同，以下主要描述其相異處。FIG. 8 is a cross-sectional view of a package structure according to another embodiment of the present invention. As shown in FIG. 8, the packaging structure 100 of this embodiment is substantially the same as the packaging structure 100 of FIGS. 6 and 7, and the differences are mainly described below.
封裝結構100更包含第二凹陷區域119與第二晶片140。第二凹陷區域119位於導線架110的第二面113上，但不與前述第一凹陷區域115重疊處。第二晶片140具有相對之第一面141與第二面143，其中第二晶片140的第一面141固定於導線架110的第二凹陷區域119上，且第二晶片140的第一面141與至少部份第二凹陷區域119電性連接。封裝材130更包覆第二晶片140。The package structure 100 further includes a second recessed region 119 and a second chip 140. The second recessed area 119 is located on the second surface 113 of the lead frame 110, but does not overlap the aforementioned first recessed area 115. The second chip 140 has a first surface 141 and a second surface 143 opposite to each other, wherein the first surface 141 of the second chip 140 is fixed on the second recessed area 119 of the lead frame 110, and the first surface 141 of the second chip 140 Is electrically connected to at least part of the second recessed area 119. The packaging material 130 further covers the second chip 140.
具體而言，第二晶片140的第二面143自封裝材130裸露，但並不限於此。在其他實施方式中，封裝材130可能覆蓋第二晶片140的第二面143。Specifically, the second surface 143 of the second wafer 140 is exposed from the packaging material 130, but is not limited thereto. In other embodiments, the packaging material 130 may cover the second surface 143 of the second wafer 140.
具體而言，導線架110的第一凹陷區域115的厚度與導線架110的第二凹陷區域119的厚度大致相同。Specifically, the thickness of the first recessed area 115 of the lead frame 110 is substantially the same as the thickness of the second recessed area 119 of the lead frame 110.
第9圖繪示依照本發明另一實施方式之封裝結構的剖面圖。如第9圖所繪示，本實施方式之封裝結構100與第8圖的封裝結構100大致相同，主要相異處在於第一凹陷區域115與第二凹陷區域119的厚度不同。在本實施方式中，第一凹陷區域115的厚度小於第二凹陷區域119的厚度。應了解到，以上所舉之第一凹陷區域115與第二凹陷區域119的厚度僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇第一凹陷區域115與第二凹陷區域119的厚度。FIG. 9 is a cross-sectional view of a package structure according to another embodiment of the present invention. As shown in FIG. 9, the package structure 100 of this embodiment is substantially the same as the package structure 100 of FIG. 8, and the main difference is that the thickness of the first recessed region 115 and the second recessed region 119 are different. In this embodiment, the thickness of the first recessed region 115 is smaller than the thickness of the second recessed region 119. It should be understood that the thicknesses of the first recessed region 115 and the second recessed region 119 mentioned above are merely examples, and are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should flexibly choose according to actual needs The thickness of the first recessed region 115 and the second recessed region 119.
因為封裝材130沒有包覆導線架110的第一面111，第一晶片120可以藉由先將熱能傳遞至導線架110，再藉由導線架110的第一面111有效地散熱。同時，因為散熱件150的第二面153自封裝材130裸露，且散熱件150的第一面151熱接觸且覆蓋第一晶片120的第二面123，第一晶片120可以藉由第一晶片120的第二面123先將熱能傳遞至散熱件150，再藉由散熱件150有效地散熱。於是，封裝結構100的散熱能力得以有效提升。Because the packaging material 130 does not cover the first surface 111 of the lead frame 110, the first chip 120 can transfer heat energy to the lead frame 110 first, and then efficiently dissipate heat through the first surface 111 of the lead frame 110. At the same time, because the second surface 153 of the heat sink 150 is exposed from the packaging material 130 and the first surface 151 of the heat sink 150 is in thermal contact with and covers the second surface 123 of the first wafer 120, the first wafer 120 can pass through the first wafer The second surface 123 of 120 first transfers thermal energy to the heat sink 150, and then efficiently dissipates heat through the heat sink 150. Therefore, the heat dissipation capability of the packaging structure 100 can be effectively improved.
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be determined by the scope of the attached patent application.
100‧‧‧封裝結構100‧‧‧ package structure
110‧‧‧導線架110‧‧‧ lead frame
111‧‧‧第一面111‧‧‧ the first side
113‧‧‧第二面113‧‧‧Second Side
115‧‧‧第一凹陷區域115‧‧‧ the first depression area
116‧‧‧第一區塊116‧‧‧ Block 1
116b‧‧‧第三區塊116b‧‧‧The third block
117‧‧‧第二區塊117‧‧‧Second Block
118‧‧‧平坦區域118‧‧‧ flat area
119‧‧‧第二凹陷區域119‧‧‧Second depression area
120‧‧‧第一晶片120‧‧‧The first chip
121‧‧‧第一面121‧‧‧ the first side
123‧‧‧第二面123‧‧‧Second Side
130‧‧‧封裝材130‧‧‧Packaging material
140‧‧‧第二晶片140‧‧‧Second chip
141‧‧‧第一面141‧‧‧ the first side
143‧‧‧第二面143‧‧‧Second Side
150‧‧‧散熱件150‧‧‧ heat sink
151‧‧‧第一面151‧‧‧First
153‧‧‧第二面153‧‧‧Second Side
第1圖繪示依照本發明一實施方式之封裝結構的立體圖。 第2圖繪示沿第1圖之切線2的剖面圖。 第3圖繪示依照本發明一實施方式之不具有封裝材的封裝結構的立體圖。 第4圖繪示依照本發明另一實施方式之封裝結構的剖面圖。 第5圖繪示依照本發明另一實施方式之封裝結構的剖面圖。 第6圖繪示依照本發明另一實施方式之封裝結構的立體圖。 第7圖繪示沿第6圖之切線7的剖面圖。 第8圖繪示依照本發明另一實施方式之封裝結構的剖面圖。 第9圖繪示依照本發明另一實施方式之封裝結構的剖面圖。FIG. 1 is a perspective view of a package structure according to an embodiment of the present invention. Fig. 2 is a cross-sectional view taken along the tangent line 2 of Fig. 1. FIG. 3 is a perspective view of a packaging structure without a packaging material according to an embodiment of the present invention. FIG. 4 is a cross-sectional view of a package structure according to another embodiment of the present invention. FIG. 5 is a cross-sectional view of a package structure according to another embodiment of the present invention. FIG. 6 is a perspective view of a packaging structure according to another embodiment of the present invention. FIG. 7 is a cross-sectional view taken along a tangent line 7 in FIG. 6. FIG. 8 is a cross-sectional view of a package structure according to another embodiment of the present invention. FIG. 9 is a cross-sectional view of a package structure according to another embodiment of the present invention.
Claims (10)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/052,899 US9748165B2 (en) | 2014-05-30 | 2016-02-25 | Packaging structure |
| US15/052,899 | 2016-02-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201731044A TW201731044A (en) | 2017-09-01 |
| TWI625833B true TWI625833B (en) | 2018-06-01 |
Family
ID=59717017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW105112755A TWI625833B (en) | 2016-02-25 | 2016-04-25 | Package structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107123633B (en) |
| TW (1) | TWI625833B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20190055662A (en) * | 2017-11-15 | 2019-05-23 | 에스케이하이닉스 주식회사 | Semiconductor package with thermal redistribution pattern |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW503491B (en) * | 1999-08-25 | 2002-09-21 | Hitachi Ltd | Semiconductor apparatus and its manufacturing method |
| TW200410380A (en) * | 2002-12-09 | 2004-06-16 | Advanpack Solutions Pte Ltd | Leadless semiconductor packaging structure with inverted flip chip and methods of manufacture |
| TW200802635A (en) * | 2006-06-13 | 2008-01-01 | Siliconware Precision Industries Co Ltd | Heat sink package structure and method for fabricating the same |
| TW200849515A (en) * | 2007-06-13 | 2008-12-16 | Siliconware Precision Industries Co Ltd | Heat dissipation type package structure and fabrication method thereof |
| TW201131712A (en) * | 2010-03-12 | 2011-09-16 | Richtek Technology Corp | Flip chip package structure with heat dissipation enhancement and its application |
| TW201545285A (en) * | 2014-05-30 | 2015-12-01 | 台達電子工業股份有限公司 | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2572564Y (en) * | 2002-09-29 | 2003-09-10 | 威盛电子股份有限公司 | Die Level Package Structure |
| JP5398269B2 (en) * | 2009-01-07 | 2014-01-29 | 三菱電機株式会社 | Power module and power semiconductor device |
| US8674497B2 (en) * | 2011-01-14 | 2014-03-18 | International Business Machines Corporation | Stacked half-bridge package with a current carrying layer |
-
2016
- 2016-04-25 CN CN201610260696.0A patent/CN107123633B/en active Active
- 2016-04-25 TW TW105112755A patent/TWI625833B/en active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW503491B (en) * | 1999-08-25 | 2002-09-21 | Hitachi Ltd | Semiconductor apparatus and its manufacturing method |
| TW200410380A (en) * | 2002-12-09 | 2004-06-16 | Advanpack Solutions Pte Ltd | Leadless semiconductor packaging structure with inverted flip chip and methods of manufacture |
| TW200802635A (en) * | 2006-06-13 | 2008-01-01 | Siliconware Precision Industries Co Ltd | Heat sink package structure and method for fabricating the same |
| TW200849515A (en) * | 2007-06-13 | 2008-12-16 | Siliconware Precision Industries Co Ltd | Heat dissipation type package structure and fabrication method thereof |
| TW201131712A (en) * | 2010-03-12 | 2011-09-16 | Richtek Technology Corp | Flip chip package structure with heat dissipation enhancement and its application |
| TW201545285A (en) * | 2014-05-30 | 2015-12-01 | 台達電子工業股份有限公司 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107123633A (en) | 2017-09-01 |
| CN107123633B (en) | 2020-03-17 |
| TW201731044A (en) | 2017-09-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101159254B (en) | Semiconductor device | |
| US7829995B2 (en) | Semiconductor device and method of fabrication | |
| TWI278976B (en) | Integrated circuit package device and method for manufacturing the same | |
| US20100084761A1 (en) | Semiconductor device and fabrication method of the same | |
| TWI551198B (en) | Printed circuit board structure with heat dissipation function | |
| CN102522380B (en) | PoP packaging structure | |
| TW201411788A (en) | Integrated circuit package and assembly method thereof | |
| TW201537719A (en) | Stacked semiconductor package | |
| TW201415587A (en) | Thermal management structure of semiconduvtor device and methods for forming the same | |
| TWI615925B (en) | Semiconductor device | |
| JP2011035352A (en) | Semiconductor device | |
| US20240274490A1 (en) | Semiconductor module | |
| CN101111935A (en) | Semiconductor device with a plurality of semiconductor chips | |
| TWI536515B (en) | Semiconductor package component with heat dissipation structure and packaging method thereof | |
| TWI625833B (en) | Package structure | |
| JPH04326557A (en) | Cooling structure of semiconductor chip | |
| TWI722633B (en) | Chip packaging structure and chip packaging module | |
| JP2007305761A (en) | Semiconductor device | |
| US7235889B2 (en) | Integrated heatspreader for use in wire bonded ball grid array semiconductor packages | |
| JPH11214448A (en) | Semiconductor device and method of manufacturing semiconductor device | |
| TW201644328A (en) | Chip package structure | |
| JP4225243B2 (en) | Semiconductor device and substrate connection structure | |
| CN112490202A (en) | Power device package structure | |
| JP4371946B2 (en) | Semiconductor device and substrate connection structure thereof | |
| JP2007036035A (en) | Semiconductor device |