TWI621231B - Chip package structure manufacturing method and substrate structure - Google Patents

Abstract

A manufacturing method of a chip package structure and a substrate structure, wherein the manufacturing method includes the following steps. First, a carrier board is provided, and the carrier board includes a substrate and a release film connected to the substrate. Next, a laminated structure layer is formed on the release film, and the laminated structure is patterned to form a pre-break groove that runs through at least a part of the laminated structure, wherein the pre-break groove is located at the edge of the laminated structure and divides the laminated structure. A part and a pre-break part are provided for the wafer. Next, a wafer is set on the wafer setting portion. Next, an encapsulant is formed on the wafer setting portion and covers the wafer. After that, the pre-break portion and the wafer setting portion are disconnected along the pre-break groove, and the release film and the substrate are removed through the pre-break portion.

Description

Manufacturing method of chip package structure and substrate structure

The invention relates to a manufacturing method and a substrate structure of a packaging structure, and more particularly to a manufacturing method and a substrate structure of a chip packaging structure.

At present, after the chip package structure is fabricated on the flexible carrier board, the flexible carrier board needs to be further removed to obtain the chip package structure. Because the chip packaging structure and the flexible carrier board are bonded to each other through a release film, and the adhesive force of the release film is not high, after applying a moderate force to the release film, the chip package structure and the The flexible carrier is separated. Since the release film is clamped between the chip packaging structure and the flexible carrier board, and in order to avoid damaging the area of the chip and the circuit, the application point is usually near the side of the chip packaging structure and / or the flexible carrier board. edge. Generally, the periphery of the chip package structure is flush with the periphery of the flexible carrier board, so it is not conducive to applying force, and the chip package structure may be damaged if it is inadvertent.

The invention provides a method for manufacturing a chip package structure and a substrate structure, which can improve the convenience and yield of a process.

The invention provides a method for manufacturing a chip package structure, which includes the following steps. First, a carrier board is provided, and the carrier board includes a substrate and a release film connected to the substrate. Next, a laminated structure layer is formed on the release film, and the laminated structure is patterned to form a pre-break groove that runs through at least a part of the laminated structure, wherein the pre-break groove is located at the edge of the laminated structure and divides the laminated structure. A part and a pre-break part are provided for the wafer. Next, a wafer is set on the wafer setting portion. Next, an encapsulant is formed on the wafer setting portion and covers the wafer. After that, the pre-break portion and the wafer setting portion are disconnected along the pre-break groove, and the release film and the substrate are removed through the pre-break portion.

In an embodiment of the present invention, the step of forming the laminated structure on the release film and patterning the laminated structure to form a pre-break trench that penetrates at least part of the laminated structure includes forming a first solder resist layer on the release film. The first solder resist is patterned on the release film to form a first trench penetrating the first solder resist, and the first trench exposes the release film. Next, a conductive layer is formed on the first solder resist layer, and the conductive layer is patterned to form a second trench penetrating the conductive layer, and the second trench is aligned with the first trench. After that, a second solder resist layer is formed on the conductive layer, and the second solder resist layer is patterned to form a third trench penetrating the second solder resist layer, and the third trench is aligned with the second trench. The pre-breaking trench is composed of a first trench, a second trench, and a third trench.

In an embodiment of the present invention, the pre-breaking portion includes a part of the first solder resist layer, a part of the conductive layer, and a part of the second solder resist layer.

In an embodiment of the present invention, the step of forming the laminated structure on the release film and patterning the laminated structure to form a pre-break trench that penetrates at least part of the laminated structure includes forming a first solder resist layer on the release film. On the release film. Next, a core layer is disposed on the first solder resist layer. Next, a conductive layer is formed on the core layer, and the conductive layer is patterned to form a first trench penetrating the conductive layer, and the first trench exposes the core layer. Next, a second solder resist layer is formed on the conductive layer, and the second solder resist layer is patterned to form a second trench penetrating the second solder resist layer, and the second trench is aligned with the first trench. The pre-breaking trench is composed of a first trench and a second trench.

In an embodiment of the present invention, the pre-breaking portion includes a part of the conductive layer and a part of the second solder resist layer.

In an embodiment of the present invention, the pre-break groove described above divides the first solder resist layer and the core layer into a first portion overlapping the wafer setting portion and a second portion overlapping the pre-break portion. When the pre-break part and the wafer setting part are disconnected along the pre-break groove, and the release film and the substrate are removed through the pre-break part, the first part and the second part are disconnected, so that the second part follows the release film and the substrate. Removed.

In an embodiment of the present invention, the step of forming the pre-break trenches penetrating through the at least partially laminated structure includes extending the pre-break trenches from a first side edge of the stacked structure to a second side connected to the first side edge. Side.

In an embodiment of the present invention, the pre-breaking groove has opposite ends, and the ends are respectively spaced from the first side and the second side.

In an embodiment of the present invention, the step of forming the pre-break trenches penetrating through the at least part of the stacked structure includes extending the pre-break trenches from the first side of the stacked structure to the first side parallel to the first side. Two sides.

The invention provides a substrate structure, which includes a carrier plate and a laminated structure. The carrier board includes a substrate and a release film connecting the substrate. The stacked structure is disposed on a release film, wherein the stacked structure has a pre-break groove, the pre-break groove is located at an edge of the stacked structure, and the stacked structure is divided into a wafer setting portion and a pre-break portion.

In an embodiment of the present invention, the above-mentioned laminated structure includes a first solder resist layer, a conductive layer, and a second solder resist layer. The first solder resist layer is disposed on the release film, wherein the first solder resist layer has a first groove, and the first groove exposes the release film. The conductive layer is disposed on the first solder resist layer, wherein the conductive layer has a second trench, and the second trench is aligned with the first trench. The second solder mask layer is disposed on the conductive layer, wherein the second solder mask layer has a third trench, the third trench is aligned with the second trench, and the pre-breaking trench is composed of the first trench, the second trench, and Composed of a third groove.

In an embodiment of the present invention, the above-mentioned laminated structure includes a first solder resist layer, a core layer, a conductive layer, and a second solder resist layer. The first solder resist is disposed on the release film. The core layer is disposed on the first solder resist layer. The conductive layer is disposed on the core layer, wherein the conductive layer has a first trench, and the first trench exposes the core layer. The second solder mask layer is disposed on the conductive layer, wherein the second solder mask layer has a second groove, the second groove is aligned with the first groove, and the pre-break groove is formed by the first groove and the second groove. composition.

In an embodiment of the present invention, the above-mentioned laminated structure has a first side edge and a second side edge connected to the first side edge, and the pre-break groove extends from the first side edge to the second side edge.

In an embodiment of the present invention, the above-mentioned laminated structure has a first side edge and a second side edge parallel to the first side edge, and the pre-break groove extends from the first side edge to the second side edge.

Based on the above, in the process of forming a laminated structure on a carrier plate to fabricate a substrate structure, the present invention forms a pre-break groove in the laminated structure through at least part of the groove. Thereby, after the fabrication of the chip package structure is completed, the carrier board can be removed through the pre-break groove. Therefore, the manufacturing method and the substrate structure of the chip packaging structure provided by the present invention can not only improve the convenience of the manufacturing process, but also avoid damage to the chip packaging structure when the carrier is removed to improve the yield of the manufacturing process.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

1A to 1E are schematic cross-sectional views illustrating a manufacturing process of a chip package structure according to a first embodiment of the present invention. Please refer to FIG. 1A. First, a carrier board 110 is provided. The carrier board 110 includes a substrate 111 and a release film 112 connecting the substrate 111. The substrate 111 may be polyester (PET) or polyurethane (PI). Flexible substrate made of other materials, used as a temporary load. However, the present invention does not limit the material of the substrate. In other embodiments, the substrate may be a rigid substrate. In this embodiment, the release film 112 may be a thin film having an upper surface 112a and a lower surface 112b, wherein the lower surface 112b of the release film 112 is attached to the substrate 111, and the upper surface of the release film 112 is 112a is exposed for subsequent bonding of the laminated structure 120 (shown in FIG. 1C).

Next, a first solder resist layer 121 is formed on the upper surface 112 a of the release film 112. After the first solder resist layer 121 is adhered to the release film 112, the first solder resist layer 121 may be patterned by means of stamping, etching, or laser cutting to form a first trench penetrating the first solder resist layer 121. 121a, and the first groove 121a exposes the upper surface 112a of the release film 112. Please refer to FIG. 1B. Next, a conductive layer 122 is formed on the first solder resist layer 121. The material of the conductive layer 122 can be copper, other conductive metals or alloys, and can be patterned by stamping, etching or laser cutting. The conductive layer 122 forms a second trench 122 a penetrating the conductive layer 122. In this embodiment, the second groove 122a is aligned with the first groove 121a. Referring to FIG. 1C, a second solder resist layer 123 is formed on the conductive layer 122, and the second solder resist layer 123 can be patterned by stamping, etching, or laser cutting to form a second solder resist layer 123. The third trench 123a is aligned with the second trench 122a. So far, the substrate structure 101 has been completed. The first trenches 121a, the second trenches 122a, and the third trenches 123a aligned with each other constitute a pre-break trench 102, and the first solder resist layer 121, the conductive layer 122, and The laminated structure 120 composed of the second solder resist layer 123 is penetrated by the pre-break groove 102 to expose the upper surface 112 a of the release film 112.

In this embodiment, the pre-break groove 102 is located at an edge of the stacked structure 120, and the stacked structure 120 is divided into a wafer setting portion 125 and a pre-break portion 126. 2A and 2B are schematic top views of two embodiments of the substrate structure of FIG. 1C, respectively. Please refer to FIG. 2A. In one embodiment, the laminated structure 120 has a first side edge 127 and a second side edge 128 connected to the first side edge 127. The pre-break groove 102 is formed from the first side edge 127. It extends to the second side edge 128 and is inclined to the first side edge 127 and the second side edge 128. The pre-break groove 102 has two opposite ends, and the two ends are spaced apart from the first side 127 and the second side 128 respectively. In other embodiments, the two opposite ends of the pre-break groove may penetrate the first side and the second side, respectively. Please refer to FIG. 2B. In another embodiment, the laminated structure 120 has a first side edge 127 and a second side edge 129 parallel to the first side edge 127. The pre-break groove 102 is formed from the first side edge. 127 extends to the second side edge 129 and is perpendicular to the first side edge 127 and the second side edge 129. The pre-breaking trench 102 has two opposite ends, and the two ends are respectively spaced from the first side 127 and the second side 129.

Please refer to FIG. 1D. Next, a second solder mask layer 123 on the wafer mounting portion 125 is disposed on the wafer 130. For example, although not shown in the drawings, the patterned second solder mask layer 123 may have multiple layers. The two openings expose parts of the patterned conductive layer 122, so the chip 130 can be electrically connected to the patterned conductive layer 122 by wire bonding or flip-chip bonding. Next, a second solder mask layer 123 of the encapsulant 140 is formed on the wafer setting portion 125 and covers the wafer 130. It is particularly noted that although this embodiment only uses a single wafer for description, it is not limited thereto. In other embodiments, a plurality of wafers can be set on the wafer setting portion, and the aforementioned gel can be collectively covered by the encapsulating gel.

Please refer to FIG. 1D and FIG. 1E. In this embodiment, the pre-break part 126 includes a part of the first solder resist layer 121, a part of the conductive layer 122, and a part of the second solder resist layer 123. Finally, the pre-break part 126 is used as a force point and The pre-breaking portion 126 and the wafer setting portion 125 are disconnected along the pre-breaking groove 102, so that the pre-breaking portion 126, the release film 112, and the substrate 111 are removed at the same time, so that the chip packaging structure 100 is separated from the carrier board 110. Since the pre-breaking part 126 can be used as a force point for removing the carrier board 110, it can not only improve the convenience of the process, but also avoid damage to the chip packaging structure 100 when the carrier board 110 is removed to improve the yield of the process. .

3A to 3F are schematic cross-sectional views of a manufacturing process of a chip package structure according to a second embodiment of the present invention. Please refer to FIG. 3A. First, a carrier board 210 is provided. The carrier board 210 includes a substrate 211 and a release film 212 connecting the substrate 211. The substrate 211 can be polyester (PET) or polyurethane (PI). Flexible substrate made of other materials. However, the present invention does not limit the material of the substrate. In other embodiments, the substrate may be a rigid substrate. In this embodiment, the release film 212 may be a thin film having an upper surface 212a and a lower surface 212b, wherein the lower surface 212b of the release film 212 is attached to the substrate 211, and the upper surface of the release film 212 is 212a is exposed for subsequent bonding of the laminated structure 220 (shown in FIG. 3D).

Next, a first solder resist layer 221 is formed on the upper surface 212 a of the release film 212. After the first solder resist layer 221 is adhered to the release film 212, a core layer 224 is disposed on the first solder resist layer 221. Please refer to FIG. 3C. Next, a conductive layer 222 is formed on the core layer 224. The material of the conductive layer 222 can be copper, other conductive metals or alloys, and the conductive layer 222 can be patterned by stamping, etching or laser cutting. To form a first trench 222a penetrating the conductive layer 222, and the first trench 222a exposes the core layer 224. Referring to FIG. 3D, a second solder resist layer 223 is formed on the conductive layer 222, and the second solder resist layer 223 can be patterned by stamping, etching, or laser cutting to form a second solder resist layer 223. The second trench 223a is aligned with the first trench 222a. So far, the substrate structure 201 has been completed. The first trench 222a and the second trench 223a aligned with each other constitute the pre-break trench 202, and the first solder resist layer 221, the core layer 224, the conductive layer 222, and the second The solder resist layer 223 constitutes a laminated structure 220. In addition, the conductive layer 222 and the second solder resist layer 223 are penetrated by the pre-break trench 202 to expose the core layer 224.

In this embodiment, the pre-break groove 202 is located at an edge of the stacked structure 220, and the stacked structure 220 is divided into a wafer setting portion 225 and a pre-break portion 226. 4A and 4B are schematic top views of two embodiments of the substrate structure of FIG. 3D, respectively. Please refer to FIG. 4A. In one embodiment, the laminated structure 220 has a first side edge 227 and a second side edge 228 connected to the first side edge 227. The pre-break groove 202 is formed from the first side edge 227. It extends to the second side edge 228 and is inclined to the first side edge 227 and the second side edge 228. The pre-breaking trench 202 has two opposite ends, and the two ends are respectively spaced from the first side 227 and the second side 228. In other embodiments, the two opposite ends of the pre-break groove may penetrate the first side and the second side, respectively.

Please refer to FIG. 4B. In another embodiment, the stacked structure 220 has a first side edge 227 and a second side edge 229 parallel to the first side edge 227, wherein the pre-break groove 202 is formed from the first side edge. 227 extends to the second side edge 229 and is perpendicular to the first side edge 227 and the second side edge 229. The pre-breaking trench 202 has two opposite ends, and the two ends are respectively spaced from the first side 227 and the second side 229. In other embodiments, the two opposite ends of the pre-break groove may penetrate the first side and the second side, respectively.

Please refer to FIG. 3E. Next, the second solder resist layer 223 of the wafer 230 is disposed on the wafer setting portion 225. For example, although not shown in the drawings, the patterned second solder resist layer 223 may have a large number of layers. The two openings expose parts of the patterned conductive layer 222. Therefore, the chip 230 can be electrically connected to the patterned conductive layer 222 through wire bonding or flip-chip bonding. Next, a second solder resist layer 223 of the encapsulant 240 on the wafer setting portion 225 is formed and covers the wafer 230.

Please refer to FIG. 3E and FIG. 3F. In this embodiment, the pre-break part 226 includes a part of the conductive layer 222 and a part of the second solder resist layer 223, and the pre-break trench 202 divides the first solder resist layer 221 and the core layer 224 into and A first portion 225 a overlapping the wafer setting portion 225 and a second portion 226 a overlapping the pre-break portion 226. Finally, the pre-breaking portion 226 is used as a force point and the pre-breaking portion 226 and the wafer setting portion 225 are disconnected along the pre-breaking groove 202, and the first portion 225a and the second portion 226a are disconnected, so that the pre-breaking portion 226, the second portion 226a, and the The mold film 212 and the substrate 211 are removed at the same time to separate the chip package structure 200 from the carrier 210. Since the pre-breaking portion 226 can be used as a force point for removing the carrier plate 210, it can not only improve the convenience of the process, but also avoid damage to the chip packaging structure 200 when the carrier plate 210 is removed to improve the yield of the process. . In this embodiment, the depth of the pre-break trench 202 is such that the core layer 224 is exposed. In other embodiments, the pre-break groove may further penetrate the core layer or the core layer and the corresponding first solder resist layer. The foregoing are all aspects that can be implemented by the present invention.

FIG. 5 is a schematic cross-sectional view of a substrate structure packaged with a plurality of wafers according to a third embodiment of the present invention. Referring to FIG. 5, the substrate structure 101 a is substantially similar to the substrate structure 101 of the first embodiment, except that the substrate structure 101 a has a longer length, so that a plurality of wafers 130 can be disposed thereon. In detail, the wafers 130 are disposed on the second solder mask layer 123 on the wafer setting portion 125. For example, although not shown in the drawings, the patterned second solder mask layer 123 may have multiple openings. Since a part of the patterned conductive layer 122 is exposed, these wafers 130 can be electrically connected to the patterned conductive layer 122 through wire bonding or flip-chip bonding. Next, a second solder mask layer 123 is formed on the chip mounting portion 125 to encapsulate the chips 130. Finally, the pre-breaking portion 126 is used as a force point and the pre-breaking portion 126 and the wafer setting portion 125 are disconnected along the pre-breaking groove 102, so that the pre-breaking portion 126, the release film 112, and the substrate 111 are removed at the same time. Similarly, the size of the substrate structure 201 of the second embodiment can be increased, and a plurality of wafers 230 are packaged thereon.

In summary, in the process of forming a laminated structure on a carrier plate to fabricate a substrate structure, the present invention forms a pre-break groove in the laminated structure to penetrate at least part of the laminated structure to divide the laminated structure into a wafer setting portion. With the pre-break section. Thereby, after the fabrication of the chip package structure is completed, the pre-break part and the chip setting part can be disconnected along the pre-break groove, and the carrier board can be removed through the pre-break part. Therefore, the manufacturing method and the substrate structure of the chip packaging structure provided by the present invention can not only improve the convenience of the manufacturing process, but also avoid damage to the chip packaging structure when the carrier is removed to improve the yield of the manufacturing process.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100, 200‧‧‧ chip package structure

101, 101a, 201‧‧‧ substrate structure

102, 202‧‧‧pre-break groove

110, 210‧‧‧ carrier board

111, 211‧‧‧ substrate

112, 212‧‧‧ release film

112a, 212a‧‧‧ Top surface

112b, 212b‧‧‧ lower surface

120, 220‧‧‧ stacked structure

121, 221‧‧‧ first solder mask

121a, 222a‧‧‧First groove

122, 222‧‧‧ conductive layer

122a, 223a‧‧‧Second groove

123, 223‧‧‧Second solder mask

123a‧‧‧Third groove

125, 225‧‧‧ Wafer Setting Department

126, 226‧‧‧Pre-break section

127, 227‧‧‧ First side

128, 129, 228, 229‧‧‧ second side

130, 230‧‧‧ chips

140, 240‧‧‧ encapsulated colloid

224‧‧‧Core layer

225a‧‧‧Part I

226a‧‧‧Part Two

1A to 1E are schematic cross-sectional views illustrating a manufacturing process of a chip package structure according to a first embodiment of the present invention. 2A and 2B are schematic top views of two embodiments of the substrate structure of FIG. 1C, respectively. 3A to 3F are schematic cross-sectional views of a manufacturing process of a chip package structure according to a second embodiment of the present invention. 4A and 4B are schematic top views of two embodiments of the substrate structure of FIG. 3D, respectively. FIG. 5 is a schematic cross-sectional view of a substrate structure packaged with a plurality of wafers according to a third embodiment of the present invention.

Claims (20)

A manufacturing method of a chip packaging structure includes: providing a carrier board, and the carrier board includes a substrate and a release film connected to the substrate; forming a laminated structure layer on the release film and patterning the same; The stacked structure to form a pre-break groove that runs through at least part of the stacked structure, wherein the pre-break groove is located at an edge of the stacked structure, and the stacked structure is divided into a wafer setting portion and a pre-break portion; Setting a wafer on the wafer setting portion; forming a packaging gel on the wafer setting portion and covering the wafer; and disconnecting the pre-breaking portion and the wafer setting portion along the pre-breaking groove and moving through the pre-breaking portion Remove the release film and the substrate. The method for manufacturing a chip package structure according to item 1 of the scope of patent application, wherein the laminated structure is formed on the release film, and the laminated structure is patterned to form the pre-break through at least part of the laminated structure. The step of trenching includes: forming a first solder resist layer on the release film, and patterning the first solder resist layer to form a first trench penetrating the first solder resist layer, and the first The trench exposes the release film; a conductive layer is formed on the first solder resist layer, and the conductive layer is patterned to form a second trench penetrating the conductive layer, and the second trench and the The first trenches are aligned; and a second solder mask layer is formed on the conductive layer, and the second solder mask layer is patterned to form a third trench penetrating the second solder mask layer, and the first trench Three grooves with the second The grooves are aligned, and the pre-breaking groove is composed of the first groove, the second groove, and the third groove. The method for manufacturing a chip package structure according to item 2 of the scope of the patent application, wherein the pre-break part includes a part of the first solder resist layer, a part of the conductive layer, and a part of the second solder resist layer. The method for manufacturing a chip package structure according to item 1 of the scope of patent application, wherein the laminated structure is formed on the release film, and the laminated structure is patterned to form the pre-break through at least part of the laminated structure The step of trenching includes: forming a first solder resist layer on the release film; providing a core layer on the first solder resist layer; forming a conductive layer on the core layer and patterning the conductive layer, Forming a first trench penetrating the conductive layer, and the first trench exposing the core layer; and forming a second solder resist layer on the conductive layer, and patterning the second solder resist layer to A second trench is formed through the second solder resist layer, and the second trench is aligned with the first trench. The pre-breaking trench is composed of the first trench and the second trench. The method for manufacturing a chip package structure according to item 4 of the scope of the patent application, wherein the pre-break part includes a part of the conductive layer and a part of the second solder resist layer. The method for manufacturing a chip package structure according to item 4 of the scope of the patent application, wherein the pre-break groove divides the first solder resist layer and the core layer into a first portion overlapping the wafer setting portion and the pre-break A second part overlapping with each other, when the pre-break part and the wafer setting part are disconnected along the pre-break groove, and pass through the pre-break When the release film and the substrate are removed by a broken portion, the first portion and the second portion are disconnected, so that the second portion is removed along with the release film and the substrate. The method of manufacturing a chip package structure according to item 1 of the scope of patent application, wherein the step of forming the pre-break trenches penetrating at least part of the stacked structure includes moving the pre-break trenches from a first side of the stacked structure It extends to a second side edge connected to the first side edge. According to the manufacturing method of the chip package structure described in item 7 of the patent application scope, wherein the pre-breaking trench has opposite two ends, and the two ends are respectively spaced from the first side and the second side. The method of manufacturing a chip package structure according to item 1 of the scope of patent application, wherein the step of forming the pre-break trenches penetrating at least part of the stacked structure includes moving the pre-break trenches from a first side of the stacked structure Extending to a second side parallel to the first side. The method for manufacturing a chip package structure according to item 9 of the scope of the patent application, wherein the pre-breaking trench has two opposite ends, and the two ends are respectively spaced from the first side and the second side. A substrate structure includes: a carrier board including a substrate and a release film connected to the substrate; and a laminated structure disposed on the release film, wherein the laminated structure has a pre-break groove, The pre-break groove is located at an edge of the stacked structure, and the stacked structure is divided into a wafer setting portion and a pre-break portion. The stacked structure includes a conductive layer, and the pre-break groove passes through the conductive layer. The substrate structure according to item 11 of the patent application scope, wherein the laminated structure further comprises: a first solder resist layer disposed on the release film, wherein the first solder resist layer has a first trench, And the first trench exposes the release film, the conductive layer is disposed on the first solder resist layer, wherein the conductive layer has a second trench, and the second trench is opposite to the first trench And a second solder mask layer disposed on the conductive layer, wherein the second solder mask layer has a third groove, the third groove is aligned with the second groove, and the pre-break groove Consists of the first trench, the second trench, and the third trench. The substrate structure according to item 12 of the application, wherein the pre-break part includes a part of the first solder resist layer, a part of the conductive layer, and a part of the second solder resist layer. The substrate structure according to item 11 of the scope of patent application, wherein the laminated structure further comprises: a first solder resist layer disposed on the release film; a core layer disposed on the first solder resist layer, The conductive layer is disposed on the core layer, wherein the conductive layer has a first trench, and the first trench exposes the core layer; and a second solder resist layer is disposed on the conductive layer, wherein the The second solder mask layer has a second groove, the second groove is aligned with the first groove, and the pre-breaking groove is composed of the first groove and the second groove. The substrate structure according to item 14 of the scope of patent application, wherein the pre-break part includes a part of the conductive layer and a part of the second solder resist layer. The substrate structure according to item 14 of the scope of the patent application, wherein the pre-break groove divides the first solder resist layer and the core layer into a first portion overlapping the wafer setting portion and a portion overlapping the pre-break portion. One second part. The substrate structure according to item 11 of the scope of patent application, wherein the laminated structure has a first side edge and a second side edge connected to the first side edge, and the pre-break groove is from the first side The edge extends to the second edge. The substrate structure according to item 17 of the scope of patent application, wherein the pre-break groove has two opposite ends, and the two ends are respectively spaced from the first side and the second side. The substrate structure according to item 11 of the scope of patent application, wherein the stacked structure has a first side edge and a second side edge parallel to the first side edge, and the pre-break groove is formed from the first The side edge extends to the second side edge. The substrate structure according to item 18 of the scope of the patent application, wherein the pre-break groove has opposite ends, and the ends are respectively spaced from the first side and the second side.