201126715 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種高壓金屬氧化物半導體元件，特別是指 一種定義p型摻雜區範圍，以加強元件崩潰防護電壓 (breakdown voltage)之N型高壓金屬氧化物半導體元件，或 降低元件導通阻值(ON resistance)之P型該高壓金屬氧化物半 導體元件。本發明也有關於一種高壓金屬氧化物半導體元件的 製作方法。 【先前技術】 金屬氧化物半導體元件源極與沒極間的崩潰防護電壓取 決於源極與汲極間的PN接面。舉例而言，突崩潰 breakdown)的發生肇因於PN接面空乏區電場的升高，因此也 限制了源極與汲極所能施加的電壓。若崩潰發生於源極與沒 極間的PN接面’會使源極與汲極間的電流急速升高，且造 成PN接面的損壞以及MOS元件的功能失常。 第1圖顯示先前技術N型高壓金屬氧化物半導體元件的 I構’包括·半導體基板11、P型井區12a、N型漂移區(d!讯 region)14a、N型源極15a、N型汲極18a、N型淡摻雜區16a、 臨界電壓調整P型摻雜區19a、以及閘極結構17。其中，>^型 淡摻雜區16a以及N型漂移區14a都有加強該N型高壓金屬 氧化物半導體元件崩潰防護電壓的作用。兩者皆是在濃摻雜 區源極15a或汲極15b與P型井區12a間的PN接面，摻雜濃 度較淡的N型雜質，以增加pn接面空乏區寬度，以加強該N 型高壓金屬氧化物半導體元件崩潰防護電壓。. 隨著元件尺寸的縮小與高壓元件所需承受的電壓的増 201126715 加，上述的先前技術也遇到無法突破的瓶頸。因為上述的先 前技術雖然增強了崩潰防護電壓，卻犧牲了另一個重要的元 件操作參數，即導通電阻。 反過來說’p型高壓金屬氧化物半導體元件則有降低導通 電阻的瓶頸。 有鑑於此，本發明即針對上述先前技術之不足，提出一種 能夠增強N型高壓金屬氧化物轉體元件崩潰防護電壓且不 犧牲導通電阻，以及能夠降低p型高壓金屬氧化物半導體元 件導通電阻且不犧牲崩潰防護賴的高壓金屬氧化 元件與製作方法。 【發明内容】 _本發明目的之-在提供型高壓金屬氧化物半導體 疋件，能夠增強元件崩潰防護電壓且不犧牲導通電阻。 —本發明目的之-在提供―種p型高壓金屬氧化物半 元件i夠降低導通電阻且;^犧牲元件崩潰防護電麗。 雜元目的缺供—種製偏壓金魏化物半導 為達上述之目的，就其中一個觀點言，本發 一 ’包含：—基板；位於該基板 表面上之-_結構；倾該基 面視之此Ρ型賴在水平 從頂 區内部之—第—^上構成-兀件區；位於該ρ型井 源極;位於該第一 Ν型漂移區内部 極結構以該第-Ν型漂 ^其與該開 第-Ν型w老 ^開乂及位於§亥ρ型井區與該 第Ν“狐父界處且僅涵蓋部份元件區之一第一 ρ型摻 201126715 雜區，該第一 p型摻雜區係以離子植入技術，植入p型雜質， 以加強該兩壓金屬氧化物半導體元件之崩潰電壓。 在其中一種實施型態中，從剖面圖視之，該第一 p型摻 雜區之一端至多延伸至該N型汲極中點，另一端至少延伸至 該閘極結構下方一部份。 • 上述高壓金屬氧化物半導體元件可為對稱元件或非對稱 _ 疋件，當其為非對稱元件時，宜設置一與該N型源極部分重 疊且部分位於該閘極下方之N型輕摻雜區。當其為對稱元件 • 時’宜設置一位於該P型井區内部之-第二N型漂移區，以 隔開该N型源極與該閘極結構；以及位於該p型井區與該第 二N型漂移區交界處且僅涵蓋部份元件區之一第二p型^雜 區。 "、 …就另一個觀點言，本發明也提供了一種高壓金屬氧化物 半導體7L件’包含··—基板；位於該基板表面上之一閑極結 構；位於該基板内部之一 N型井區，從頂面視之此\型井^ 在水平面上構成一元件區；位於該N型井區内部之一第一 p • 型漂^區；位於該㈣井區内部之-p型源極；位於該第一 P型漂移_部之—P魏極’其與該_結構以該第一 p 型漂移區隔開；以及位於該p魏極與該第—P型漂移區交 . 界處且僅涵蓋部份元件區之—第-P型摻_，該第一 p型 • f雜區係贈子植人髓，植人P型雜質，崎低該高壓金 屬氧化物半導體元件之導通阻值。 在其中-種實施型態中，從剖_視之，該第—p型摻 雜區之i至多延伸至該N型井區與第型漂移區之交界 處0 上述南壓金屬氧化物半導體元件可為對稱元件或非對稱 201126715 疋件，當其為非對稱元件時’宜設置一與該p型源極部分重疊 且部分位於該閘極下方之P型輕摻雜區。當其為對稱元件時， 宜設置一位於該N型井區内部之一第二P型漂移區，以隔開 該P型源極與該閘極結構；以及位於該N型井區與該第二p 型你移區交界處且僅涵蓋部份元件區之一第二p型摻雜區， 其中從剖面圖視之，該第二p型摻雜區之一端至多延伸至該N 型井區與第二p型漂移區之交界處。 Λ 就再另一個觀點言，本發明提供了一種製作高壓金屬氧 化物半導體元件之方法，包含以下步驟:提供一基板；於該基 板内部形成-第-導電型井區，從頂面視之此第—導電 區在水平面上構成4件區；於該第一導電型井區内部形成 -第二導電型之漂移區；位於該基板表面上，形成 構；於該第-導電型井區内部形成—第二導電型源極；於= 第-漂移區内部形成-第二導電型汲極，其與該閘極結構^ 該漂移區隔開；以及以離子植人技術，植人ρ型雜質，以於 該基板表φ下方形成-不涵蓋整個元件區的ρ雜雜區，以 在調整臨界職的_加強辭導體元件之赌 降低該半導體元件之導通阻值。 α 上述製作高壓金魏化物半導體元件之方法巾第 】型：為Ρ型’第二導電型可為Ν型;或該第一導電型為Ν 里，第一導電型為！>型。其中形成該ρ型摻雜區之離子植入 技術之參數制宜為：加速賴顏—萬電子伏特至二十萬 電子伏特；植人之離子為含_銦之離子；植 方公分1Ε12至1Ε14個離子。 』里句母十 底下藉由具體實施例詳加朗，當更容純解本發明之 目的、技術内容、特點及其所達成之功效。 201126715 【實施方式】 本發明巾的赋均屬示意，主要意在表示製程步驟以及各 層之間之上下次序_ ’至於職、厚度減度職未依照比 例繪製。 請參閱第2A_2F之·流程圖，顯示本發_第一實施 . 例’本實施例顯示N型高壓金屬氧化物半導體 、製作方法。如第从圖所示，首先提供—基板n，接著= 影技術與離子植人技術於基板u中定義出p型井區以， • 從頂面視之’此p型井區在水平面上構成-元件區100。接 下來’如第2B圖所示，於基板u中形成隔離區13，該隔 離區13可以為區域氧化（L〇c〇s)或淺溝槽絕緣（奶）製 程技術所形成。接下來，如第2C圖所示，以微影技術盥離 子植入技術於p型井區12a中定義型第一漂移區14a。 再接下來，如第2D圖所示，以微影技術與離子植入技 術於P型井區12a與N型第一漂移區14a交界處，形成一第 一 P型摻雜區1%，該第-p型摻雜區1%係以離子植入技術， • 植入P型雜質所形成；此第一 P型摻雜區1%可提高該^[型 高壓金屬氧化物半導體元件之崩潰防護電壓，且不犧牲導通 電阻。不但如此，形成此第一 P型摻雜區19b的步驟可以與 . 調整臨界電壓的離子植入步驟(VT implant)整合，亦即利用原 ， 本元件所需的臨界電壓調整步驟，在不增加光罩與製程步驟的 障况下，僅是更動光罩的佈局，即可達成本發明的效果。詳 言之，先前技術中之臨界電壓調整步驟係暴露出整個元件， 對7L件區作全面性植入，本發明則是僅打開該p型井區12a 與該N型第一漂移區14a交界處，其範圍請先參照第2F圖， 一端至多延伸至汲極區18a中點，另一端則至少延伸至閘極 201126715 =構π下方的-部分，如第2F圖中之虛線部分所定義之區 Ξ之::離==製程參數’亦可以採用臨界電壓調 定為:加速電壓範圍-萬電子伏 特至一十萬電子伏H之離子為含 劑量為每平方公分m…14個離子。此 麵’且不犧牲導通電阻， 罩、製程步驟、狀變其他製程參數（例如並未 g 點之— =熱預雜_i bud剛），糊_ = =來如第2E圖所示，於基板„上形成閘極結構17 的一部分，包含閘極介電層17a與閘極導電層m。第邛圖 顯不以自我對準技術、微影技術、侧技術、與離子植入技 =形成N型淡摻雜區16a、於間極側壁形成間極間隔層^(此 f開極結構17的一部分）、以及形成N型源極15a與N型汲 8a其中’ N型淡摻雜區恤與N型源極i5a部分重疊且 部分位於該閘極結構17的下方。 第3圖示出本發明的第二實施例，本實施例為—p型高i 屢金屬氧化物半導體元件。該p型高麗金屬氧化物半導體元 件之製作流程與本發明的第—實施例主要的差異，除了本實施 例包含N型井區12b、第一 p型漂移^4b、p型雜i5b、p . 型沒極18b、以及P型淡換雜區16b與前述N型高麗金屬氧化， 物半導體元件關之外’主要在於p型摻腿1%是定 ，於P型沒極18b與P型第一漂移區14b交界處，其範圍一 端至多延伸至N型井區12b與第-P型漂移區14b的交界處， 另一端則沒有限制（如虛線與箭號所示），而其離子植入步驟 8 201126715201126715 VI. Description of the Invention: [Technical Field] The present invention relates to a high-voltage metal oxide semiconductor device, and more particularly to an N-type defining a range of p-type doping regions to enhance component breakdown voltage A high voltage metal oxide semiconductor device, or a P-type high voltage metal oxide semiconductor device that reduces the ON resistance of the device. The present invention also relates to a method of fabricating a high voltage metal oxide semiconductor device. [Prior Art] The breakdown protection voltage between the source and the gate of the metal oxide semiconductor device depends on the PN junction between the source and the drain. For example, the occurrence of a breakdown breakdown is due to an increase in the electric field in the PN junction depletion region, thus limiting the voltage that can be applied to the source and drain electrodes. If the collapse occurs at the PN junction between the source and the gate, the current between the source and the drain is rapidly increased, and the PN junction is damaged and the MOS device is malfunctioning. 1 shows an I structure of a prior art N-type high-voltage metal oxide semiconductor device including a semiconductor substrate 11, a P-type well region 12a, an N-type drift region (d! region) 14a, an N-type source 15a, and an N-type. The drain electrode 18a, the N-type lightly doped region 16a, the threshold voltage adjustment P-type doped region 19a, and the gate structure 17 are provided. Among them, the <^ type lightly doped region 16a and the N type drift region 14a both have the effect of enhancing the collapse protection voltage of the N-type high voltage metal oxide semiconductor device. Both of them are PN junctions between the source 15a or the drain 15b of the heavily doped region and the P-type well region 12a, doped with a lighter N-type impurity to increase the width of the pn junction depletion region to enhance the N-type high voltage metal oxide semiconductor device breakdown protection voltage. As the size of the components shrinks and the voltage that the high-voltage components are subjected to, the above-mentioned prior art also encounters a bottleneck that cannot be broken. Because the prior art described above enhances the crash protection voltage, it sacrifices another important component operating parameter, the on-resistance. Conversely, the 'p-type high-voltage metal oxide semiconductor device has a bottleneck for reducing the on-resistance. In view of the above, the present invention is directed to the deficiencies of the prior art described above, and provides an enhancement of the N-type high voltage metal oxide swivel element collapse protection voltage without sacrificing on-resistance and the ability to reduce the on-resistance of the p-type high voltage MOS device. High-pressure metal oxide components and methods of fabrication without sacrificing crash protection. SUMMARY OF THE INVENTION It is an object of the present invention to provide a high voltage metal oxide semiconductor device capable of enhancing a component breakdown protection voltage without sacrificing on-resistance. - the object of the present invention - to provide a p-type high voltage metal oxide half-element i capable of reducing the on-resistance and the sacrificial element collapse protection. The lack of supply of impurities - the preparation of biased gold-based derivative semi-conducting for the above purposes, in one of the points of view, the present invention contains: - the substrate; the - _ structure on the surface of the substrate; Ρ Ρ 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ^ It is the same as the opening type - w 老 老 乂 乂 乂 乂 乂 乂 乂 乂 乂 乂 § § § § § § ρ ρ ρ ρ ρ ρ ρ ρ ρ ρ ρ ρ ρ ρ ρ ρ ρ ρ ρ ρ ρ ρ ρ ρ ρ ρ The first p-type doping region is implanted with p-type impurities by ion implantation technology to enhance the breakdown voltage of the two-voltage metal oxide semiconductor device. In one embodiment, the cross-sectional view is One end of a p-type doped region extends at most to the midpoint of the N-type drain, and the other end extends at least to a portion below the gate structure. • The high-voltage MOS device can be a symmetrical element or an asymmetrical _ 疋a component, when it is an asymmetric component, it is preferable to provide a portion overlapping with the N-type source portion An N-type lightly doped region located below the gate. When it is a symmetrical element, a second N-type drift region located inside the P-type well region should be disposed to separate the N-type source from the a gate structure; and a second p-type impurity region at a boundary between the p-type well region and the second N-type drift region and covering only one of the component regions. ", ... In another aspect, the present invention A high-voltage metal oxide semiconductor 7L device is also provided, including a substrate; a dummy structure on the surface of the substrate; and an N-type well region inside the substrate, which is viewed from the top surface. Forming an element region on a horizontal surface; a first p-type drift region located inside the N-type well region; a -p-type source region located inside the (4) well region; and located at the first P-type drift_ portion a P-pole is separated from the first p-type drift region by the first p-type drift region; and is located at the intersection of the p-electrode and the first-P-type drift region and covers only a part of the component region - the -P Type-doped _, the first p-type•f-hetero-system gives a seed to implant the human marrow, implants P-type impurities, and lowers the conduction resistance of the high-voltage metal oxide semiconductor device In the embodiment, the i-type doping region i extends at most to the junction of the N-type well region and the first-type drift region. The semiconductor component can be a symmetric component or an asymmetric 201126715 component. When it is an asymmetric component, a P-type lightly doped region partially overlapping the p-type source and partially below the gate should be provided. In the case of a symmetrical element, a second P-type drift region located inside the N-type well region is preferably provided to separate the P-type source from the gate structure; and the N-type well region and the second p-type At the junction of your hand, and covering only one of the second p-type doped regions of the component region, wherein from the cross-sectional view, one end of the second p-doped region extends at most to the N-well region and the second The junction of the p-type drift region. Λ In still another aspect, the present invention provides a method of fabricating a high voltage metal oxide semiconductor device, comprising the steps of: providing a substrate; forming a first-conducting well region inside the substrate, viewed from the top surface The first conductive region forms 4 regions on the horizontal surface; a drift region of the second conductivity type is formed inside the first conductive well region; a structure is formed on the surface of the substrate; and a structure is formed inside the first conductive well region a second conductivity type source; a second conductivity type drain formed inside the first drift region, which is spaced apart from the gate structure; and an ion implantation technique for implanting a p-type impurity, The ρ impurity region of the entire device region is formed under the substrate table φ to reduce the on-resistance of the semiconductor device in the adjustment of the critical position. α The above-mentioned method for producing a high-voltage gold-based semiconductor device is of the type: the second type can be a Ν type; or the first conductivity type is Ν, the first conductivity type is! > type. The parameter of the ion implantation technique for forming the p-type doping region is: accelerating Laiyan-wan electron volts to 200,000 electron volts; implanting ions are ions containing _indium; planting centimeters is 1Ε12 to 1Ε14 Ions. In the following, the specific examples are given by Lang Lang, and the purpose, technical content, characteristics and effects achieved by the present invention are more purely explained. 201126715 [Embodiment] The assignment of the towel of the present invention is schematically indicated, and is mainly intended to indicate that the process steps and the order of the top and bottom layers between the layers are not drawn according to the ratio. Referring to the flowchart of the 2A_2F, the present invention is shown in the first embodiment. Example This embodiment shows an N-type high voltage metal oxide semiconductor and a method of fabricating the same. As shown in the figure, the substrate n is first provided, followed by the shadow technique and the ion implantation technique to define the p-type well region in the substrate u, and • from the top surface, the p-type well region is formed on a horizontal surface. - Component area 100. Next, as shown in Fig. 2B, an isolation region 13 is formed in the substrate u, and the isolation region 13 may be formed by a region oxidation (L〇c〇s) or shallow trench insulation (milk) process technology. Next, as shown in Fig. 2C, the first drift region 14a is defined in the p-type well region 12a by the lithography technique. Next, as shown in FIG. 2D, a first P-type doping region is formed at a boundary between the P-type well region 12a and the N-type first drift region 14a by lithography and ion implantation technology, and the first P-type doping region is formed by 1%. 1% of the first-p-type doping region is formed by ion implantation technology, • implanted with P-type impurities; this first P-type doped region 1% can improve the collapse protection of the high-voltage metal oxide semiconductor device Voltage without sacrificing on-resistance. Moreover, the step of forming the first P-type doping region 19b can be integrated with the VT implant step of adjusting the threshold voltage, that is, using the threshold voltage adjustment step required by the original device, without increasing Under the circumstance of the reticle and the process step, the effect of the present invention can be achieved only by the layout of the reticle. In detail, the threshold voltage adjustment step in the prior art exposes the entire component, and the 7L component region is fully implanted, and the present invention opens only the p-type well region 12a and the N-type first drift region 14a. For the range, please refer to the 2F figure first, one end extends at most to the midpoint of the drain region 18a, and the other end extends at least to the gate 201126715 = the portion below the π, as defined by the dotted line in the 2F figure. The zone:: from == process parameters can also be set to a threshold voltage: acceleration voltage range - 10,000 electron volts to 100,000 electron volts H of ions with a dose of m ... 14 ions per square centimeter. This side' does not sacrifice the on-resistance, the mask, the process steps, the other process parameters (for example, no g-points - = heat pre-mix _i bud just), paste _ = = as shown in Figure 2E, A portion of the gate structure 17 is formed on the substrate „, including the gate dielectric layer 17a and the gate conductive layer m. The second figure is not formed by self-alignment technology, lithography technology, side technology, and ion implantation technology. The N-type lightly doped region 16a forms a spacer spacer layer (the portion of the f open-pole structure 17) on the sidewall of the interpole, and forms an N-type source 15a and an N-type 汲8a, wherein the 'N-type lightly doped region shirt Partially overlapping with the N-type source i5a and partially below the gate structure 17. Fig. 3 shows a second embodiment of the present invention, which is a p-type high-order metal oxide semiconductor device. The main difference between the fabrication process of the Koryo metal oxide semiconductor device and the first embodiment of the present invention is that the N-well region 12b, the first p-type drift ^4b, the p-type hybrid i5b, and the p-type are not included in this embodiment. The pole 18b and the P-type light-changing region 16b are in contact with the aforementioned N-type Koryo metal oxide, and the semiconductor element is off. The p-type leg is 1% defined at the junction of the P-type dipole 18b and the P-type first drift region 14b, and one end of the range extends at most to the junction of the N-type well region 12b and the P-type drift region 14b. There is no limit at the other end (as indicated by the dotted line and arrow), and its ion implantation step 8 201126715
之製程參數’亦可以採祕界電壓罐之參數，其較佳之參 數設定為：加速賴制一萬電子伏特至二十萬電子伏特； 植人之離子為含之離子；植人劑量為每平方公分 1E12至1E14個離子。此步驟利用通道中橫向濃度的變化， 用以降低導通阻值卻不犧牲崩潰電壓。同樣地，形成此第- P • 雜祕19b的步驟可哺罐臨界電壓的軒植人步驟整 5，只需更動光罩的佈局，達成本發明的效果。 月'J述兩實轭例為非對稱元件，第4圖顯示本發明的另一 • 個實施例’本實施例為一N型高壓金屬氧化物半導體對稱元 件’與第一實施例的主要差異，在於P型井區12a内省略N 型淡摻雜區16a’但增加一第二；^型漂移區14c，隔開問極結 構17與N型源極i5a，使源極15a也可以施加高電壓❶此外 本實施例亦增加位於P型井區12a與第工㈣漂移區14c交 界處之第二P型摻雜區19c，此第二p型捧雜區⑼係以離 子植入技術’植入P型雜質，以加強該高壓N型金屬氧化物 半，體對稱元件之崩潰電塵。同樣地，此第二P型摻雜區19c 鲁鳊至多延伸至源極區l5a中點，另一端則至少延伸至閘極 結構17下方的一部分。 第5圖顯示為本發明的又一個實施例，本實施例為一 p型 高壓金屬氧化物半導體對稱元件，與第二實施例的主要差異， 在於N型井區i2b内省略p型淡摻雜區〗仍，但增加一 p型第 一π移區14d ’隔開閘極結構17與p型源極15b，此外本實 施例亦增加位於P型源極15b與第二p型漂移區14d交界處 之第二P型摻雜區19c，該第二p型掺雜區丨％係以離子植入 技術’植人P娜質，以進―步降低該紐P型金屬氧化物 半導體對稱元件之導通阻值。 201126715 以上已針對較佳實施例來說明本發明，唯以上所述者， 僅係為使熟悉本技術者易於了解本發明的内容而已並非甩 來限定本發明之權利棚。在本發明之相同精神下，熟悉本 技術者可以思及各種等效變化。例如，在不影響元件主要的 特性下，可加入其他製程步驟或結構，如深井區等；又如， 微影技術並祕於光罩技術，亦可包含電子束微f彡技術。此 外，在第1·5 ®中，汲極18a/18b係與閘極間隔層nc對齊， 此暗示各實酬巾之祕18a/18b係使用自我解方式，以間 極結構為遮罩作離子植人卿成，但本發明不限於此，没極 18a/18b不使用自我對準方式形成，亦屬可行，例如第6、7圖。 因此，本發明的範圍應涵蓋上述及其他所有等效變化。 【圖式簡單說明】 第1圖7歧前技術型紐金屬氧化物轉航件 視圖。 σ 第2A-2F目科本發明的帛-實細的剖視圖。 第3-5圖不出本發明的另外三種實施例的剖視圖。 第卜7圖示出本發明的其他實施例的剖視圖，其中沒極18a/18b 不使用自我對準方式形成。 【主要元件符號說明】 11基板 12a P型井區 12b N型井區 13隔離區 14a第一 N型漂移區 14b第一 P型漂移區 14c第二N型漂移區 14d第二P型漂移區 15a N型源極 15b P型源極 201126715 16a N型淡摻雜區 16b P型淡摻雜區 17閘極結構 17a閘極介電層 17b閘極導電層 17c閘極間隔層 18a N型汲極 18b P型汲極 19a臨界電壓調整P型摻雜區 19b第一 P型摻雜區 19c第二P型摻雜區The process parameter 'can also adopt the parameters of the secret voltage tank. The preferred parameters are set to: accelerate the tens of thousands of electron volts to 200,000 electron volts; the implanted ions are contained ions; the implant dose is per square 1E12 to 1E14 ions. This step takes advantage of changes in the lateral concentration in the channel to reduce the turn-on resistance without sacrificing the breakdown voltage. Similarly, the step of forming the first - P • complication 19b can be used to adjust the threshold voltage of the canister, and only needs to change the layout of the reticle to achieve the effect of the present invention. The two yoke examples are asymmetrical elements, and FIG. 4 shows another embodiment of the present invention. This embodiment is a main difference between the N-type high-voltage metal oxide semiconductor symmetrical element and the first embodiment. The N-type lightly doped region 16a' is omitted in the P-type well region 12a, but a second type-type drift region 14c is added, and the source-pole structure 17 and the N-type source electrode i5a are separated, so that the source 15a can also be applied high. Voltage ❶ In addition, in this embodiment, the second P-type doping region 19c located at the boundary between the P-type well region 12a and the fourth (four) drift region 14c is also added, and the second p-type doping region (9) is implanted by ion implantation technology. P-type impurities are added to strengthen the collapsed electric dust of the high-voltage N-type metal oxide half-body symmetrical element. Similarly, the second P-type doping region 19c is reluctantly extended to a midpoint of the source region 15a, and the other end extends at least to a portion below the gate structure 17. Fig. 5 is a view showing still another embodiment of the present invention. This embodiment is a p-type high-voltage metal oxide semiconductor symmetrical element. The main difference from the second embodiment is that the p-type light doping is omitted in the N-type well region i2b. The area is still, but a p-type first π-shift region 14d' is added to separate the gate structure 17 from the p-type source 15b. In addition, the present embodiment also increases the boundary between the P-type source 15b and the second p-type drift region 14d. Wherein the second P-type doped region 19c, the second p-type doped region 丨% is implanted with P-nano by an ion implantation technique to further reduce the New P-type metal oxide semiconductor symmetrical element Conduction resistance. The present invention has been described with reference to the preferred embodiments thereof, and the above description is merely intended to be illustrative of the invention and is not intended to limit the scope of the invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as deep well areas, may be added without affecting the main characteristics of the components; for example, lithography may be used in reticle technology, and may also include electron beam micro-f彡 technology. In addition, in the 1st 5th, the drain 18a/18b is aligned with the gate spacer nc, suggesting that the secret 18a/18b of each pay towel uses a self-solution method, and the interpolar structure is used as a mask as an ion.植人卿成, However, the invention is not limited thereto, and it is also feasible that the immersed 18a/18b is formed without self-alignment, such as Figures 6 and 7. Therefore, the scope of the invention should be construed as covering the above and all other equivalents. [Simple description of the diagram] Figure 1 shows the view of the prior art metal oxide transfer parts. σ 2A-2F is a cross-sectional view of the present invention. Figures 3-5 illustrate cross-sectional views of three other embodiments of the present invention. Figure 7 is a cross-sectional view showing another embodiment of the present invention in which the poles 18a/18b are formed without self-alignment. [Major component symbol description] 11 substrate 12a P-type well region 12b N-type well region 13 isolation region 14a first N-type drift region 14b first P-type drift region 14c second N-type drift region 14d second P-type drift region 15a N-type source 15b P-type source 201126715 16a N-type lightly doped region 16b P-type lightly doped region 17 gate structure 17a gate dielectric layer 17b gate conductive layer 17c gate spacer layer 18a N-type drain electrode 18b P-type drain 19a threshold voltage adjustment P-type doped region 19b first P-type doped region 19c second P-type doped region