TWI620358B - Memory structure and manufacturing method of the same - Google Patents

Abstract

A memory structure and a method of fabricating the same are provided herein. The memory structure includes a substrate and a resistor. The substrate has a groove. A resistor is disposed in the trench. The resistor includes a body and two connections. The body includes a bottom and two tops. The bottom is located in the groove and the tops are located on the bottom separately from each other. The connections are located on the top of the two. The resistivity of the connecting portion is smaller than the resistivity of the body.

Description

Memory structure and manufacturing method thereof

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a memory structure and a method of fabricating the same.

The resistors are widely used in various semiconductor devices. For example, resistors used in memory devices include resistors with higher impedance values and resistors with lower impedance values. Generally, in a two-dimensional memory device, a floating gate type resistor is used as a resistor having a relatively high impedance value, and a gate type resistor is used as a resistor having a low impedance value. Resistors used in three-dimensional memory devices, especially those with higher impedance values, are still evolving.

The present invention provides a memory structure including a novel resistor and a method of fabricating the same. The manufacturing method of such a resistor can be integrated with the manufacturing method of the array region of the memory.

According to some embodiments, a memory structure includes a substrate and a resistor. The substrate has a groove. A resistor is disposed in the trench. The resistor includes a body and two connections. The body includes a bottom and two tops. The bottom is located in the groove and the tops are located on the bottom separately from each other. The connections are located on the top of the two. Connection part The resistance is less than the resistivity of the body.

According to some embodiments, a method of fabricating a memory structure includes the following steps. First, a trench is formed in a substrate. A body forming a resistor. The body includes a bottom and two tops. The bottom is located in the groove and the tops are located on the bottom separately from each other. Next, two connection portions of the resistors are respectively formed on the tops of the two bodies of the main body. The resistivity of the connection is lower than the resistivity of the body.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

102‧‧‧Substrate

104‧‧‧resistance

106‧‧‧ Subject

108‧‧‧ bottom

110, 112‧‧‧ top

114, 116‧‧‧ Connections

118‧‧‧ dielectric layer

120, 122‧‧‧Contacts

202‧‧‧Substrate

204‧‧‧Oxide layer

206‧‧‧Light resistance

208‧‧‧ dielectric layer

210‧‧‧ body material layer

212‧‧‧Protective layer

214‧‧‧ Subject

216‧‧‧ bottom

218, 220‧‧‧ top

222‧‧‧Light resistance

224‧‧‧ Coverage

226‧‧‧ Coverage

228‧‧‧First dielectric material layer

230‧‧‧metal layer

232‧‧‧Connection material layer

234, 236‧‧‧ Connections

238‧‧‧Second dielectric material layer

240‧‧‧Contacts

242‧‧‧Barrier layer

244‧‧‧metal layer

302‧‧‧resistance

304, 306‧‧‧ Connections

308‧‧‧Contacts

402‧‧‧resistance

404, 406‧‧‧ Connections

408‧‧‧Contacts

L1, L2, L3‧‧‧ length

T‧‧‧ trench

W‧‧‧Width

Figure 1 is a schematic illustration of a memory structure in accordance with an embodiment of the present invention.

2A to 11C are schematic views showing respective steps of a method of fabricating a memory structure in accordance with an embodiment of the present invention.

12A-12B are schematic diagrams showing the resistance configuration of a memory structure in accordance with an embodiment of the present invention.

13A-13B are schematic diagrams showing the resistance configuration of a memory structure in accordance with another embodiment of the present invention.

Please refer to FIG. 1 , which illustrates a memory structure in accordance with an embodiment of the present invention. The memory structure includes a substrate 102 and a resistor 104. The substrate 102 may be a germanium substrate. The substrate 102 has a trench T.

The resistor 104 is disposed in the trench T. Here, the resistor 104 may partially protrude beyond the trench T, but still belongs to the feature of "disposed in the trench T". Included range. The resistor 104 includes a body 106 and two connecting portions 114, 116. The body 106 includes a bottom portion 108 and two top portions 110, 112. The bottom 108 is located in the trench T. The tops 110, 112 are located on the bottom 108 separately from one another. In one embodiment, such a configuration is such that the body 106 has a substantially U-shaped cross-section. The connections 114, 116 are located on the tops 110, 112, respectively. The resistivity of the connecting portions 114, 116 is smaller than the resistivity of the body 106.

In one embodiment, the body 106 is formed of a doped polysilicon having a doping amount of 10 ¹⁶ cm ^-3 to 10 ²⁰ cm ^-3 (which may be p-type or n-type), and the connecting portions 114, 116 are deuterated by metal. The substance is formed, for example, CoSi, NiSi, TiSi, or the like. At this time, the resistance value of the metal telluride is negligible with respect to the resistance value of the doped polysilicon. Therefore, the effective length of the resistor 104 is substantially the length L1 between the connecting portion 114 to the bottom portion 108, the length L2 between the top portions 110, 112, and the length L3 plus the length between the bottom portion 108 and the connecting portion 116, and The effective width of the resistor 104 is substantially the width W of the trench. In this way, the resistance value of the resistor 104 can be changed by adjusting these dimensions.

In an embodiment, the memory structure may further include a dielectric layer 118 between the resistor 104 and the substrate 102. Dielectric layer 118 can have an oxide-nitride-oxide (ONO) structure. In an embodiment, the dielectric layer 118 memory structure may further include two contacts 120, 122 located on the connecting portions 114, 116, respectively.

2A to 11C are diagrams showing various steps of a method of fabricating a memory structure according to an embodiment of the present invention, wherein the maps indicated by "B" and "C" are respectively taken from the map indicated by "A". Sectional view of the 1' line and the 2-2' line.

Referring to FIGS. 2A-2B, a trench T is formed in a substrate 202. Specifically, the substrate 202 may include an array region and a peripheral region, and the trench T is formed in the peripheral region. The substrate 202 can be, for example, a germanium substrate. An oxide layer 204 may be formed on the substrate, and the trench T also penetrates the oxide layer 204. The trench T can be formed, for example, by etching using the photoresist 206.

Next, a body 214 of a resistor is formed (shown in Figures 5A-5B). The body 214 includes a bottom portion 216 and two top portions 218, 220. The bottom 216 is located in the trench T. The tops 218, 220 are located on the bottom 216 separately from one another.

Referring to FIGS. 3A-3B, a body material layer 210 is formed on the substrate 202 and in the trench T. In one embodiment, if the process of forming a resistor in the peripheral region is performed in synchronization with the process of forming the memory array in the array region, a conformal formation on the substrate 202 and the trench T may be formed before the formation of the host material layer 210. Dielectric layer 208. Dielectric layer 208 may have an oxide-nitride-oxide (ONO) structure formed by deposition. The body material layer 210 may be formed of doped germanium. For example, the host material layer 210 may be formed of a p-type or n-type doped polysilicon having a doping amount of 10 ¹⁶ cm ^-3 to 10 ²⁰ cm ^-3 . The body material layer 210 can be formed by deposition.

When the dielectric layer 208 and the host material layer 210 are deposited, it is possible that the two regions in the peripheral region, which are not intended to form a resistance, are also deposited, and thus a removal step is required. Alternatively, other processing may be performed in areas of the array area and the peripheral area that are not intended to form a resistor. At this time, please refer to FIGS. 4A-4B to avoid structural damage with a protective layer 212 over the area where the resistance is to be formed. The protective layer 212 can be, for example, a photoresist.

Referring to Figures 5A-5B, the body material layer 210 is patterned to form The bottom 216 and the top 218, 220 of the body 214. This patterning step can be performed, for example, by etching using a photoresist 222. In an embodiment, the body material layer 210 located in the trench T will not be removed even if it is not used to form the bottom 216 of the resistor. In this embodiment, the bottom portion 216 and the top portions 218, 220 are formed in an integral manner, and no other layers are sandwiched between the bottom portion 216 and the top portions 218, 220.

Next, two connection portions 234 and 236 of resistance are formed on the top portions 218 and 220 of the main body 214 (shown in FIGS. 10A to 10B). The resistivity of the connecting portions 234, 236 is lower than the resistivity of the body 214.

Referring to FIGS. 6A-6B, two cover layers 224, 226 are conformally formed on the top surfaces 218, 220 of the substrate 202 and the body 214. The cover layer 224 can be an oxide layer and the cover layer 226 can be a nitride (eg, SiN _x ) layer.

Referring to Figures 7A-7B, a first dielectric material layer 228 is formed in the recesses of the cover layers 224, 226. The first dielectric material layer 228 can be an oxide layer. The first dielectric material layer 228 can be performed, for example, by deposition and chemical mechanical polishing (CMP). Chemical mechanical polishing can be stopped upon contact with the cover layer 226.

Referring to Figures 8A-8B, a portion of the cover layers 224, 226 are removed to expose the top portions 218, 220. This removal step can be performed, for example, by etching.

Next, please refer to Figures 9A-9B to deposit a metal layer 230 on the exposed top portions 218,220. The metal layer 230 may be, for example, a cobalt (Co) layer, a nickel (Ni) layer, or a titanium (Ti) layer, or the like.

Referring to Figures 10A-10B, the exposed top portions 218, 220 are reacted with the metal layer 230 to form a layer of bonding material 232 on the top portions 218, 220. The exposed top portions 218, 220 and the metal layer 230 can be reacted, for example, by heating or the like. The connecting material layer 232 is formed of a metal telluride layer such as a CoSi layer, a NiSi layer or a TiSi layer, or the like. The connecting material layer 232 constitutes two connecting portions 234, 236 of electrical resistance. Thereafter, the metal layer 230 is removed.

Referring to FIGS. 11A-11C, a second dielectric material layer 238 may be formed on the bonding material layer 232, and a contact 240 may be formed through the two dielectric material layers 238 and connected to the connecting portions 234, 236 of the body 214, respectively. A barrier layer 242 may be formed under the second dielectric material layer 238, and the contact 240 also penetrates the barrier layer 242. A second dielectric material layer 238 may be a nitride (e.g., SiN _x) layer, a barrier layer 242 may be an oxide layer. A metal layer 244 may be further formed on the second dielectric material layer 238 for connecting the contacts 240.

The memory structure fabrication method according to an embodiment of the present invention is as described above, wherein the process of the resistor can be integrated with the process of the array region. In this way, manufacturing time can be shortened.

In addition to the one shown in Figure 11A, the memory structure can have other types of resistor configurations. Referring to Figures 12A-12B, the memory structure includes a complex resistor 302. The resistors 302 are arranged side by side. Either one of the resistors 302 and its adjacent ones are only connected by one of the connecting portions 304, 306, respectively, to form a series circuit. Specifically, the connecting portions 304 of the resistors 302 are connected in series, and the connecting portions 306 of the resistors 302 are connected in series, and the connected connecting portions 304 are alternately arranged with the connected connecting portions 306. The two contacts 308 are respectively disposed at the two ends of the series circuit. Referring to Figures 13A-13B, the memory structure includes a complex resistor 402. The resistors 402 are arranged side by side. Any of the resistors 402 are connected to their neighbors by connecting portions 404, 406 to form a parallel circuit. Specifically, in this embodiment, all of the resistors 402 are connected. The portions 404 are all connected, and the connections 406 of all the resistors 402 are connected. The two contacts 408 are respectively disposed at the two ends of the parallel circuit.

According to the resistor of the present invention, the resistance value can be adjusted by adjusting the size and interval of each part. Moreover, since the main body of the resistor is made of doped polysilicon, it has the advantages of being stable, less affected by temperature, and less likely to be depleted. The resistor according to the invention is particularly suitable for use in three-dimensional memory devices, such as three-dimensional vertical gate NAND memory devices.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (10)

A memory structure includes: a substrate including an array region and a peripheral region, and having a trench formed in the peripheral region; and a resistor disposed in the trench, the resistor comprising: a body, including a a bottom portion and a second top portion, the bottom portion being located in the trench, the two top portions being located on the bottom portion separately from each other; and two connecting portions respectively located on the top portions, the two connecting portions having a resistivity smaller than a resistivity of the main body. The memory structure according to claim 1, wherein the body is formed of doped polysilicon having a doping amount of 10 ¹⁶ cm ^-3 to 10 ²⁰ cm ^-3 , and the two connections are made of metal telluride. Formed. The memory structure of claim 1, further comprising: a dielectric layer between the resistor and the substrate. The memory structure of claim 1, further comprising: two contacts, respectively located on the two connections. The memory structure of claim 1, comprising a plurality of resistors, the resistors being arranged side by side, and any one of the resistors and the adjacent ones of the resistors are only one of the two connections Connected to form a series circuit. The memory structure of claim 1, comprising a plurality of resistors, the resistors being arranged side by side, and any one of the resistors being connected to the adjacent one of the two connections to form a parallel circuit. A method of fabricating a memory structure, comprising: forming a peripheral region of a substrate including an array region and a peripheral region a body forming a resistor, the body comprising a bottom portion and a top portion, the bottom portion being located in the groove, the top portions being spaced apart from each other on the bottom portion; and the top portion of the body being separately formed a two-connecting portion of the resistor, the resistivity of the two connecting portions being lower than a resistivity of the body. The method of fabricating a memory structure according to claim 7, wherein the step of forming the body of the resistor comprises: forming a body material layer on the substrate and in the trench; and patterning the body material layer . The method for fabricating a memory structure according to claim 8, further comprising: forming a dielectric layer on the substrate and in the trench before forming the host material layer. The method for fabricating a memory structure according to claim 7, wherein the forming the two connecting portions comprises: conformally forming two covering layers on the two tops of the substrate and the body; Forming a first layer of dielectric material; removing a portion of the two cap layers to expose the top portions; depositing a metal layer on the exposed tops; and exposing the two tops to the The metal layer reacts to form a layer of bonding material on the top of the two, the layer of bonding material forming the two connections of the resistor.