TWI616981B - Substrate structure - Google Patents
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- TWI616981B TWI616981B TW106109262A TW106109262A TWI616981B TW I616981 B TWI616981 B TW I616981B TW 106109262 A TW106109262 A TW 106109262A TW 106109262 A TW106109262 A TW 106109262A TW I616981 B TWI616981 B TW I616981B
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- 239000000758 substrate Substances 0.000 title claims abstract description 70
- 239000003989 dielectric material Substances 0.000 claims abstract description 82
- 150000001875 compounds Chemical class 0.000 claims description 12
- 229920005989 resin Polymers 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 6
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920001568 phenolic resin Polymers 0.000 claims description 3
- 239000005011 phenolic resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 2
- 229910052707 ruthenium Inorganic materials 0.000 claims description 2
- 125000003396 thiol group Chemical group [H]S* 0.000 claims 1
- 239000010410 layer Substances 0.000 description 159
- 238000004519 manufacturing process Methods 0.000 description 23
- 238000000034 method Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 230000017525 heat dissipation Effects 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 238000012536 packaging technology Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000001747 exhibiting effect Effects 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 239000002918 waste heat Substances 0.000 description 1
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Abstract
一種基板結構包含一第一介電材料層、一第二介電材料層、一第一導線層、一第二導線層、一第一導電柱層以及一第二導電柱層。第一導線層部份地嵌設於第一介電材料層內。第一導電柱層嵌設於第二介電材料層內並設置於第一導線層以及第二導線層之間,其具有一第一導電柱。第二導電柱層設置於第二導線層上,其具有一第二導電柱。第一導線層以及第二導線層藉由第一導電柱層電性連接。第二導電柱係┴型導電柱、┬型導電柱或+型導電柱。 A substrate structure comprises a first dielectric material layer, a second dielectric material layer, a first wire layer, a second wire layer, a first conductive pillar layer and a second conductive pillar layer. The first wire layer is partially embedded in the first dielectric material layer. The first conductive pillar layer is embedded in the second dielectric material layer and disposed between the first wire layer and the second wire layer, and has a first conductive pillar. The second conductive pillar layer is disposed on the second wire layer and has a second conductive pillar. The first wire layer and the second wire layer are electrically connected by the first conductive pillar layer. The second conductive pillar is a 导电-type conductive pillar, a ┬-type conductive pillar or a +-type conductive pillar.
Description
本發明係關於一種基板結構,更詳細地說,本發明係關於一種半導體基板結構。 The present invention relates to a substrate structure, and more particularly to a semiconductor substrate structure.
在新一代的電子產品中,使用者不但追求更輕薄短小,更要求其具有多功能以及高性能。因此,電子產品製造商必須在積體電路(integrated circuit;IC)之有限的區域中,容納更多電子元件以達成高密度與微型化之要求。據此,電子產品製造商開發了新型封裝技術,例如覆晶(Flip-Chip)、晶片尺寸封裝(Chip Scale Package;CSP)、晶圓級封裝以及立體封裝(3D Package)技術等。 In a new generation of electronic products, users are not only pursuing thinner and lighter, but also demanding versatility and high performance. Therefore, electronics manufacturers must accommodate more electronic components in a limited area of an integrated circuit (IC) to achieve high density and miniaturization requirements. Accordingly, electronics manufacturers have developed new packaging technologies such as Flip-Chip, Chip Scale Package (CSP), wafer-level packaging, and 3D Package technology.
然而,在數位、類比、記憶體及無線射頻等領域的應用中,不同功能的電子電路會產生不同的需求及結果,因此,在單一晶粒上整合不同功能的產品已然不是最佳化的產品解決方案。隨著系統單晶片(System on Chip;SOC)、系統級封裝(System-in-Package;SiP)、PiP(Package-in-Package)封裝、堆疊式封裝(Package-on-Package;PoP)以及晶片尺寸構裝(Chip Scale Package;CSP)技術的快速發展,近年來最有效能的系統晶片應朝向單一封裝結構中,藉由充分利用多維空間的架構,整合使用異質性技術及不同電壓操作環境的各種不同功能的晶粒。因此,目前的系統晶片的封裝已朝向立體封裝技術的方向前進,立體封裝技術可將晶粒、封裝與被動元件整合成一封裝體,而可成為系統封裝的一種解決方式。 However, in applications such as digital, analog, memory, and radio frequency, electronic circuits with different functions have different requirements and results. Therefore, products that integrate different functions on a single die are not optimized products. solution. System-on-a-chip (SOC), System-in-Package (SiP), PiP (Package-in-Package), Package-on-Package (PoP), and With the rapid development of Chip Scale Package (CSP) technology, the most efficient system chips in recent years should be oriented in a single package structure, by leveraging the multi-dimensional space architecture, integrating heterogeneity technology and different voltage operating environments. Grains of various functions. Therefore, the current system wafer package has been oriented toward the three-dimensional packaging technology, and the three-dimensional packaging technology can integrate the die, the package and the passive component into a package, which can be a solution for the system package.
雖然傳統之多層堆疊式封裝架構可藉由使用剛性導體作為層架支撐的方式控制層間高度,但這種方式在製程上的準位控制相當困難。相對地,若使用銲球作為層架支撐,雖然能輕 易地解決準位控制的問題,但卻有著高度限制的問題存在,尤其是將容易使得上層基板壓制於下層元件上。此外,傳統的立體架構中,越多層的架構代表運作的系統模組越多,而每個元件運作時所產生的廢熱將會產生加乘的效應,進而使得傳統之多層堆疊式封裝架構的散熱效果極差。 Although the conventional multi-layer stacked package architecture can control the interlayer height by using a rigid conductor as a shelf support, this method of controlling the level on the process is quite difficult. In contrast, if a solder ball is used as a shelf support, although it can be light Easily solve the problem of level control, but there are problems with high restrictions, especially it will be easy to press the upper substrate onto the lower layer. In addition, in the traditional three-dimensional architecture, the more multi-layer architecture represents the more system modules that operate, and the waste heat generated by each component operation will have a multiplier effect, which in turn makes the traditional multi-layer stacked package architecture heat dissipation. The effect is very poor.
前段所述之種種因素均會影響立體封裝技術之可靠度,並大大地降低封裝製程的良率,導致成本大幅提高。因此,如何提供一種具有剛性與散熱性且滿足高良率的基板結構,乃是業界亟待解決的問題。 All the factors mentioned in the previous paragraph will affect the reliability of the three-dimensional packaging technology, and greatly reduce the yield of the packaging process, resulting in a substantial increase in cost. Therefore, how to provide a substrate structure having rigidity and heat dissipation and satisfying a high yield is an urgent problem to be solved in the industry.
本發明之一目的在於提供一種基板結構。該基板結構包含一第一介電材料層、一第二介電材料層、一第一導線層、一第二導線層、一第一導電柱層以及一第二導電柱層。該第一導線層部份地嵌設於該第一介電材料層內。該第一導電柱層嵌設於該第二介電材料層內並設置於該第一導線層以及該第二導線層之間,其具有至少一第一導電柱。該第二導電柱層設置於該第二導線層上,其具有至少一第二導電柱。該第一導線層以及該第二導線層係藉由該至少一第一導電柱電性連接。該至少一第二導電柱係┴型導電柱、┬型導電柱或+型導電柱。 It is an object of the present invention to provide a substrate structure. The substrate structure comprises a first dielectric material layer, a second dielectric material layer, a first wire layer, a second wire layer, a first conductive pillar layer and a second conductive pillar layer. The first wire layer is partially embedded in the first dielectric material layer. The first conductive pillar layer is embedded in the second dielectric material layer and disposed between the first wire layer and the second wire layer, and has at least one first conductive pillar. The second conductive pillar layer is disposed on the second wire layer and has at least one second conductive pillar. The first wire layer and the second wire layer are electrically connected by the at least one first conductive pillar. The at least one second conductive pillar is a 导电-type conductive pillar, a ┬-type conductive pillar or a +-type conductive pillar.
綜上所述,本發明之基板結構係利用較簡易的製作流程形成不同型態之導電柱,並以這些導電柱作為層架支撐,進而取代傳統之多層堆疊式封裝架構。據此,本發明之基板結構可縮小多層堆疊式封裝架構的厚度,同時增加剛性與散熱性,並兼具高良率。如此一來,將可縮短基板結構之加工時間並大幅降低製作成本。 In summary, the substrate structure of the present invention utilizes a relatively simple fabrication process to form different types of conductive pillars, and these conductive pillars are used as a shelf support, thereby replacing the conventional multilayer stacked package architecture. Accordingly, the substrate structure of the present invention can reduce the thickness of the multi-layer stacked package structure while increasing rigidity and heat dissipation, and has high yield. As a result, the processing time of the substrate structure can be shortened and the manufacturing cost can be greatly reduced.
在參閱圖式及隨後描述之實施方式後,所屬技術領域具有通常知識者便可瞭解本發明之其它目的、優點以及本發明之技術手段及實施態樣。 Other objects, advantages, and technical means and embodiments of the present invention will become apparent to those skilled in the <RTIgt;
1、2、3、4‧‧‧基板結構 1, 2, 3, 4‧‧‧ substrate structure
11、21、31、41‧‧‧介電材料層 11, 21, 31, 41‧‧‧ dielectric material layer
11a、21a、31a‧‧‧第一介電材料層 11a, 21a, 31a‧‧‧ first dielectric material layer
11b、21b、31b‧‧‧第二介電材料層 11b, 21b, 31b‧‧‧ second dielectric material layer
21c、31c、31c'‧‧‧第三介電材料層 21c, 31c, 31c'‧‧‧ third dielectric material layer
13‧‧‧第一導線層 13‧‧‧First wire layer
15‧‧‧第一導電柱層 15‧‧‧First conductive column
17‧‧‧第二導線層 17‧‧‧Second wire layer
19A、19B、23A、23B‧‧‧導電柱 19A, 19B, 23A, 23B‧‧‧ conductive columns
61‧‧‧承載板 61‧‧‧Loading board
第1圖係為本發明之第一實施例之基板結構之示意圖。 Fig. 1 is a schematic view showing the structure of a substrate according to a first embodiment of the present invention.
第2圖係為本發明之第二實施例之基板結構之示意圖。 Fig. 2 is a schematic view showing the structure of a substrate of a second embodiment of the present invention.
第3圖係為本發明之第三實施例之基板結構之示意圖。 Fig. 3 is a schematic view showing the structure of a substrate of a third embodiment of the present invention.
第4圖係為本發明之第四實施例之基板結構之示意圖。 Fig. 4 is a schematic view showing the structure of a substrate of a fourth embodiment of the present invention.
第5圖係為本發明之第五實施例之基板結構之製作方法之流程圖。 Fig. 5 is a flow chart showing a method of fabricating a substrate structure according to a fifth embodiment of the present invention.
第6A圖至第6G圖係為本發明之第五實施例之基板結構之製作示意圖。 6A to 6G are schematic views showing the fabrication of the substrate structure of the fifth embodiment of the present invention.
第7圖係為本發明之第六實施例之基板結構之製作方法之流程圖。 Fig. 7 is a flow chart showing a method of fabricating a substrate structure according to a sixth embodiment of the present invention.
第8A圖至第8B圖係為本發明之第六實施例之基板結構之製作示意圖。 8A to 8B are views showing the fabrication of the substrate structure of the sixth embodiment of the present invention.
第9圖係為本發明之第七實施例之基板結構之製作方法之流程圖。 Figure 9 is a flow chart showing a method of fabricating a substrate structure according to a seventh embodiment of the present invention.
第10A圖至第10B圖係為本發明之第七實施例之基板結構之製作示意圖。 10A to 10B are views showing the fabrication of the substrate structure of the seventh embodiment of the present invention.
第11圖係為本發明之第七實施例之基板結構之另一製作示意圖。 Figure 11 is a schematic view showing another fabrication of the substrate structure of the seventh embodiment of the present invention.
第12圖係為形成介電材料層之流程圖。 Figure 12 is a flow chart for forming a layer of dielectric material.
以下將透過實施例來解釋本發明內容,本發明的實施例並非用以限制本發明須在如實施例所述之任何特定的環境、應用或特殊方式方能實施。因此,關於實施例之說明僅為闡釋本發明之目的,而非用以限制本發明。須說明者,以下實施例及圖式中,與本發明非直接相關之元件已省略而未繪示;且圖式中各元件間之尺寸關係僅為求容易瞭解,非用以限制實際比例。 The present invention is not limited by the embodiment, and the embodiment of the present invention is not intended to limit the invention to any specific environment, application or special mode as described in the embodiments. Therefore, the description of the embodiments is merely illustrative of the invention and is not intended to limit the invention. It should be noted that, in the following embodiments and drawings, components that are not directly related to the present invention have been omitted and are not shown; and the dimensional relationships between the components in the drawings are merely for ease of understanding and are not intended to limit the actual ratio.
本發明之第一實施例如第1圖所示,係為一基板結構1之示意圖。基板結構1包含一介電材料層11、一第一導線層13、一第二導線層17、一第一導電柱層15以及一第二導電柱層。介電材料層11具有一第一介電材料層11a及一第二介電材料層 11b。第一導電柱層15具有複數個導電柱;類似地,第二導電柱層具有複數個導電柱19A、19B。第一導線層13嵌設於第一介電材料層11a與第二介電材料層11b內。 A first embodiment of the present invention, as shown in Fig. 1, is a schematic view of a substrate structure 1. The substrate structure 1 comprises a dielectric material layer 11, a first wire layer 13, a second wire layer 17, a first conductive pillar layer 15, and a second conductive pillar layer. The dielectric material layer 11 has a first dielectric material layer 11a and a second dielectric material layer 11b. The first conductive pillar layer 15 has a plurality of conductive pillars; similarly, the second conductive pillar layer has a plurality of conductive pillars 19A, 19B. The first wire layer 13 is embedded in the first dielectric material layer 11a and the second dielectric material layer 11b.
介電材料層11係為一鑄模化合物(Molding Compound)層,其具有酚醛基樹脂(Novolac-based Resin)、環氧基樹脂(Epoxy-based Resin)、矽基樹脂(Silicone-based Resin)或其它適當之鑄模化合物,但不以此為限。此外,在本實施例中,第一導電柱層15具有五個導電柱;第二導電柱層具有四個導電柱19A以及五個導電柱19B。然而,在其它實施例中,依據基板結構1之不同用途與類型,第一導電柱層15以及第二導電柱層可分別具有任意數目之導電柱,並不以本實施例所述之導電柱的數量為限。 The dielectric material layer 11 is a Molding Compound layer having a Novolac-based Resin, an Epoxy-based Resin, a Silicone-based Resin or the like. Suitable mold compounds, but not limited to this. Further, in the present embodiment, the first conductive pillar layer 15 has five conductive pillars; the second conductive pillar layer has four conductive pillars 19A and five conductive pillars 19B. However, in other embodiments, the first conductive pillar layer 15 and the second conductive pillar layer may have any number of conductive pillars respectively according to different uses and types of the substrate structure 1, and the conductive pillars not described in this embodiment are not used. The number is limited.
第一導電柱層15嵌設於第二介電材料層11b內,並設置於第一導線層13以及第二導線層17之間;同時,第一導電柱層15電性連接第一導線層13以及第二導線層17。第二導電柱層之導電柱19A、19B設置於第二導線層17上;同時,第二導電柱層之導電柱19A、19B電性連接第二導線層17。在本實施例中,如圖所示由一縱向截面觀之,第二導電柱層之導電柱19A係┴型導電柱,第二導電柱層之導電柱19B係口型導電柱,且┴型導電柱以及口型導電柱,例如係以電鍍銅製成之單一結構體。導電柱19A在視覺上係為一個二階段式(或階梯狀)的導電柱,以形成┴型導電柱,而導電柱19B在視覺上係為一塊狀的導電柱,以形成口型導電柱。 The first conductive pillar layer 15 is embedded in the second dielectric material layer 11b and disposed between the first conductive layer 13 and the second conductive layer 17; meanwhile, the first conductive pillar layer 15 is electrically connected to the first conductive layer 13 and a second wire layer 17. The conductive pillars 19A, 19B of the second conductive pillar layer are disposed on the second wire layer 17; meanwhile, the conductive pillars 19A, 19B of the second conductive pillar layer are electrically connected to the second wire layer 17. In the present embodiment, as shown in the longitudinal section, the conductive pillar 19A of the second conductive pillar layer is a 导电-type conductive pillar, and the conductive pillar 19B of the second conductive pillar layer is a gate-type conductive pillar, and the ┴ type The conductive pillars and the oral conductive pillars are, for example, a single structure made of electroplated copper. The conductive pillar 19A is visually formed as a two-stage (or stepped) conductive pillar to form a ┴-type conductive pillar, and the conductive pillar 19B is visually formed as a block-shaped conductive pillar to form a slab-shaped conductive pillar. .
本發明之第二實施例如第2圖所示,係為一基板結構2之示意圖。基板結構2之一結構類似於本發明之第一實施例所述之基板結構1之結構,其差異在於基板結構2中,介電材料層21與基板結構1之介電材料層11不同;且第二導電柱層具有複數個導電柱23A、23B。詳細地說,介電材料層21具有一第一介電材料層21a、一第二介電材料層21b及一第三介電材料層21c。第二導線層17嵌設於介電材料層21內,第二導電柱層之導 電柱23A、23B部份地嵌設於介電材料層21內。在本實施例中,如圖所示由一縱向截面觀之,第二導電柱層之導電柱23A係+型導電柱,第二導電柱層之導電柱23B係┬型導電柱,且+型導電柱以及┬型導電柱,例如係以電鍍銅製成之單一結構體。 A second embodiment of the present invention, as shown in FIG. 2, is a schematic view of a substrate structure 2. One of the structures of the substrate structure 2 is similar to the structure of the substrate structure 1 of the first embodiment of the present invention, except that the dielectric material layer 21 is different from the dielectric material layer 11 of the substrate structure 1 in the substrate structure 2; The second conductive pillar layer has a plurality of conductive pillars 23A, 23B. In detail, the dielectric material layer 21 has a first dielectric material layer 21a, a second dielectric material layer 21b, and a third dielectric material layer 21c. The second conductive layer 17 is embedded in the dielectric material layer 21, and the second conductive pillar layer is guided. The posts 23A, 23B are partially embedded in the dielectric material layer 21. In this embodiment, as shown in the longitudinal section, the conductive pillar 23A of the second conductive pillar layer is a +-type conductive pillar, and the conductive pillar 23B of the second conductive pillar layer is a conductive pillar of the type, and the type is + The conductive pillars and the 导电-type conductive pillars are, for example, a single structure made of electroplated copper.
本發明之第三實施例如第3圖所示,係為一基板結構3之示意圖。基板結構3之一結構類似於本發明之第一實施例所述之基板結構1之結構,其差異在於基板結構3中,介電材料層31與基板結構1之介電材料層11不同。詳細地說,介電材料層31具有一第一介電材料層31a、一第二介電材料層31b及一第三介電材料層31c。第二導線層17及第二導電柱層之導電柱19A嵌設於第三介電材料層31c內,且第二導電柱層之導電柱19B部份地嵌設於第三介電材料層31c內。類似於第一實施例之基板結構1,在本實施例中,如圖所示由一縱向截面觀之,第二導電柱層之導電柱19A係┴型導電柱,第二導電柱層之導電柱19B係口型導電柱,且┴型導電柱以及口型導電柱,例如係以電鍍銅製成之單一結構體。 A third embodiment of the present invention, as shown in FIG. 3, is a schematic view of a substrate structure 3. One of the structures of the substrate structure 3 is similar to the structure of the substrate structure 1 described in the first embodiment of the present invention, with the difference that in the substrate structure 3, the dielectric material layer 31 is different from the dielectric material layer 11 of the substrate structure 1. In detail, the dielectric material layer 31 has a first dielectric material layer 31a, a second dielectric material layer 31b, and a third dielectric material layer 31c. The conductive pillars 19A of the second conductive layer and the second conductive pillars are embedded in the third dielectric material layer 31c, and the conductive pillars 19B of the second conductive pillars are partially embedded in the third dielectric material layer 31c. Inside. Similar to the substrate structure 1 of the first embodiment, in the present embodiment, as shown in the longitudinal section, the conductive pillar 19A of the second conductive pillar layer is a conductive pillar and the second conductive pillar is electrically conductive. The column 19B is a port-type conductive column, and the 导电-type conductive column and the port-shaped conductive column are, for example, a single structure made of electroplated copper.
本發明之第四實施例如第4圖所示,係為一基板結構4之示意圖。基板結構4之一結構類似於本發明之第一實施例所述之基板結構1之結構,其差異在於基板結構4中,介電材料層41與基板結構1之介電材料層11不同。詳細地說,介電材料層41具有一第一介電材料層31a、一第二介電材料層31b及一第三介電材料層31c'。第二導線層17嵌設於第三介電材料層31c'內,第二導電柱層之導電柱19A、19B分別部份地嵌設於第三介電材料層31c'內。類似於第一實施例之基板結構1,在本實施例中,如圖所示由一縱向截面觀之,第二導電柱層之導電柱19A係┴型導電柱;第二導電柱層之導電柱19B係口型導電柱,且┴型導電柱以及口型導電柱,例如係以電鍍銅製成之單一結構體。 A fourth embodiment of the present invention, as shown in FIG. 4, is a schematic view of a substrate structure 4. One of the structures of the substrate structure 4 is similar to the structure of the substrate structure 1 described in the first embodiment of the present invention, with the difference that in the substrate structure 4, the dielectric material layer 41 is different from the dielectric material layer 11 of the substrate structure 1. In detail, the dielectric material layer 41 has a first dielectric material layer 31a, a second dielectric material layer 31b, and a third dielectric material layer 31c'. The second conductive layer 17 is embedded in the third dielectric material layer 31c'. The conductive pillars 19A and 19B of the second conductive pillar layer are partially embedded in the third dielectric material layer 31c'. Similar to the substrate structure 1 of the first embodiment, in the present embodiment, as shown in the longitudinal section, the conductive pillar 19A of the second conductive pillar layer is a conductive pillar; the conductive layer of the second conductive pillar The column 19B is a port-type conductive column, and the 导电-type conductive column and the port-shaped conductive column are, for example, a single structure made of electroplated copper.
本發明之第五實施例如第5圖所示,其係為一種基板結構之製作方法之流程圖。本實施例所述之製作方法可用於製作一基板結構,例如:第一實施例所述之基板結構1。以下將透過 第5圖以及第6A圖至第6G圖進一步說明本實施例之基板結構之製作方法的步驟。 A fifth embodiment of the present invention is shown in Fig. 5, which is a flow chart of a method of fabricating a substrate structure. The manufacturing method described in this embodiment can be used to fabricate a substrate structure, such as the substrate structure 1 described in the first embodiment. The following will be through Fig. 5 and Figs. 6A to 6G further illustrate the steps of the method of fabricating the substrate structure of the present embodiment.
首先,於步驟501中,提供如第6A圖繪示之一承載板61。其中,承載板61係由鋁、銅、不銹鋼或其組合製成之一金屬板。 First, in step 501, a carrier board 61 is provided as shown in FIG. 6A. The carrier plate 61 is a metal plate made of aluminum, copper, stainless steel or a combination thereof.
接著,於步驟503中,形成如第6B圖繪示之一第一介電材料層11a於承載板61之一表面。其中,於步驟503中,係應用一真空壓合製程將介電材料層壓合於承載板61之表面,其具有以下之優點:(1)僅需真空壓合單層之介電材料層以縮短製作時間;以及(2)適合進行大面積的封裝製程以降低成本與生產時間。 Next, in step 503, a first dielectric material layer 11a is formed on one surface of the carrier plate 61 as shown in FIG. 6B. Wherein, in step 503, a dielectric bonding material is laminated on the surface of the carrier plate 61 by using a vacuum pressing process, which has the following advantages: (1) only a single layer of dielectric material layer is required to be vacuum-pressed. Reduce production time; and (2) Suitable for large-area packaging processes to reduce cost and production time.
於步驟505中,如第6C圖所示,形成一第一導線層13於前述之第一介電材料層11a上。接著,於步驟507中,如第6D圖所示,形成一第一導電柱層15於第一導線層13上。於步驟509中,如第6E圖所示,形成一第二介電材料層11b,使其包覆第一導線層13以及第一導電柱層15,並露出第一導電柱層15之一端。 In step 505, as shown in FIG. 6C, a first wiring layer 13 is formed on the first dielectric material layer 11a. Next, in step 507, a first conductive pillar layer 15 is formed on the first wiring layer 13 as shown in FIG. 6D. In step 509, as shown in FIG. 6E, a second dielectric material layer 11b is formed to cover the first wiring layer 13 and the first conductive pillar layer 15, and expose one end of the first conductive pillar layer 15.
於步驟511中,如第6F圖所示,形成一第二導線層17於露出之第一導電柱層15之一端上與第二介電材料層11b上。接著,於步驟513中,如第6G圖所示,形成一第二導電柱層於第二導線層17上。其中,第二導電柱層具有複數個導電柱19A、19B;且第二導電柱層之導電柱19A係┴型導電柱;第二導電柱層之導電柱19B係口型導電柱。最後,於步驟515中,移除承載板61,以形成如第1圖繪示之基板結構1。 In step 511, as shown in FIG. 6F, a second wiring layer 17 is formed on one end of the exposed first conductive pillar layer 15 and on the second dielectric material layer 11b. Next, in step 513, as shown in FIG. 6G, a second conductive pillar layer is formed on the second wiring layer 17. The second conductive pillar layer has a plurality of conductive pillars 19A, 19B; and the conductive pillar 19A of the second conductive pillar layer is a ┴-type conductive pillar; and the conductive pillar 19B of the second conductive pillar layer is a gate-type conductive pillar. Finally, in step 515, the carrier plate 61 is removed to form the substrate structure 1 as shown in FIG.
本發明之第六實施例如第7圖所示,其係為一種基板結構之製作方法之流程圖。本實施例所述之製作方法可用於製作一基板結構,例如:第二實施例所述之基板結構2。其中,第7圖所示之第六實施例之步驟701至步驟711與本發明之第五實施例之步驟501至步驟511相同,故在此不再贅述。以下將透過第7圖以及第8A圖至第8B圖進一步說明本實施例之基板結構之製作 方法的後續步驟。需說明的是,本實施例之第一介電材料層21a以及第二介電材料層21b係與前述實施例之第一介電材料層11a以及第二介電材料層11b為相同。 A sixth embodiment of the present invention is shown in Fig. 7, which is a flow chart of a method of fabricating a substrate structure. The manufacturing method described in this embodiment can be used to fabricate a substrate structure, such as the substrate structure 2 described in the second embodiment. The steps 701 to 711 of the sixth embodiment shown in FIG. 7 are the same as the steps 501 to 511 of the fifth embodiment of the present invention, and thus are not described herein again. The fabrication of the substrate structure of the present embodiment will be further described below through FIG. 7 and FIGS. 8A to 8B. The next steps of the method. It should be noted that the first dielectric material layer 21a and the second dielectric material layer 21b of the present embodiment are the same as the first dielectric material layer 11a and the second dielectric material layer 11b of the foregoing embodiment.
於步驟713中,如第8A圖所示,形成一第三介電材料層21c於第二導線層17上,並露出第二導線層17之一端。其中,第8A圖所示之第一介電材料層21a、第二介電材料層21b及第三介電材料層21c即構成基板結構2之介電材料層21。接著,於步驟715中,如第8B圖所示,形成一第二導電柱層於露出之第二導線層17之一端上。其中,第二導電柱層具有複數個導電柱23A、23B,且第二導電柱層之導電柱23A係+型導電柱,第二導電柱層之導電柱23B係┬型導電柱。最後,於步驟717中,移除承載板61,以形成如第2圖繪示之基板結構2。 In step 713, as shown in FIG. 8A, a third dielectric material layer 21c is formed on the second wiring layer 17, and one end of the second wiring layer 17 is exposed. The first dielectric material layer 21a, the second dielectric material layer 21b, and the third dielectric material layer 21c shown in FIG. 8A constitute the dielectric material layer 21 of the substrate structure 2. Next, in step 715, as shown in FIG. 8B, a second conductive pillar layer is formed on one end of the exposed second wiring layer 17. The second conductive pillar layer has a plurality of conductive pillars 23A, 23B, and the conductive pillar 23A of the second conductive pillar layer is a +-type conductive pillar, and the conductive pillar 23B of the second conductive pillar layer is a 导电-type conductive pillar. Finally, in step 717, the carrier plate 61 is removed to form the substrate structure 2 as shown in FIG.
本發明之第七實施例如第9圖所示,其係為一種基板結構之製作方法之流程圖。本實施例所述之製作方法可用於製作一基板結構,例如:第三實施例所述之基板結構3或第四實施例所述之基板結構4。其中,第9圖所示之第七實施例之步驟901至步驟913與本發明之第五實施例之步驟501至步驟513相同,故在此不再贅述。以下將透過第9圖、第10A圖至第10B圖以及第11圖進一步說明本實施例之基板結構之製作方法的後續步驟。需說明的是,本實施例之第一介電材料層31a以及第二介電材料層31b係與前述實施例之第一介電材料層21a以及第二介電材料層21b為相同。 A seventh embodiment of the present invention is shown in Fig. 9, which is a flow chart of a method of fabricating a substrate structure. The manufacturing method described in this embodiment can be used to fabricate a substrate structure, such as the substrate structure 3 described in the third embodiment or the substrate structure 4 described in the fourth embodiment. The steps 901 to 913 of the seventh embodiment shown in FIG. 9 are the same as the steps 501 to 513 of the fifth embodiment of the present invention, and thus are not described herein again. The subsequent steps of the method of fabricating the substrate structure of the present embodiment will be further described below through FIG. 9, FIG. 10A to FIG. 10B, and FIG. It should be noted that the first dielectric material layer 31a and the second dielectric material layer 31b of the present embodiment are the same as the first dielectric material layer 21a and the second dielectric material layer 21b of the foregoing embodiment.
於步驟915中,如第10A圖所示,形成一第三介電材料層31c,使其包覆第二導線層17以及第二導電柱層,並露出第二導電柱層之一端。其中,第二導電柱層具有複數個導電柱19A、19B;且第二導電柱層之導電柱19A係┴型導電柱;第二導電柱層之導電柱19B係口型導電柱。 In step 915, as shown in FIG. 10A, a third dielectric material layer 31c is formed to cover the second wiring layer 17 and the second conductive pillar layer, and expose one end of the second conductive pillar layer. The second conductive pillar layer has a plurality of conductive pillars 19A, 19B; and the conductive pillar 19A of the second conductive pillar layer is a ┴-type conductive pillar; and the conductive pillar 19B of the second conductive pillar layer is a gate-type conductive pillar.
於步驟917中,蝕刻第三介電材料層31c,形成如第10B圖所繪示之介電材料層31。其中,第二導電柱層之導電柱19A嵌設於第三介電材料層31c內,且第二導電柱層之導電柱19B部 份地嵌設於第三介電材料層31c內。需說明的是,於步驟917中,蝕刻第三介電材料層31c'亦可形成如第11圖所繪示之介電材料層41。其中,第二導電柱層之導電柱19A、19B部份地嵌設於第三介電材料層31c'內。 In step 917, the third dielectric material layer 31c is etched to form a dielectric material layer 31 as depicted in FIG. 10B. The conductive pillar 19A of the second conductive pillar layer is embedded in the third dielectric material layer 31c, and the conductive pillar 19B of the second conductive pillar layer is The portion is embedded in the third dielectric material layer 31c. It should be noted that, in step 917, the third dielectric material layer 31c' may be etched to form the dielectric material layer 41 as shown in FIG. The conductive pillars 19A, 19B of the second conductive pillar layer are partially embedded in the third dielectric material layer 31c'.
最後,於步驟919中,移除承載板61,以形成如第3圖繪示之基板結構3或如第4圖繪示之基板結構4。 Finally, in step 919, the carrier board 61 is removed to form the substrate structure 3 as shown in FIG. 3 or the substrate structure 4 as shown in FIG.
此外,於上述形成第一介電材料層11a、21a、31a、第二介電材料層11b、21b、31b或第三介電材料層21c、31c、31c'之步驟中,更包含如第12圖繪示之步驟。首先,於步驟1201中,提供一鑄模化合物。其中,鑄模化合物可為酚醛基樹脂、環氧基樹脂、矽基樹脂或其它適當之鑄模化合物。於步驟1203中,加熱鑄模化合物至一液體狀態。接著,於步驟1205中,注入呈現該液體狀態之鑄模化合物,使呈現該液體狀態之鑄模化合物包覆第一導線層13、第一導電柱層15、第二導線層17或第二導電柱層。最後,於步驟1207中,固化呈現液體狀態之鑄模化合物以形成一鑄模化合物層。 In addition, in the step of forming the first dielectric material layer 11a, 21a, 31a, the second dielectric material layer 11b, 21b, 31b or the third dielectric material layer 21c, 31c, 31c', the second step is further included as the 12th The figure shows the steps. First, in step 1201, a mold compound is provided. Among them, the mold compound may be a phenolic resin, an epoxy resin, a ruthenium-based resin or other suitable mold compound. In step 1203, the mold compound is heated to a liquid state. Next, in step 1205, a mold compound exhibiting the liquid state is injected, and the mold compound exhibiting the liquid state is coated with the first wire layer 13, the first conductive pillar layer 15, the second wire layer 17, or the second conductive pillar layer. . Finally, in step 1207, the mold compound in a liquid state is cured to form a mold compound layer.
綜上所述,本發明之基板結構係利用較簡易的製作流程形成不同型態之導電柱,並以這些導電柱作為層架支撐,進而取代傳統之多層堆疊式封裝架構。據此,本發明之基板結構及其製作方法可縮小多層堆疊式封裝架構的厚度,同時增加剛性與散熱性,並兼具高良率。如此一來,將可縮短基板結構之加工時間並大幅降低製作成本。 In summary, the substrate structure of the present invention utilizes a relatively simple fabrication process to form different types of conductive pillars, and these conductive pillars are used as a shelf support, thereby replacing the conventional multilayer stacked package architecture. Accordingly, the substrate structure of the present invention and the method of fabricating the same can reduce the thickness of the multi-layer stacked package structure while increasing rigidity and heat dissipation, and have high yield. As a result, the processing time of the substrate structure can be shortened and the manufacturing cost can be greatly reduced.
上述之實施例僅用來例舉本發明之實施態樣,以及闡釋本發明之技術特徵,並非用來限制本發明之保護範疇。任何熟悉此技術者可輕易完成之改變或均等性之安排均屬於本發明所主張之範圍,本發明之權利保護範圍應以申請專利範圍為準。 The embodiments described above are only intended to illustrate the embodiments of the present invention, and to explain the technical features of the present invention, and are not intended to limit the scope of protection of the present invention. Any changes or equivalents that can be easily made by those skilled in the art are within the scope of the invention. The scope of the invention should be determined by the scope of the claims.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200943508A (en) * | 2008-04-11 | 2009-10-16 | Phoenix Prec Technology Corp | Multilayer package substrate and method for fabricating the same |
| TW201039416A (en) * | 2009-04-20 | 2010-11-01 | Phoenix Prec Technology Corp | Package substrate structure and fabrication method thereof |
| TWM433634U (en) * | 2012-03-23 | 2012-07-11 | Unimicron Technology Corp | Semiconductor substrate |
| TWI474417B (en) * | 2014-06-16 | 2015-02-21 | 恆勁科技股份有限公司 | Packaging method |
-
2015
- 2015-07-15 TW TW106109262A patent/TWI616981B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200943508A (en) * | 2008-04-11 | 2009-10-16 | Phoenix Prec Technology Corp | Multilayer package substrate and method for fabricating the same |
| TW201039416A (en) * | 2009-04-20 | 2010-11-01 | Phoenix Prec Technology Corp | Package substrate structure and fabrication method thereof |
| TWM433634U (en) * | 2012-03-23 | 2012-07-11 | Unimicron Technology Corp | Semiconductor substrate |
| TWI474417B (en) * | 2014-06-16 | 2015-02-21 | 恆勁科技股份有限公司 | Packaging method |
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| Publication number | Publication date |
|---|---|
| TW201727827A (en) | 2017-08-01 |
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