TWI616860B - Gate driving circuit and operating method thereof - Google Patents

Abstract

A gate driving circuit includes a first-stage driving circuit including a first input transistor, a first output transistor, and a first circuit group, and a second-stage driving circuit including a second input transistor, a second output transistor, and a first Two circuit groups. The first circuit group is coupled between the first input transistor and the first output transistor. The second circuit group is coupled between the second input transistor and the second output transistor. The first input transistor is coupled to the first voltage and receives a first gate control signal. The first output transistor is coupled to the second voltage and outputs a second gate control signal. The second input transistor is coupled to the first output transistor and the first voltage and receives a second gate control signal. The second output transistor is coupled to the second voltage. The voltage value of the first gate control signal is between the first voltage and the second voltage.

Description

Gate driving circuit and operation method thereof

The present invention relates to a display, and in particular, to a gate driving circuit provided on a gate driving circuit array substrate (Gate On Array, GOA) and operating by a single-side driving method and an operation method thereof.

Generally speaking, when the gate driving circuit 1 provided on the gate driving circuit array substrate (GOA) operates by a single-sided driving method, as shown in FIG. 1, the conventional method is to drive a scanning line input on one side. The signal (such as the second driving signal SD2 in FIG. 1) is intercepted, and the scanning line driving signal (such as the first driving signal SD1 in FIG. 1) input from the other side is driven.

However, the above-mentioned conventional single-sided driving method can easily cause bright and dark lines in the horizontal direction to appear on the screen displayed by the display panel PL, which seriously affects the quality of the display screen and needs to be improved urgently.

A specific embodiment of the invention is a gate driving circuit. In this embodiment, the gate driving circuit includes a first-stage driving circuit and a second-stage driving circuit. The second-stage driving circuit is coupled to the first-stage driving circuit. The first-stage driving circuit includes a first input transistor, a first output transistor, and a first circuit group. Second-level drive The circuit includes a second input transistor, a second output transistor, and a second circuit group. The first input transistor is coupled to the first voltage and receives a first gate control signal. The first output transistor is coupled to the second voltage and outputs a second gate control signal. The first circuit group is coupled between the first input transistor and the first output transistor. The second input transistor is coupled to the first output transistor and the first voltage and receives a second gate control signal. The second output transistor is coupled to the second voltage. The second circuit group is coupled between the second input transistor and the second output transistor. The first gate control signal has a third voltage between the first voltage and the second voltage.

In one embodiment, the second gate control signal has a voltage value between the first voltage and the second voltage.

In one embodiment, the voltage value of the first gate control signal is equal to the voltage value of the second gate control signal.

In one embodiment, the first voltage is greater than the second voltage.

In one embodiment, the waveforms of the operating points (Quiescent Point) of the plurality of circuit units included in the first circuit group and the plurality of circuit units included in the second circuit group are the same.

In one embodiment, the second output transistor outputs a third gate control signal, and the third gate control signal has a voltage value between the first voltage and the second voltage.

In one embodiment, the first gate control signal is also input to the gate of another transistor. The contact of the first gate control signal is divided into two parts and one part is welded to a third voltage.

Another embodiment of the present invention is a method for operating a gate driving circuit. In this embodiment, the gate driving circuit includes a first-stage driving circuit and a second-stage driving circuit. The first-stage driving circuit includes a first input transistor, a first circuit group, and a first output transistor. The second-stage driving circuit includes a second input transistor, a second circuit group, and a second output transistor. The first circuit group is coupled between the first input transistor and the first output transistor. The second circuit group is coupled between the second input transistor and the second output transistor.

The operation method of the gate driving circuit includes the following steps: coupling a first input transistor and a second input transistor to a first voltage and coupling a first output transistor and a second output transistor to a second voltage; providing a first A gate control signal to the first input transistor; and a second output transistor outputting a second gate control signal to the second input transistor; wherein the first gate control signal has a voltage between the first voltage and the second A third voltage between the voltages.

According to the present invention, a gate driving circuit and a method for operating the same are coupled to a gate of a first input transistor (T11) of a first-stage driving circuit between a first voltage (VssQ) and a second voltage (Vcom) The third voltage (VssG) between causes the first input transistor (T11) and the first output transistor (T12) in the first-stage drive circuit and the second input transistor (T11) in the second-stage drive circuit ) And the switching state of the second output transistor (T12) are the same, so that the operating point waveform of the circuit unit in the first-stage driving circuit is the same as the operating point waveform of the circuit unit in the second-stage driving circuit, so it can be effective. Improve the phenomenon that the screen displayed in the prior art displays bright and dark lines in the horizontal direction.

The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

PL‧‧‧ Display Panel

SD1‧‧‧First drive signal

SD2‧‧‧Second drive signal

1, 2, 3, 4‧‧‧Gate driving circuit

21, 31‧‧‧ the first four levels of driving circuit

22, 32‧‧‧The last four levels of driving circuit

T11‧‧‧input transistor

QS1, QS2‧‧‧Circuit Group

T12‧‧‧ Output Transistor

ST 、 ST1 ~ ST8‧‧‧Gate control signal

VssQ‧‧‧first voltage

Vcom‧‧‧Second voltage (ground voltage)

VssG‧‧‧Third voltage

Q1 ~ Q8‧‧‧Circuit Unit

6‧‧‧Single-level GOA drive circuit

7‧‧‧Multi-level GOA drive circuit

70‧‧‧The first level GOA drive circuit

72‧‧‧Second level GOA drive circuit

T21, T31 ~ T35, T41 ~ T44, T51 ~ T56, T61 ~ T66‧‧‧Transistors

C‧‧‧Capacitor

P (n), P (n + 4), K (n), K (n + 4), G (n), G (n + 4), G (n + 8), Q (n), Q ( n-2), Q (n + 2), Q (n + 4), Q (n + 8)

ST (n + 4), ST (n + 8) ‧‧‧Gate control signal

HC1 ~ HC8, VGH‧‧‧Voltage

S10 ~ S14‧‧‧‧step

FIG. 1 is a schematic diagram showing that the gate driving circuit of the prior art using a single-side driving method easily causes bright and dark lines in the horizontal direction.

FIG. 2A is a functional block diagram of a gate driving circuit according to a preferred embodiment of the present invention.

FIG. 2B is a schematic diagram showing that the operating point waveforms of circuit units Q5 to Q8 of the second-stage driving circuit are significantly higher than the operating point waveforms of circuit units Q1 to Q4 of the first-stage driving circuit.

FIG. 3 is a functional block diagram of a gate driving circuit according to another preferred embodiment of the present invention.

FIG. 4 illustrates an embodiment of the gate driving circuit.

FIG. 5 is a schematic diagram showing that the operating point waveforms of the circuit units Q1 to Q4 of the first-stage driving circuit are the same as the operating point waveforms of the circuit units Q5 to Q8 of the second-stage driving circuit.

FIG. 6 illustrates an embodiment of a single-level GOA driving circuit.

FIG. 7 illustrates an embodiment in which a first-level GOA driving circuit and a second-level GOA driving circuit in a multi-level GOA driving circuit are connected in series with each other.

FIG. 8 is a flowchart illustrating an operation method of a gate driving circuit according to another preferred embodiment of the present invention.

The invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts of regions have been enlarged for clarity. Throughout the description, the same reference numerals denote the same elements. It should be understood that when an element such as a region or substrate is referred to as being "on" or "connected (or referred to as a coupling)" or "electrically connected" to another element, it can be directly on the other element. It is connected to (or called coupled with) or electrically connected to another element, or an intermediate element may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected (or referred to as" coupled ") may refer to a physical and / or electrical connection.

A preferred embodiment of the present invention is a gate driving circuit. In this embodiment, the gate driving circuit may be disposed on the gate driving circuit array substrate (GOA) and may be driven by a single-sided driving method, but is not limited thereto.

First, please refer to FIG. 2A, which is a functional block diagram of a gate driving circuit in this embodiment. As shown in FIG. 2A, the gate driving circuit 2 may include at least a first four-stage driving circuit 21 and a last four-stage driving circuit 22. Each of the first four stages of the driving circuit 21 includes an input transistor T11, a circuit group QS1, and an output transistor T12. Each of the last four stages of the driving circuit 22 includes an input transistor T11, a circuit group QS2, and an output transistor T12. In the first four-stage driving circuit 21, a circuit group QS1 is coupled between the input transistor T11 and the output transistor T12. In other words, the circuit groups QS1 are respectively coupled to the inputs The second terminal (or drain) of the transistor T11 and the control terminal (or gate) of the output transistor T12. In the last four-stage driving circuit 22, a circuit group QS2 is coupled between the input transistor T11 and the output transistor T12. In other words, the circuit group QS2 is respectively coupled to the second terminal (or called the drain) of the input transistor T11 and the control terminal (or called the gate) of the output transistor T12.

The input transistor T11 of the front four-stage driving circuit 21 and the input transistor T11 of the rear four-stage driving circuit 22 are respectively coupled to the first voltage VssQ. In other words, the first terminal (or source) of the input transistor T11 of the first four-stage driving circuit 21 and the second-stage driving circuit 22 are both coupled to the first voltage VssQ; the output transistor T12 of the first-stage driving circuit 21 The output transistors T12 of the four-stage driving circuit 22 are respectively coupled to a second voltage (ground voltage) Vcom, where the first voltage VssQ is greater than the second voltage Vcom. In other words, the first terminals (or sources) of the output transistors T12 of the first four-stage driving circuit 21 and the second four-stage driving circuit 22 are both coupled to the second voltage (ground voltage) Vcom. In the embodiment of the present invention, the second terminal (or drain) of the output transistor T12 of the previous four-stage driving circuit 21 is coupled to the control terminal (or the so-called Gate) is an example, but it is not limited to this.

In order to improve the bright and dark line phenomenon encountered in the prior art, in this embodiment, the gate of the input transistor T11 of the first four-stage driving circuit 21 of the gate driving circuit 2 is directly coupled to the ground voltage Vcom, so that the first four-stage driving The gate control signal ST received by the circuit 21 has a ground voltage Vcom, and the gate control signal ST is also referred to as an initial gate control signal. Thereby, the input transistor T11 of the first four-stage driving circuit 21 can be maintained in a constant-on state, and the voltage of the circuit group QS1 in the first four-stage driving circuit 21 can be maintained. The circuit units Q1 to Q4 can all be charged (or called both) to be charged to the first voltage VssQ, which is considered to be quite stable.

However, in this embodiment, because the working point (Quiescent Point) voltage of the circuit units Q1 to Q4 of the circuit group QS1 in the first four-stage driving circuit 21 is relatively low, the output transistor T12 from the first four-stage driving circuit 21 is relatively low. The gate control signals ST1 to ST4 output to the input transistor T11 of the fourth-stage driving circuit 22 are in a floating state, which results in poor stability of the input transistor T11 of the fourth-stage driving circuit 22. As shown in FIG. 2B, this will cause the operating point waveforms of the circuit units Q5 ~ Q8 of the circuit group QS2 in the last four-stage drive circuit 22 to be significantly higher than the circuit units Q1 ~ of the circuit group QS1 in the previous four-stage drive circuit 21. The working point waveform of Q4 makes the phenomenon of bright and dark lines not completely improved. In this embodiment, the first four-stage driving circuit 21 has its own corresponding input transistor T11 and output transistor T12, and the gate terminals of the input transistor T11 of the first four-stage driving circuit 21 respectively receive the same starting gate control. As for the signal ST, the second terminals of the output transistor T12 of the first four-stage driving circuit 21 respectively output gate control signals ST1 to ST4. The last four-stage driving circuit 22 has its own corresponding input transistor T11 and output transistor T12. The gate terminals of the input transistor T11 of the last four-stage driving circuit 22 respectively receive the corresponding gate control signals ST1 to ST4. The second terminals of the output transistor T12 of the stage driving circuit 22 respectively output gate control signals ST5 to ST8.

In order to further overcome the disadvantages of the above embodiments, please refer to FIG. 3, which is a functional block diagram of a gate driving circuit in another preferred embodiment of the present invention.

As shown in FIG. 3, the gate driving circuit 3 may include at least the first four stages of driving The circuit 31 and the subsequent four-stage driving circuit 32. Each of the first four stages of the driving circuit 31 includes an input transistor T11, a circuit group QS1, and an output transistor T12. The last four-stage driving circuit 32 includes an input transistor T11, a circuit group QS2, and an output transistor T12. In the first four-stage driving circuit 31, a circuit group QS1 is coupled between the input transistor T11 and the output transistor T12. In the last four-stage driving circuit 32, a circuit group QS2 is coupled between the input transistor T11 and the output transistor T12.

The first terminals of the input transistors T11 of the first four-stage driving circuit 31 and the second-stage driving circuit 32 are coupled to the first voltage VssQ; the first-four-stage driving circuit 31 and the output transistors T12 of the second-stage driving circuit 32 are coupled. Connected to a second voltage (ground voltage) Vcom, where the first voltage VssQ is greater than the second voltage Vcom.

The input transistor T11 of the first four-stage driving circuit 31 receives the gate control signal ST and the output transistor T12 of the first four-stage driving circuit 31 outputs the gate control signals ST1 to ST4 to the input transistor T11 of the fourth-stage driving circuit 32. Similarly, the input transistor T11 of the last four-stage driving circuit 32 receives the gate control signals ST1 to ST4, and the output transistor T12 of the latter four-stage driving circuit 32 outputs the gate control signals ST5 to ST8.

In actual application, if the gate driving circuit 3 also includes another four-level driving circuit (not shown), the input transistor of the other four-level driving circuit will receive the output of the output transistor T12 of the next four-level driving circuit 32. The gate control signals ST5 ~ ST8, and the output transistor of the other four-level drive circuit will output another set of gate control signals to the next four-level drive circuit, and so on. It should be noted that the gate driving circuit 3 may include a plurality of stages of driving circuits, and the number of the plurality of stages of driving circuits may depend on actual requirements. It is not limited to this embodiment. The rest can be deduced by analogy and will not be repeated here.

Next, referring to FIG. 4, in an embodiment, it is assumed that the first four-stage driving circuit of the gate driving circuit 4 includes four input transistors T11, four circuit units Q1 to Q4, and four output transistors T12. The last four-stage driving circuit of the pole driving circuit 4 includes four input transistors T11, four circuit units Q5 to Q8, and four output transistors T12.

The first terminals (or sources) of the four input transistors T11 in the first four stages of driving circuits are all coupled to the voltage VGH, and the second terminals (or sinks) of the four input transistors T11 are respectively coupled. The control terminals (or gates) of the four output transistors T12 and the control terminals (or gates) of the four input transistors T11 are controlled by the gate control signal ST; the circuit units Q1 ~ Q4 are respectively coupled Connected between the second terminal (or drain) of the four input transistors T11 and the control terminal (or gate) of the four output transistors T12; the first terminal of the four output transistors T12 ( (Or source) are respectively coupled to the voltages HC1 ~ HC4 and their second ends (or drains) are respectively coupled to the control terminals (or gates) of the four input transistors T11 of the four-stage drive circuit .

It should be noted that, in practical applications, the voltage VGH may be equal to the aforementioned first voltage VssQ and the voltages HC1 to HC4 may be equal to the aforementioned second voltage (ground voltage) Vcom, but it is not limited thereto. In addition, the gate control signal ST may have a voltage value between the first voltage VssQ and the second voltage (ground voltage) Vcom, such as the third voltage VssG, but is not limited thereto.

The first terminal (or source) of the four input transistors T11 of the last four stages of the driving circuit are all coupled to the voltage VGH, and the second terminal (or so-called (Drain) are respectively coupled to the control terminals (or gates) of the four output transistors T12 and the control terminals (or gates) of the four input transistors T11 are controlled by the four The gate control signals ST1 ~ ST4 output by each output transistor T12; the four circuit units Q5 ~ Q8 are respectively coupled to the second end (or drain) of the four input transistors T11 and the four output circuits. The control terminal (or gate) of the crystal T12; the first terminal (or source) of the four output transistors T12 are respectively coupled to the voltages HC5 ~ HC8 and the second terminal (or the drain) ) Output gate control signals ST5 ~ ST8 respectively.

In practical applications, the voltages HC5 to HC8 may be equal to the aforementioned second voltage (ground voltage) Vcom, but it is not limited thereto. In addition, the gate control signals ST1 ~ ST4 output by the four output transistors T12 of the first four-stage driving circuit and the gate control signals ST5 ~ ST8 output by the four output transistors T12 of the fourth-stage driving circuit are both It may have a voltage value between the first voltage VssQ and the second voltage (ground voltage) Vcom, such as the third voltage VssG, but is not limited thereto.

It should be noted that since the gate control signal ST of the four input transistors T11 input to the first four-stage driving circuits in this embodiment has a voltage value (for example, the third voltage VssG) that is greater than the input to the first four in the above embodiment The second voltage (ground voltage) Vcom of the gate control signal ST of the input transistor T11 of the stage driving circuit makes the four input transistors T11 of the previous four-stage driving circuit in the embodiment all slightly open, and It is not like the input transistor T11 of the previous four-stage driving circuit in the above embodiment is in a constant-on state, which also causes the four output transistors T12 coupled to the four input transistor T11 in this embodiment to also be in the micro state. ON state, so in this embodiment, the four output transistors T12 of the previous four-stage drive circuit output to the last four-stage drive. The gate control signals ST1 ~ ST4 of the dynamic circuit also have a voltage value between the first voltage VssQ and the second voltage Vcom (for example, the third voltage VssG), thereby making the four input transistors in the last four stages of the driving circuit. T11 and four output transistors T12 are also in a slightly open state.

As a consequence, since the four input transistors T11 and four output transistors T12 in the first four-stage drive circuits are the same as the four input transistors T11 and four output transistors T12 in the four-stage drive circuits, Both are in a slightly open state, so that the operating point waveforms of the four circuit units Q1 ~ Q4 in the first four-stage driving circuit and the operating point waveforms of the four circuit units Q5 ~ Q8 in the latter four-stage driving circuit will also be the same, such as Figure 5 shows.

Compared with the operating point waveforms of the four circuit units Q5 ~ Q8 of the subsequent four-stage driving circuit shown in FIG. 2B, the operating point waveforms of the four circuit units Q1 ~ Q4 of the previous four-stage driving circuit are significantly higher than before. The operating point waveforms of the four circuit units Q1 ~ Q4 of the four-stage driving circuit are the same as the operating point waveforms of the four circuit units Q5 ~ Q8 of the latter four-stage driving circuit, which represent the previous four-stage driving circuit and the subsequent stages in this embodiment. The operation of the driving circuit becomes more consistent and stable, and there is no phenomenon that the transistor in the above embodiment is turned on or off, so the phenomenon of bright and dark lines in the horizontal direction of the display screen of the display panel can be effectively improved.

Next, please refer to FIG. 6, which illustrates an embodiment of a single-level GOA driving circuit. As shown in FIG. 6, in the single-level GOA driving circuit 6, the first terminal (or source) of the transistor T44 is coupled to the second terminal (or drain) of the input transistor T11 and the transistor T44. The second terminal (or drain) is coupled to the first voltage VssQ and the transistor The control terminal (or gate) of the body T44 is controlled by the second voltage (ground voltage) Vcom; the second terminal (or the drain) of the transistors T55 and T56 are both coupled to the first voltage VssQ and its control The terminals (or gates) are all coupled to the contact Q (n-2); the second terminals (or drains) of the transistors T52 and T54 are all coupled to the first voltage VssQ and their control terminals (or (Referred to as the gate) are all coupled to the contact Q (n); the first ends (or sources) of the transistors T51 and T53 are coupled to the control end (or the gate) of the transistor T51, And the second terminal (or drain) of transistor T51 is respectively coupled to the first terminal (or source) of transistor T56 and T52 and the control terminal (or gate) of transistor T53, and The second terminal (or drain) of transistor T53 is coupled to the first terminal (or source) of transistors T54 and T55 and the control terminal (or gate) of transistors T32, T34, and T42, respectively. Pole) at the contact point P (n); the second ends (or drains) of the transistors T34 and T42 are both coupled to the first voltage VssQ, and the second ends (or drains) of the transistor T32 are coupled Connected to the third voltage VssG; the first terminal (or source) of transistor T42 is coupled to the second terminal (or source) of input transistor T11 Is the drain) and the first end (or source) of transistor T44; one end of capacitor C is coupled to the second end (or drain) of input transistor T11 and the first end of transistor T44 Between one end (or source) and the other end is coupled to the first end (or source) of the transistor T32.

The second terminals (or drains) of the transistors T65 and T66 are both coupled to the first voltage VssQ and their control terminals (or gates) are all coupled to the contact Q (n-2); the transistor T62 And the second terminal (or drain) of T64 is coupled to the first voltage VssQ and its control terminal (or gate) is coupled to contact Q (n); the first of transistors T61 and T63 The terminals (or sources) are coupled to the control terminals (or gates) of transistor T61, and the second terminals (or drains) of transistor T61 are coupled to the transistors T66 and T62, respectively. First end (or (Referred to as the source) and the control terminal (or gate) of the transistor T63, and the second terminal (or the drain) of the transistor T63 is coupled to the first terminal (or the transistor T64 and T65) (or (Referred to as the source) is connected to the control terminal (or gate) of the transistors T33, T35 and T43 at the contact K (n); the second terminal (or referred to as the drain) of the transistors T35 and T43 is coupled The first voltage VssQ, and the second terminal (or drain) of the transistor T33 is coupled to the third voltage VssG; the first terminal (or source) of the transistor T43 is coupled to the first terminal of the input transistor T11. The contact Q (n) between the two terminal (or drain) and the control terminal (or gate) of the output transistor T12; the first terminal (or source) of the transistor T33 is coupled Between capacitor C and transistor T32 and contact G (n).

The first terminal (or source) of the input transistor T11 is coupled to the voltage VGH, and the second terminal (or drain) of the input transistor T11 is coupled to the control terminal (or gate) of the output transistor T12. ) And the control terminal (or gate) of the input transistor T11 is controlled by the gate control signal ST; the first terminal (or source) of the output transistor T12 is coupled to the voltage HC1 and its second terminal ( (Also called the drain) are respectively connected to the first terminal (or source) of the transistors T34 and T35 and the control terminal (or gate) of the input transistor T11 of the other GOA circuit; the transistor T41 The control terminal (or gate) is controlled by the gate control signal ST (n + 4) and its first terminal (or source) is coupled between the transistors T12 and T21, and its second Terminal (or drain) is coupled to the first voltage VssQ; the first terminal (or source) of transistor T21 is coupled to voltage HC1 and the second terminal (or drain) is coupled to transistor T31 The first terminal (or source) of the transistor T31 is connected to the contact G (n); the second terminal (or drain) of the transistor T31 is coupled to the third voltage VssG and its control terminal (or gate) Coupled to contact G (n + 4).

It should be noted that the output transistor T12 in the single-stage GOA drive circuit 6 can output the gate drive signal to the control terminal (or the input transistor T11 of the GOA circuit of the other stage) through its second end (or called the drain). (Called the gate). In practical applications, the contact of the gate control signal ST can also be divided into two parts, one of which can be soldered to the contact of the third voltage VssG, and the other can be coupled to the control terminal (or Gate), but not limited to this.

Next, please refer to FIG. 7, which illustrates an embodiment in which a first-level GOA driving circuit and a second-level GOA driving circuit in a multi-level GOA driving circuit are connected in series with each other.

As shown in FIG. 7, in the multi-level GOA driving circuit 7, the first-level GOA driving circuit 70 and the second-level GOA driving circuit 72 are connected in series with each other. The first-stage GOA driving circuit 70 is coupled to output the gate control signal ST1 through the second terminal (or called the drain) of the output transistor T12 to the control terminal of the input transistor T11 of the second-stage GOA driving circuit 72. (Or gate).

The first terminal (or source) of the input transistor T11 of the second-stage GOA driving circuit 72 is coupled to the voltage VGH, and the second terminal (or drain) of the input transistor T11 is coupled to the output transistor T12. The control terminal (or gate) and the control terminal (or gate) of the input transistor T11 are controlled by the gate control signal ST1; the first terminal of the output transistor T12 of the second-level GOA driving circuit 72 ( Or the source) is coupled to the voltage HC1 and its second end (or the drain) is respectively connected to the first end (or the source) of the transistors T34 and T35 and the input voltage of the third-level GOA circuit The control terminal (or gate) of the crystal T11. The second-stage GOA driving circuit 72 is through the second terminal of its output transistor T12 (or (Referred to as the drain) outputs the gate control signal ST2 to the control terminal (or gate) of the input transistor T11 of the third-level GOA circuit.

It should be noted that if the multi-level GOA driving circuit 7 includes only the first-level GOA driving circuit 70 and the second-level GOA driving circuit 72, the second terminal (or (Drain) is coupled to and output the gate control signal to the corresponding scan line on the display panel to drive the corresponding scan line, but not limited to this. As for the detailed circuit structure and the component coupling relationship of the first-level GOA driving circuit 70 and the second-level GOA driving circuit 72, reference may be made to the description of FIG. 6 above, which will not be repeated here.

Another embodiment of the present invention is a method for operating a gate driving circuit. In this embodiment, the operation method of the gate driving circuit is to drive the gate driving circuit in a single-sided driving manner, and the gate driving circuit is disposed on the gate driving circuit array substrate (GOA).

Please refer to FIG. 8. FIG. 8 is a flowchart illustrating an operation method of the gate driving circuit of this embodiment. As shown in FIG. 8, the operation method of the gate driving circuit may include at least the following steps: Step S10: The input transistor T11 of the first four-stage driving circuit 31 and the input transistor T21 of the last four-stage driving circuit 32 are coupled to the first A voltage VssQ, and the output transistor T12 of the first four-stage drive circuit 31 and the output transistor T22 of the last four-stage drive circuit 32 are respectively coupled to a second voltage (ground voltage) Vcom, where the first voltage VssQ is greater than the second voltage Vcom; Step S12: Provide the gate control signal ST to the first four-stage driving circuit 31 The gate of the input transistor T11, and the gate control signal ST has a voltage value between the first voltage VssQ and the second voltage (ground voltage) Vcom, such as the third voltage VssG; and step S14: the first four The output transistor T12 of the stage driving circuit 31 outputs the gate control signal ST1 to the input transistor T11 of the last four stage driving circuit 32. The gate control signal ST1 also has a voltage between the first voltage VssQ and the second voltage (ground voltage). The voltage value between Vcom, for example, the third voltage VssG, that is, the voltage value of the gate control signal ST received by the first four-stage drive circuit 31 and the gate control signal ST1 received by the fourth-stage drive circuit 32 The voltage values are equal.

Similarly, the output transistor T12 in the last four-stage driving circuit 32 outputs the gate control signal ST2 to the corresponding scan line on the display panel to drive the corresponding scan line, and the gate control signal ST2 also has A voltage value between the first voltage VssQ and the second voltage (ground voltage) Vcom, such as the third voltage VssG, but is not limited thereto.

In actual application, it is assumed that the circuit group QS1 in the first four-stage driving circuit 31 includes a plurality of circuit units Q1 to Q4 and the circuit group QS2 in the last four-stage driving circuit 32 includes a plurality of circuit units Q5 to Q8, as shown in FIG. 5 As shown, the waveforms of the operating points of the plurality of circuit units Q1 to Q4 of the circuit group QS1 are the same as the waveforms of the operating points of the plurality of circuit units Q5 to Q8 of the circuit group QS2.

It should be noted that the gate driving circuit operation method in this embodiment can be applied to the foregoing embodiments, for example, FIG. 3, FIG. 4, FIG. 6 or FIG. 7, and the components of each of the foregoing embodiments are described. For its related connection relationship, you can view the aforementioned implementation The illustrations are not repeated here. Furthermore, the gate driving circuit operating method of the present invention is based on the gate driving circuit shown in FIG. 3 as an example, but is not limited thereto.

From the detailed description of the above preferred embodiments, it is hoped that the features and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, the intention is to cover various changes and equivalent arrangements within the scope of the patents to be applied for in the present invention. With the above detailed description of the preferred embodiments, it is hoped that the features and spirit of the present invention can be more clearly described, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, the intention is to cover various changes and equivalent arrangements within the scope of the patents to be applied for in the present invention.

3‧‧‧Gate driving circuit

31‧‧‧The first four levels of driving circuit

32‧‧‧Last four-stage driving circuit

T11‧‧‧input transistor

QS1, QS2‧‧‧Circuit Group

T12‧‧‧ Output Transistor

ST 、 ST1 ~ ST8‧‧‧Gate control signal

VssQ‧‧‧first voltage

Vcom‧‧‧Second Voltage

Claims (10)

A gate driving circuit includes: a first-stage driving circuit including: a first input transistor coupled to a first voltage and receiving a first gate control signal; a first output transistor coupled to a A second voltage and outputting a second gate control signal; and a first circuit group coupled between the first input transistor and the first output transistor; and a second-stage driving circuit coupled to the The first-stage driving circuit includes: a second input transistor coupled to the first output transistor and the first voltage and receiving the second gate control signal; a second output transistor coupled to the second Voltage; and a second circuit group coupled between the second input transistor and the second output transistor; wherein the first gate control signal has a voltage between the first voltage and the second voltage Between a third voltage. The gate driving circuit according to item 1 of the patent application range, wherein the second gate control signal has a voltage value between the first voltage and the second voltage. The gate driving circuit according to item 1 of the scope of the patent application, wherein the voltage value of the first gate control signal is equal to the voltage value of the second gate control signal. The gate driving circuit according to item 1 of the patent application scope, wherein the first voltage is greater than the second voltage. The gate driving circuit according to item 1 of the scope of patent application, wherein the plurality of circuit units included in the first circuit group and the plurality of circuits included in the second circuit group The waveform of the Quiescent Point of the unit is the same. The gate driving circuit according to item 1 of the scope of patent application, wherein the second output transistor outputs a third gate control signal, and the third gate control signal has a voltage between the first voltage and the second The voltage value between voltages. The gate driving circuit according to item 1 of the scope of patent application, wherein the first gate control signal is also input to the gate of another transistor, and the contact point of the first gate control signal is divided into two parts and A part of it is welded to the third voltage. A method for operating a gate driving circuit. The gate driving circuit includes a first-stage driving circuit and a second-stage driving circuit. The first-stage driving circuit includes a first input transistor, a first circuit group, and a The first output transistor includes a second input transistor, a second circuit group, and a second output transistor. The first circuit group is coupled to the first input transistor and the first output transistor. Between an output transistor, the second circuit group is coupled between the second input transistor and the second output transistor. The operation method includes the following steps: the first input transistor and the second input The transistor is coupled to a first voltage and the first output transistor and the second output transistor are coupled to a second voltage; a first gate control signal is provided to the first input transistor; and the first An output transistor outputs a second gate control signal to the second input transistor; wherein the first gate control signal has a third voltage between the first voltage and the second voltage. The operation method as described in item 8 of the scope of patent application, wherein the second gate control signal has a voltage value between the first voltage and the second voltage. The operating method according to item 8 of the scope of patent application, wherein the first voltage is greater than the second voltage.