TWI600071B - Method for improving surface flatness of tantalum wafer epitaxial layer - Google Patents

Description

Method for improving surface flatness of tantalum wafer epitaxial layer

The present invention relates to the field of semiconductor fabrication, and more particularly to a method of improving the surface flatness of an epitaxial layer.

In the method for manufacturing a crystal layer, the ends of the single crystal germanium ingot are cut to provide a block shape, and the outer side of the crucible is ground to make the overall diameter uniform to obtain a block body, and an oriented plane is formed on the block. Or orientation notch to indicate a particular crystal orientation, and then the block is sliced at a predetermined angle to the axial direction. The surrounding portion of the sliced wafer is chamfered to avoid chipping or fragmentation of the peripheral portion of the wafer. Next, as a smoothing process, wafer double-side polishing (DDSG) is performed to polish the surfaces on both sides of the wafer. Next, wafer single-sided polishing (SDSG) is performed. Subsequent wafer double-sided polishing (DSP) simultaneously polishes the surfaces on both sides of the wafer. Next, wafer single side polishing (SMP) is performed. Further, when an epitaxial layer of a single crystal germanium is formed on the surface of the wafer by epitaxial growth, an epitaxial wafer can be obtained.

However, the conventional manufacturing method has the following problems.

Machining processes (such as slicing, grinding) will inevitably result in mechanical or mechanical scratches on the wafer. Since the epitaxial layer formation step based on epitaxial growth amplifies scratches or damage (lattice distortion) on the surface of the wafer, the defect portion due to mechanical processing such as polishing is used as a starting point in the epitaxial layer. Crystal defects such as poor row or stacking errors occur, and in some In the case, such defects can cause surface defects on the surface of the epitaxial layer. Moreover, when the scratch or mechanical damage caused by the machining process is severe, slippage is formed in the formed epitaxial layer.

The prior art is to immerse the wafer in an etchant after polishing to chemically etch both sides of the wafer, thereby reducing the incidence of scratch defects caused by the convex defects on the surface of the single crystal germanium epitaxial film, and Reduce the height of such raised defects. However, since the immersion etching etches the entire wafer surface at the same time, the wafer surface removal amount control affects the shape control, and the predetermined wafer surface shape cannot be obtained, which may make the surface state (such as flatness) difficult to improve, and may even Worse than before grinding. Moreover, the smoothing process mainly based on mechanical (such as grinding) is applied to the vapor phase growth of the single crystal germanium film, and mechanical damage or processing scratches are inevitably formed on the wafer, even after subsequent water polishing or polishing with an abrasive. It is also impossible to effectively reduce surface defects or slip formation on the epitaxial layer.

There are also prior art systems for controlling the etching solution to control the smoothing process, but it is easy to leave the etching liquid on the upper surface of the wafer for too long, so that the wafer plane and the outer edge shape cannot be controlled, resulting in deterioration of wafer flatness.

Accordingly, there is still a need for methods for increasing the surface flatness of wafers and epitaxial layers.

The invention provides a method for improving the surface flatness of a wafer of a silicon wafer, comprising: wet etching, grinding and polishing the silicon wafer obtained by slicing a single crystal germanium ingot; and detecting the surface roughness of the wafer to be processed; Calculating and obtaining a temperature control profile according to the profile; according to the profile, the partition heats and partitions the temperature of the germanium wafer, and planarizes by dry etching; polishing the germanium wafer; and surface of the germanium wafer Forming an epitaxial layer; wherein the surface flatness measurement is performed on the entire surface of the obtained epitaxial germanium wafer, and the nanotopogr _a phy of the epitaxial germanium wafer surface flatness is less than 25 nm.

In one embodiment, the dry etch is a plasma etch.

In one embodiment, the plasma used in the etching of the etching gases include _{CF 4, C 2 F 6,} SF 6, Cl 2 and the like.

In one embodiment, the wet etch is an immersion double sided etch.

In one embodiment, the wet etching etchant is a mixture of hydrofluoric acid, nitric acid, phosphoric acid, and water.

In one embodiment, the surface roughness of the germanium wafer is detected by a detecting unit.

In one embodiment, the zone heating is performed with a zoned resistance heater.

In one embodiment, the zone heating is performed by a micro-zone temperature control unit.

In one embodiment, the temperature of the germanium wafer is controlled at 120-480 °C.

The method of the present invention can increase the smoothness of the surface of the germanium wafer. Therefore, when the epitaxial layer is grown on the surface of the germanium wafer by an epitaxial process, surface defects and slip on the epitaxial layer during epitaxial growth can be reduced.

1 is a flow chart of a method for improving the flatness of an epitaxial wafer surface according to the present invention.

2 is a flow chart of a method for improving the flatness of an epitaxial wafer surface according to an embodiment of the invention.

The method of the present invention will now be described in more detail in conjunction with the accompanying drawings in which the preferred embodiment of the invention Favorable effect. Therefore, the following description is to be understood as a broad understanding of the invention, and not as a limitation of the invention.

In the interest of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail as they may obscure the present invention in unnecessary detail. It should be understood that in the development of any actual embodiment, a large number of implementation details must be made to achieve a particular goal of the developer, such as changing from one embodiment to another in accordance with the limitations of the system or related business. In addition, such development work should be considered complex and time consuming, but is only routine work for those of ordinary skill in the art.

The invention is more specifically described in the following paragraphs by way of example with reference to the drawings. Advantages and features of the present invention will be apparent from the description and appended claims. It should be noted that the drawings are all in a very simplified form and both use non-precise proportions, and are only for convenience and clarity to assist the purpose of the embodiments of the present invention.

Referring to FIG. 1 , in the embodiment, a method for improving the surface flatness of the epitaxial layer of the tantalum wafer is proposed, which comprises the following steps: S101: sequentially etching the thin disc-shaped single crystal germanium ingots by wet etching. And polishing; S102 detects the surface roughness of the wafer to be processed by the detecting unit; S103 calculates and obtains a temperature control distribution map according to the data of the concave and convex condition; S104 according to the profile, heats and controls the temperature of the wafer by a partition resistance, and planarizes the wafer by dry etching; S105 performs polishing; and S106 forms an epitaxial layer on the surface of the wafer.

Further, in an embodiment, please refer to Fig. 2 to explain the method of the present invention in more detail.

First, a single crystal germanium ingot (S201) is provided, and the steps of grinding, rounding, positioning or positioning V-groove, slicing, chamfering, double-side grinding, single-side grinding (S202~S207) are sequentially performed to prepare a tantalum wafer. . Next, the surface damage of the tantalum wafer is mechanically damaged by immersion double-sided etching (S208), and double-side polishing (S209) and edge polishing (S210) are performed.

The surface of the wafer to be processed is detected by the detecting unit, and the detection data is saved (S211). The detecting unit may be, for example, Wafersight 2 (available from KLA-Tencor), LSW-3020FE (available from Kobelco), and Nanometro 300TT. -A (available from Kuroda), etc., the detection data can be stored in a memory. The data of the surface roughness of the wafer after the detection unit is detected is received, and the wafer electrostatic chuck partition temperature control profile and the etching time are calculated (S212).

Next, the twine substrate is heated by the electrostatic chuck partition control resistor, the temperature of the wafer substrate is controlled by the partition, and the germanium wafer flattening process is performed by plasma etching (S213), whereby the smoothness of the surface of the germanium wafer can be improved.

The above steps can be performed using a micro-zone temperature control unit. The micro-zone temperature control unit is composed of an array of Peltier devices and/or electric resistance heaters, which may be polyimine heaters, Silicone heaters, mica heaters, metal heaters (such as tungsten, nickel/chromium alloys, molybdenum, niobium, etc.), ceramic heaters (such as tungsten carbide), semiconductor heaters, carbon heaters, or any other suitable heating/ Cooling element. The temperature control unit can incorporate different designs or configurations, such as a screen printing heater, a wound heater, an etched foil heater, or any other suitable design. The partitions of the micro-zone temperature control unit can independently control the temperature, and the control circuit ranges from 0-20W. The overall area of the micro-zone temperature control unit can be from 90% to 120% of the area of the wafer substrate.

The single-sided mirror polishing of the germanium wafer after the plasma etching treatment is performed (S214). Then, epitaxial growth (S215) can be performed on the surface of the germanium wafer subjected to the above treatment, thereby effectively reducing surface defects and slippage on the epitaxial layer during epitaxial growth.

In the above embodiment, the wet etching is immersion double-sided etching, and the etching liquid used is a mixture of hydrofluoric acid, nitric acid, phosphoric acid, and water.

In the above embodiment, the dry etching is plasma etching, and the etching gas used includes CF ₄ , C ₂ F ₆ , SF ₆ , Cl _{2 ,} and the like.

Through the above steps of wet etching, zone heating, zone temperature control, dry etching, etc., the smoothness of the surface of the germanium wafer can be effectively improved. Therefore, when the epitaxial layer is grown on the surface of the wafer with better surface smoothness, the surface defects and slippage of the epitaxial layer can be reduced, thereby improving the performance of the subsequent device.

The above description of the specific embodiments is intended to be illustrative of the invention, and is not intended to limit the invention. It will be understood by those skilled in the art that various changes or modifications may be made to the present invention without departing from the scope of the appended claims.

Claims (8)

A method for improving the flatness of the surface of the epitaxial layer of the tantalum wafer comprises: wet etching, grinding and polishing the tantalum wafer obtained by slicing the single crystal germanium ingot; detecting the unevenness of the surface of the wafer to be processed; Data, calculating and obtaining a temperature control profile; according to the profile, the partition heats and partitions the temperature of the germanium wafer, and planarizes by dry etching; polishing the germanium wafer; and forming epitaxial grains on the surface of the germanium wafer a layer; wherein the surface flatness of the entire surface of the obtained epitaxial wafer is measured, and the nanotopography of the surface flatness of the epitaxial wafer is less than 25 nm. The method of claim 1, wherein the dry etching is plasma etching. The method of claim 2, wherein the plasma etching uses an etching gas comprising CF ₄ , C ₂ F ₆ , SF ₆ , and Cl ₂ . The method of claim 1, wherein the wet etching is an immersion double-sided etching. The method of claim 1, wherein the wet etching etchant is a mixture of hydrofluoric acid, nitric acid, phosphoric acid and water. The method of claim 1, wherein the surface roughness of the germanium wafer is detected by a detecting unit. The method of claim 1, wherein the zone heating is performed by a zoned resistance heater. The method of claim 1, wherein the zone heating is performed by a micro-zone temperature control unit.