TW201810401A - Method for improving surface flatness of tantalum wafer epitaxial layer - Google Patents

Abstract

The invention provides a method for improving the flatness of the surface of a silicon wafer epitaxial wafer, which comprises: sequentially performing wet etching, grinding, and polishing of slices of a thin circular plate-shaped single crystal silicon ingot; and detecting a silicon wafer to be processed by a detection unit. Surface unevenness condition; According to the data of the unevenness condition, calculate and obtain the distribution map of the temperature division of the wafer; according to the distribution map, heat and control the temperature of the wafer substrate with the division resistance, and planarize the silicon wafer by plasma dry etching And performing final polishing; wherein, when epitaxial growth is performed on the surface of the silicon wafer to grow the epitaxial wafer, the surface flatness measurement of the entire surface of the resulting epitaxial wafer is performed, and the nanotopography of the surface flatness of the silicon wafer is less than 25 nm.

Description

Method for improving surface flatness of epitaxial layer of silicon wafer

The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for improving the flatness of the surface of an epitaxial layer.

In the conventional epitaxial layer manufacturing method, both ends of a single crystal silicon ingot are cut out to provide a block-like shape. The outside of the silicon ingot is ground to make the entire diameter uniform to obtain a block body, which forms an orientation plane for the block. Orientation notch is used to indicate a specific crystal orientation, and then the block is sliced in such a manner as to make a predetermined angle to the axial direction. The surrounding portion of the wafer obtained by slicing is chamfered to avoid chipping or debris in the peripheral portion of the wafer. Next, as a smoothing step, wafer double-side grinding (DDSG) is performed to polish the surfaces of both sides of the silicon wafer. Next, wafer single-side grinding (SDSG) is performed. Subsequent wafer double-side polishing (DSP) can simultaneously polish both sides of the wafer. Next, wafer single-side polishing (SMP) is performed. In addition, when an epitaxial layer of single crystal silicon is formed on the surface of the wafer by an epitaxial growth method, an epitaxial wafer can be obtained.

However, the conventional manufacturing method has the following problems.

Mechanical processing processes (such as slicing and grinding) will inevitably form mechanical damage or mechanical scratches on the wafer. Since the epitaxial layer-forming step based on epitaxial growth will amplify the scratches or damages on the wafer surface (lattice distortion), in this epitaxial layer, the defects caused by machining such as grinding are used as a starting point. , Crystal defects such as misalignment or stacking errors can occur, and in some cases In the case, such defects would cause surface defects on the surface of the epitaxial layer. In addition, when the scratch or mechanical damage caused by the machining process is serious, slippage may be formed in the formed epitaxial layer.

In the prior art, the wafer was immersed in an etchant after chemical polishing to chemically etch both surfaces of the wafer, which can reduce the incidence of scratch defects caused by raised defects on the surface of the single crystal silicon epitaxial film, and Reduce the height of such raised defects. However, since the immersion etching will etch the entire wafer surface at the same time, the removal control of the wafer surface will affect the shape control, and the predetermined wafer surface shape cannot be obtained, which may make it difficult to improve the surface state (such as flatness), and may even Worse than before grinding. In addition, the mechanical (such as polishing) smoothing step is applied to the single crystal silicon thin film before the vapor phase growth, mechanical damage or processing scratches will inevitably occur on the wafer, even after subsequent water polishing or polishing using abrasives. It is also unable to effectively reduce surface defects or slip formation on the epitaxial layer.

There are also previous technologies that control the etching solution to control the smoothing process, but it is easy to let the etching solution stay on the upper surface of the wafer for too long, making the shape of the wafer plane and the outer edge uncontrollable, which causes the deterioration of wafer flatness.

Accordingly, there is still a need for a method for improving the surface flatness of wafers and epitaxial layers.

The invention provides a method for improving the flatness of the surface of a silicon wafer. The method includes: sequentially wet-etching, grinding, and polishing a silicon wafer obtained by slicing a single-crystal silicon ingot; detecting the unevenness of the surface of the silicon wafer to be processed; According to the data of the unevenness condition, a temperature control distribution map is calculated and obtained; according to the distribution map, the silicon wafer is heated in zones and controlled in sections, and planarized by dry etching; the silicon wafer is polished; and on the surface of the silicon wafer An epitaxial layer is formed. The surface flatness of the entire epitaxial silicon wafer is measured. The nanotopogr _a phy of the flatness of the epitaxial silicon wafer is less than 25 nm.

In one embodiment, the dry etching is plasma etching.

In one embodiment, the etching gas used in the plasma etching includes CF ₄ , C ₂ F ₆ , SF ₆ , Cl ₂ and the like.

In one embodiment, the wet etching is an immersion double-sided etching.

In one embodiment, the wet etching solution is a mixed solution of hydrofluoric acid, nitric acid, phosphoric acid, and water.

In one embodiment, the surface unevenness of the silicon wafer is detected by a detection unit.

In one embodiment, the zone heating is performed by a zone resistance heater.

In one embodiment, the zone heating is performed by a micro-zone temperature control unit.

In one embodiment, the temperature of the silicon wafer is controlled at 120-480 ° C.

The method of the present invention can increase the smoothness of the surface of the silicon wafer. Therefore, when an epitaxial layer is grown on the surface of the silicon wafer by an epitaxial process, surface defects and slippage on the epitaxial layer during epitaxial growth can be reduced.

FIG. 1 is a flowchart of a method for improving surface flatness of an epitaxial wafer according to the present invention.

FIG. 2 is a flowchart of a method for improving the flatness of the surface of an epitaxial wafer according to an embodiment of the present invention.

The method of the present invention will be described in more detail below with reference to the schematic diagram, which shows the preferred embodiment of the present invention. It should be understood that those skilled in the art can modify the invention described herein while still realizing the invention. Beneficial effect. Therefore, the following description should be understood as a broad understanding of those skilled in the art, and not as a limitation on the present invention.

In the interest of clarity, not all features of an actual embodiment are described. In the following description, well-known functions and structures are not described in detail because they may confuse the present invention with unnecessary details. It should be considered that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another in accordance with system- or business-related restrictions. In addition, it should be considered that such development work may be complicated and time-consuming, but it is only routine work for those with ordinary knowledge in the art.

The invention is described more specifically in the following paragraphs by way of example with reference to the drawings. The advantages and features of the present invention will become clearer from the following description and the scope of patent application. It should be noted that the drawings are all in a very simplified form and all use inaccurate proportions, which are only used to facilitate and clearly explain the purpose of the embodiments of the present invention.

Please refer to FIG. 1. In this embodiment, a method for improving the flatness of the epitaxial layer of a silicon wafer is proposed, which includes the following steps: S101 sequentially wet-etch a slice of a thin circular plate-shaped single crystal silicon ingot. And polishing; S102 uses a detection unit to detect the unevenness of the surface of the silicon wafer to be processed; S103 calculates and obtains a temperature control distribution map based on the data of the unevenness; S104 heats and controls the temperature of the wafer with partition resistance according to the distribution map, and planarizes the wafer by dry etching; S105 polishes; and S106 forms an epitaxial layer on the surface of the wafer.

Moreover, in an embodiment, please refer to FIG. 2 to describe the method of the present invention in more detail.

First, a single crystal silicon ingot (S201) is provided, and steps such as grinding rounding, positioning edge or positioning V-groove, slicing, chamfering, double-side grinding, and single-side grinding (S202-S207) are sequentially performed to prepare a silicon wafer. . Next, the silicon wafer surface is mechanically damaged by dip-type double-side etching (S208), and double-side polishing (S209) and edge polishing (S210) are performed.

The surface roughness of the silicon wafer to be processed is detected by a detection unit, and the detection data is saved (S211). The detection unit can use, for example, Wafersight 2 (available from KLA-Tencor), LSW-3020FE (available from Kobelco), Nanometro 300TT -A (available from Kuroda), etc., detection data can be stored in memory. The data of the unevenness of the surface of the silicon wafer detected by the detection unit is received, and the distribution map of the temperature control of the wafer electrostatic chuck division and the etching time are calculated (S212).

Next, the silicon wafer substrate is heated by the electrostatic chuck partition control resistor, the wafer substrate temperature is controlled by the partition, and the silicon wafer is planarized by plasma etching (S213), so that the surface smoothness of the silicon wafer can be improved.

The above steps can be performed using a micro-zone temperature control unit. The micro-zone temperature control unit is composed of a Peltier device and / or an array of resistance heaters. The resistance heater may be a polyimide heater, Silicone heaters, mica heaters, metal heaters (such as tungsten, nickel / chromium alloys, molybdenum, tantalum, etc.), ceramic heaters (such as tungsten carbide), semiconductor heaters, carbon heaters, or any other suitable heating / Cooling element. The temperature control unit may incorporate different designs or configurations, such as screen printing heaters, wire wound heaters, etched foil heaters, or any other suitable design. Each zone of the micro-zone temperature control unit can independently control the temperature, and the range of the control circuit is 0-20W. The entire area of the micro-zone temperature control unit may be 90% to 120% of the area of the wafer substrate.

One-sided mirror polishing is performed on the silicon wafer after the plasma etching process (S214). Then, epitaxial growth can be performed on the surface of the silicon wafer after the above treatment (S215), which can effectively reduce surface defects and slippage on the epitaxial layer during epitaxial growth.

In the above embodiment, the wet etching is immersion double-sided etching, and the etching solution used is a mixed solution of hydrofluoric acid, nitric acid, phosphoric acid, and water.

In the above embodiment, the dry etching is plasma etching, and the etching gas used includes CF ₄ , C ₂ F ₆ , SF ₆ , Cl ₂ and the like.

Through the above steps of wet etching, zone heating and zone temperature control, and dry etching, the smoothness of the surface of the silicon wafer can be effectively improved. Therefore, when an epitaxial layer is grown on the surface of such a silicon wafer with better surface smoothness, the occurrence of surface defects and slippage of the epitaxial layer can be reduced, thereby improving subsequent device performance.

The content of the specific embodiments described above is used to describe the present invention in detail. However, these embodiments are only used for illustration and are not intended to limit the present invention. Those skilled in the art can understand that various changes or modifications made to the present invention without departing from the scope defined by the scope of the attached patent application fall into a part of the present invention.

Claims (8)

A method for improving the surface flatness of an epitaxial layer of a silicon wafer, comprising: sequentially wet-etching, grinding, and polishing a silicon wafer obtained by slicing a single crystal silicon ingot; detecting the unevenness of the surface of the silicon wafer to be processed; and according to the unevenness Based on the data, calculate and obtain a temperature control distribution map; according to the distribution map, heat and control the temperature of the silicon wafer in sections and planarize with dry etching; polish the silicon wafer; and form epitaxial wafers on the surface of the silicon wafer The surface flatness measurement is performed on the entire surface of the obtained epitaxial silicon wafer, and the nanotopography of the surface flatness of the epitaxial silicon wafer is less than 25 nm. For example, the method of claim 1, wherein the dry etching is plasma etching. For example, the method of claim 2 in the patent application range, wherein the plasma etching uses an etching gas including CF ₄ , C ₂ F ₆ , SF ₆ , and Cl ₂ . For example, the method of claim 1 in the patent application scope, wherein the wet etching is a dip-type double-sided etching. For example, the method of claim 1 in the scope of patent application, wherein the wet etching etching solution is a mixed solution of hydrofluoric acid, nitric acid, phosphoric acid, and water. For example, the method of claim 1 in the patent application range, wherein the surface unevenness of the silicon wafer is detected by a detection unit. For example, the method of claim 1 in the patent application range, wherein the zone heating is performed by a zone resistance heater. For example, the method of claim 1 in the patent scope, wherein the zone heating is performed by a micro zone temperature control unit.