TWI698864B - Semiconductor memory device - Google Patents

Abstract

The embodiment of the present invention provides a high-quality semiconductor memory device. The semiconductor memory device of the embodiment includes: a power supply pad; a first memory bank, which includes a plurality of memory cells; a second memory bank, which is sandwiched between the power supply pad and the first bank and includes a plurality of memory cells; 1 Wiring, which is connected to the power pad to supply power to the second memory bank; and the second wiring, which is connected to the power pad, passes through the second memory bank, does not supply power to the second memory bank, but supplies power to the first memory bank power supply.

Description

Semiconductor memory device

The embodiment is related to a semiconductor memory device.

MRAM (Magnetic Random Access Memory, Magnetic Random Access Memory) is a memory device that uses magnetic elements with magnetoresistive effect to store information in the memory cell. It is characterized by high-speed operation, large capacity, and non-volatility. The next generation of memory devices has attracted much attention. In addition, MRAM is being researched and developed as a substitute for volatile memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). In this case, to control the development cost and smooth replacement, it is ideal to make MRAM operate with the same specifications as DRAM and SRAM.

The embodiment of the present invention provides a high-quality semiconductor memory device.

The semiconductor memory device of the embodiment includes: a power supply pad; a first bank (bank) with a plurality of memory cells; a second bank, which is sandwiched between the power supply pad and the first bank, and with a plurality of memories The first wiring, which is connected to the power supply pad to supply power to the second memory bank; and the second wiring, which is connected to the power supply pad, passes through the second memory bank and does not supply power to the second memory bank, but to the first The storage body supplies power.

1: memory device

2: Memory controller

10a: core circuit

10b: Peripheral circuit

11: Memory area

12: Line decoder

13: Character line driver

14: column decoder

15: Instruction address input circuit

16: Controller

17: IO circuit

20a: Memory array

20b: sense amplifier/write driver

20c: page buffer

20d: Memory cell array

20e: Line 1 selection circuit

20f: Line 2 selection circuit

20g: read current sink

23a: NAND operation circuit

23b: NAND operation circuit

23c: NAND operation circuit

23d: NOR operation circuit

23e: inverter

23f: NAND operation circuit

23g: NAND operation circuit

23h: NAND operation circuit

23i: NMOS transistor

23j: PMOS transistor

23k: PMOS transistor

23l: NMOS transistor

23m: PMOS transistor

23n: PMOS transistor

23o: NMOS transistor

23p: NMOS transistor

24a: NAND operation circuit

24b: PMOS transistor

24c: inverter

24d: NOR operation circuit

24e: inverter

24f: NAND operation circuit

24g: PMOS transistor

24h: inverter

24i: NMOS transistor

24j: NMOS transistor

24k: NMOS transistor

24l: NMOS transistor

25a: NAND operation circuit

25b: PMOS transistor

25c: inverter

25d: NOR operation circuit

25e: inverter

25f: NAND operation circuit

25g: PMOS transistor

25h: inverter

25i: NMOS transistor

25j: NMOS transistor

25k: NMOS transistor

25l: NMOS transistor

25m: PMOS transistor

25n: PMOS transistor

30: MTJ element

31: Selective transistor

40: Potential drop detector

41: Potential generating circuit

42: Command system circuit

43: Stabilized capacitor

100a: Semiconductor substrate

100b: Semiconductor substrate

101a: impurity area

101b: impurity area

101c: impurity area

101d: impurity area

102: insulating film

103: gate electrode

104: contact plug

105: contact plug

106: Wiring layer

107: Contact plug

108: Wiring layer

109: insulating film

110: gate electrode

111: contact plug

112: Wiring layer

113: Contact plug

114: Wiring layer

115: contact plug

116: Wiring layer

200: readout circuit

210: preamplifier

220: sense amplifier

221: Transistor

223: Transistor

222: The first sample and hold circuit

224: The second sample and hold circuit

225: 2nd sense amplifier

230: write to drive

300a: Power supply circuit

300b: Power supply circuit

1st ML: first wiring layer

2nd ML: 2nd wiring layer

3rd ML: 3rd wiring layer

4th ML: 4th wiring layer

B: Tunnel barrier layer

BK0: Bank

BK1: memory bank

BL0~BLj-1: bit line

BWDATA: signal

C0: contact

C0_0: contact

C1_0~C1_x: contact

C2_0~C2_x: contact

C3_0~C3_x: contact

C4_0~C4_x: contact

C5_0~C5_x: contact

C6_0~C6_x: contact

C7_0~C7_x: contact

C10_0~C10_x: contact

C11_0~C11_x: contact

C20: Contact

C20_0: contact

C20_1: Contact

C21_0~C21_y: contact

C22_0~C22_y: Contact

C23_0-0~C23_0-z: Contact

C23_y-0~C23_y-z: Contact

C24_0~C24_y: contact

C25_0~C25_0: contact

C26_0-0~C26_0-z: Contact

C26_y-0~C26_y-z: Contact

C27_0-0~C27_0-z: Contact

C28_0~C28_z: Contact

C29_0~C29_z: Contact

CA: Command address signal

CK: clock signal

CKE: Clock enable signal

CS: Chip selection signal

CSL1: Line 1 selection signal

CSL1_0~CSL1_j-1: Line 1 selection signal

CSL2: Line 2 selection signal

CSL2_0~CSL2_j-1: Line 2 selection signal

D1: Direction

D2: Direction

D3: Direction

DO: Information

DOB: Information

DQ: data line

EN_1: signal

EN_2: signal

F: Recording layer (free layer)

GBL: Global bit line

GSL: Global source line

MC: memory cell

N1: Node

N2: Node

N11: Node

N12: Node

N13: Node

N14: Node

N15: Node

N16: Node

N17: Node

N18: Node

N19: Node

N20: Node

N21: Node

N22: Node

N32: Node

N33: Node

N34: Node

N35: Node

N36: Node

N42: Node

N43: Node

N44: Node

N45: Node

N46: Node

N47: Node

P: fixed layer (pinned layer)

PCHGOFF: pre-charge disconnect signal

PDV: power pad

PDV1: The first power pad

PDV2: 2nd power pad

R1: resistance element

SA: sense amplifier

SL: source line

SL0~SLj-1: source line

SL_0~SL_j-1: source line

T0: moment

T1: moment

T2: moment

T3: moment

T4: moment

T10: moment

T11: moment

T12: moment

T13: moment

T14: moment

T15: moment

T16: moment

T20: moment

T21: moment

T22: moment

T23: moment

T24: moment

T25: moment

T30: moment

T31: moment

T32: moment

T33: moment

T34: moment

T40: moment

T41: moment

T42: moment

T43: moment

T44: moment

T45: moment

T50: moment

T51: Moment

T52: moment

T53: moment

T54: moment

T55: moment

T60: moment

T61: moment

T62: moment

T63: Moment

T64: moment

T65: moment

VDD: voltage

VDD* ext: external voltage

VDD* int: internal voltage

VDL0: Power wiring

VDL0_0: Power supply wiring

VDL1_0~VDL1_x: power supply wiring

VDL2_0~VDL2_x: power wiring

VDL3: Power wiring

VDL4_0~VDL4_x: power wiring

VDL5_0~VDL5_x: power wiring

VDL6: Power wiring

VDL7_0~VDL7_x: power wiring

VDL20: Power wiring

VDL20_0: Power wiring

VDL20_1: Power wiring

VDL21_0~VDL21_y: power wiring

VDL22_0~VDL22_y: power wiring

VDL23_0~VDL23_y: power wiring

VDL24_0~VDL24_y: power wiring

VDL25_0~VDL25_z: power wiring

VDL26: Power wiring

VDL27_0~VDL27_z: power wiring

VDL28: Power wiring

VSS: voltage

Vwrt1: voltage

Vwrt2: voltage

WD: Write to drive

WDATA: signal

WEN: Signal

WEN1: signal

WEN2: Signal

WL: select character line

WL0~WLi-1: Character line

FIG. 1 is a block diagram showing the semiconductor memory device of the first embodiment.

FIG. 2 is a block diagram showing the memory bank of the semiconductor memory device of the first embodiment.

3 is a block diagram showing the memory cell MC of the semiconductor memory device of the first embodiment.

FIG. 4 is a block diagram showing the read circuit of the semiconductor memory device of the first embodiment.

Fig. 5 is a block diagram showing the read circuit of the semiconductor memory device of the first embodiment.

FIG. 6 is a layout diagram showing the wiring of power lines of the semiconductor memory device of the first embodiment.

Fig. 7 is a sectional view taken along the line A-A of Fig. 6;

Fig. 8 is a sectional view taken along the line B-B of Fig. 6;

FIG. 9 is a flowchart showing the read operation of the semiconductor memory device of the first embodiment.

10 is a waveform diagram showing the voltage waveform during the read operation of the semiconductor memory device of the first embodiment.

FIG. 11 is a diagram showing the layout of the power line wiring of the semiconductor memory device of the comparative example of the first embodiment.

Fig. 12 is a diagram showing the read operation of the semiconductor memory device of the first embodiment.

FIG. 13 is a waveform diagram showing the voltage waveform during the read operation of the semiconductor memory device of the comparative example of the first embodiment.

14 is a waveform diagram showing the voltage waveform during the read operation of the semiconductor memory device of the comparative example of the first embodiment.

FIG. 15 is a layout diagram showing the wiring of the power supply line of the semiconductor memory device of Modification 1 of the first embodiment.

FIG. 16 is a layout diagram showing the wiring of the power supply line of the semiconductor memory device of Modification 2 of the first embodiment.

FIG. 17 shows the layout of the power supply lines of the semiconductor memory device in the modification 3 of the first embodiment Line layout diagram.

FIG. 18 is a layout diagram showing the wiring of the power supply line of the semiconductor memory device of Modification 4 of the first embodiment.

FIG. 19 is a layout diagram showing the wiring of the power supply line of the semiconductor memory device of Modification 5 of the first embodiment.

FIG. 20 is a layout diagram showing the wiring of power lines of the semiconductor memory device of the second embodiment.

Fig. 21 is a cross-sectional view taken along the line C-C of Fig. 20;

Fig. 22 is a cross-sectional view taken along the line D-D of Fig. 20;

FIG. 23 is a layout diagram showing the wiring of the power supply line of the semiconductor memory device of Modification 1 of the second embodiment.

FIG. 24 is a layout diagram showing the wiring of the power supply line of the semiconductor memory device of Modification 2 of the second embodiment.

FIG. 25 is a layout diagram showing the wiring of the power line of the semiconductor memory device of Modification 3 of the second embodiment.

FIG. 26 is a layout diagram showing the wiring of the power supply line of the semiconductor memory device of Modification 4 of the second embodiment.

FIG. 27 is a layout diagram showing the wiring of the power supply line of the semiconductor memory device of Modification 5 of the second embodiment.

FIG. 28 is a block diagram showing the controller of the semiconductor memory device of the third embodiment.

FIG. 29 is a waveform diagram showing the waveform of the read operation (normal time) of the semiconductor memory device of the third embodiment.

Fig. 30 shows the read operation of the semiconductor memory device of the third embodiment (at the time of instantaneous stop) The waveform of the waveform.

FIG. 31 is a block diagram showing the sense amplifier/write driver of the semiconductor memory device of the fourth embodiment.

32 is a circuit diagram showing the relationship between the memory array and the write driver of the semiconductor memory device of the fourth embodiment.

FIG. 33 is a circuit diagram showing the write driver of the semiconductor memory device of the fourth embodiment.

FIG. 34 is a waveform diagram showing waveforms in the write operation of the semiconductor memory device of the fourth embodiment.

35 is a circuit diagram of a write driver of a semiconductor memory device of a comparative example of the fourth embodiment.

FIG. 36 is a waveform diagram showing waveforms in the write operation of the semiconductor memory device of the comparative example of the fourth embodiment.

Fig. 37 is a circuit diagram showing a write driver of a semiconductor memory device according to a modification of the fourth embodiment.

FIG. 38 is a waveform diagram showing waveforms in the write operation of the semiconductor memory device according to a modification of the fourth embodiment.

FIG. 39 is a waveform diagram showing a waveform when the voltages of the bit line BL and the source line SL related to the fourth embodiment are floated during the period when the write operation and the read operation are not performed.

FIG. 40 is a waveform diagram showing a waveform when the voltages of the bit line BL and the source line SL related to the fourth embodiment are floated during the period when the write operation and the read operation are not performed.

FIG. 41 is a waveform diagram showing waveforms when the voltages of the bit line BL and the source line SL related to the fourth embodiment are floated during the period when the write operation and the read operation are not performed.

Hereinafter, the constructed embodiment will be described with reference to the drawings. In addition, in the following description, components having substantially the same function and configuration are denoted with the same reference numerals. The "_number" after the number constituting the reference symbol is used to distinguish the elements with the same composition by reference to the reference symbol containing the same number. When there is no need to distinguish the elements represented by the reference signs containing the same numbers from each other, these elements are referred to by reference signs containing only numbers. For example, when there is no need to distinguish the elements with the reference signs 10_1 and 10_2 from each other, the above elements are referred to as the reference sign 10 in general.

The diagram is a model diagram. It should be noted that the relationship between the thickness and the plane size, the ratio of the thickness of each layer, etc. are different from the actual product. Therefore, the specific thickness or size should be judged with reference to the following description. Moreover, of course, the drawings also include parts with different dimensional relationships or ratios.

In addition, in this specification, for convenience of explanation, an XYZ orthogonal coordinate system is introduced. In this coordinate system, two directions parallel to the upper surface of the semiconductor substrate and orthogonal to each other are referred to as the X direction (D1) and the Y direction (D2), and the directions orthogonal to both the X direction and the Y direction, That is, the stacking direction of each layer is set to the Z direction (D3).

<1> The first embodiment

<1-1> Composition

<1-1-1> Semiconductor memory device

First, the basic configuration of the semiconductor memory device of the first embodiment will be briefly described using FIG. 1.

The semiconductor memory device 1 of the first embodiment includes a core circuit 10a and a peripheral circuit 10b.

The core circuit 10a includes a memory area 11, a row decoder 12, a word line driver 13, and a column decoder 14. The memory area 11 includes a plurality of memory banks BK (in the example of FIG. 1, two memory banks BK0 and Bk1). For example, the banks BK0 and BK1 can be activated independently. Furthermore, Yu Wu When the banks BK0 and BK1 need to be distinguished, they are simply called bank BK. The details of the bank BK will be described below.

The row decoder 12 recognizes the command or address based on the command address signal CA based on the external control signal, and controls the selection of the bit line BL and the source line SL.

The word line driver 13 is arranged along at least one side of the bank BK. In addition, the word line driver 13 is configured to apply a voltage to the selected word line WL via the main word line MWL during data reading or data writing.

The column decoder 14 decodes the address of the command address signal CA supplied from the command address input circuit 15. More specifically, the column decoder 14 supplies the decoded column address to the word line driver 13. Thereby, the word line driver 13 can apply a voltage to the selected word line WL.

The peripheral circuit 10b includes a command address input circuit 15, a controller 16, and an IO circuit 17.

The memory controller (also referred to as the host device) 2 inputs various external control signals, such as the chip selection signal CS, the clock signal CK, the clock enable signal CKE, and the command address signal CA, to the command address input circuit 15. The command address input circuit 15 transmits the command address signal CA to the controller 16.

The controller 16 recognizes the command and the address. The controller 16 controls the semiconductor memory device 1.

The IO circuit 17 temporarily stores input data input from the memory controller 2 via the data line DQ or output data read from the selected memory bank. The input data is written into the memory cell of the selected memory bank.

<1-1-2> Bank BK

The basic structure of the memory bank BK of the semiconductor memory device of the first embodiment will be schematically described using FIG. 2.

Bank BK is equipped with memory array 20a, sense amplifier/write driver (SA/WD) 20b, and page buffer 20c.

The memory array 20a is composed of a plurality of memory cells MC arranged in a matrix. A plurality of word lines WL0~WLi-1 (i is an integer greater than 2), a plurality of bit lines BL0~BLj-1 (j is an integer greater than 2), and a plurality of sources are arranged in the memory array 20a Polar lines SL0~SLj-1. A row of the memory array 20a is connected to a word line WL, and a row of the memory array 20a is connected to a pair including a bit line BL and a source line SL.

The memory cell MC is composed of a magnetoresistance effect element (MTJ (Magnetic Tunnel Junction) element) 30 and a selective transistor 31. The selection transistor 31 is composed of, for example, an N-channel MOSFET (METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR, metal oxide semiconductor field effect transistor).

One end of the MTJ element 30 is connected to the bit line BL, and the other end is connected to the drain (source) of the selection transistor 31. The gate of the selection transistor 31 is connected to the word line WL, and the source (drain) is connected to the source line SL.

The sense amplifier/write driver 20b is arranged in the bit line direction of the memory array 20a. The sense amplifier/write driver 20b includes a sense amplifier and a write driver. By detecting the current flowing through the memory cell MC connected to the bit line BL via the global bit line GBL and to the selected word line WL via the main word line MWL, the data stored in the memory cell is read. The write driver is connected to the bit line BL via the global bit line GBL by passing current or connected to the source line SL via the global source line GSL and connected to the memory cell of the selected word line WL via the main word line MWL MC writes data. Next, the sense amplifier/write driver 20b controls the bit line BL and the source line SL based on the control signal from the controller 16. The data transfer between the sense amplifier/write driver 20b and the data line DQ is performed via the IO circuit 17.

The page buffer 20c temporarily stores the data read from the memory array 20a or controls it from the memory Write data received by controller 2. When writing data to the memory array 20a, it is performed in a plurality of memory cell units (page units). The unit written into the memory array 20a at one time as described above is called "page". In addition, the page buffer 20c of this embodiment is provided in each bank BK, and has a memory capacity that can temporarily store data of all pages of the bank BK.

Furthermore, the configuration of the above-mentioned bank BK is an example, and the bank BK may have other configurations.

<1-1-3> Memory cell MC

Next, the structure of the memory cell MC of the semiconductor memory device of the first embodiment will be briefly described using FIG. 3. As shown in FIG. 3, one end of the MTJ element 30 of the memory cell MC of the first embodiment is connected to the bit line BL, and the other end is connected to one end of the selection transistor 31. In addition, the other end of the selection transistor 31 is connected to the source line SL. The MTJ element 30 that utilizes the TMR (tunneling magnetoresistive) effect has a multilayer structure including two ferromagnetic layers F, P and a non-magnetic layer (tunneling insulating film) B sandwiched between them, and uses The change of magnetoresistance based on the spin-bias tunneling effect memorizes digital data. The MTJ element 30 can obtain a low resistance state and a high resistance state by the magnetization arrangement of the two ferromagnetic layers F and P. For example, if the low resistance state is defined as data “0” and the high resistance state is defined as data “1”, then 1-bit data can be recorded in the MTJ element 30. Of course, the low resistance state can also be defined as the data "1", and the high resistance state can be defined as the data "0".

For example, the MTJ element 30 is configured by stacking a fixed layer (pinning layer) P, a tunnel barrier layer B, and a recording layer (free layer) F in this order. The pinning layer P and the free layer F are made of ferromagnetic material, and the tunnel barrier layer B includes an insulating film (for example, Al ₂ O ₃ , MgO). The pinned layer P is a layer in which the direction of the magnetization arrangement is fixed. The direction of the magnetization arrangement of the free layer F is variable, and data is stored according to the direction of its magnetization.

If current flows in the direction of arrow A1 during writing, it is relative to the direction of magnetization of the pinned layer P In other words, the direction of magnetization of the free layer F becomes the antiparallel state (AP state) and becomes the high resistance state (data "1"). If current flows in the direction of arrow A2 during writing, the directions of magnetization of the pinned layer P and the free layer F become parallel (P state) and become a low resistance state (data "0"). In this way, the TMJ device can write different data according to the direction of current flow.

<1-1-4> Sense amplifier/write driver

The sense amplifier/write driver 20b of the semiconductor memory device of the first embodiment will be described with reference to FIG. 4. FIG.

As shown in FIG. 4, the sense amplifier/write driver 20b includes a plurality of readout circuits 200. A plurality of readout circuits 200 are provided on each global bit line. In addition, each of the plurality of readout circuits 200 includes a preamplifier 210 and a sense amplifier (SA) 220.

The preamplifier 210 supplies current (cell current) to the memory cell MC via the global bit line and the bit line, and generates voltages V1st and V2nd based on the power supply current.

The sense amplifier 220 determines data (DO, DOB) based on the voltages V1st and V2nd generated by the preamplifier 210.

Furthermore, the preamplifier 210 and the sense amplifier 220 operate based on the voltages VDD and VSS applied via pads not shown.

A more specific example of the sense amplifier/write driver 20b of the semiconductor memory device of the first embodiment will be described with reference to FIG. 5. FIG. In addition, the structure of the sense amplifier/write driver 20b is not limited to this.

As shown in FIG. 5, the write driver (WD) 230 of the sense amplifier/write driver 20b is connected to the bit line and the source line (BL and SL are collectively referred to as the cell path).

The read circuit 200 includes, for example, transistors 221 and 223, a first sample and hold circuit 222, and a second sample and hold circuit 224. In addition, the sense amplifier 220 in FIG. 4 corresponds to the second sense amplifier 225.

The first sample-and-hold circuit 222 holds the voltage obtained by the preamplifier 210 during the first readout operation (details will be described later).

The second sample-and-hold circuit 224 holds the voltage obtained by the preamplifier 210 during the second read operation (details will be described later).

The second sense amplifier 225 outputs the data DO based on the output voltage V1st from the first sample and hold circuit 222 and the output voltage V2nd from the first sample and hold circuit 224. The second sense amplifier 225 determines data based on the first read operation and the second read operation as described below. When the second sense amplifier 225 reads "0" data in the first read operation and reads "0" data in the second read operation, in order to accurately determine the "0" data, perform the data judgment Set the offset (offset) to make the judgment.

<1-1-5>Layout

<1-1-5-1> Wiring layout

The power supply wiring layout of the semiconductor memory device of the first embodiment will be described using FIG. 6. Here, for the sake of simple description, the pads supplying the voltage VDD, the wiring supplying the voltage VDD, the memory array 20a, and the sense amplifier/write driver 20b are shown.

As shown in FIG. 6, a bank BK0 is provided adjacent to the power pad PDV of the supply voltage VDD in the direction D2. The bank BK0 is sandwiched between the power pad PDV and the bank BK1 in the D2 direction. That is, the memory bank BK0 is arranged close to the power pad PDV, and the memory bank BK1 is arranged away from the power pad PDV.

The power pad PDV supplies the voltage VDD to the sense amplifier/write driver 20b via the power supply wiring VDL.

The power supply wiring VDL of the sense amplifier/write driver 20b connected to the bank BK0 will be described.

The power supply pad PDV is connected to the power supply wiring VDL0 via the contact C0.

The power supply wiring VDL0 extends in the D1 direction. The power supply wiring VDL0 is connected to the power supply wiring VDL1_0 to VDL1_x via the contacts C1_0 to C1_x (x is an integer), respectively.

The power supply wiring lines VDL1_0 to VDL1_x extend in the D2 direction. The power supply wiring VDL1_0~VDL1_x are connected to the power supply wiring VDL3 via the contacts C3_0~C3_x.

The power supply wiring VDL3 extends in the D1 direction. The power supply wiring VDL3 is connected to the sense amplifier/write driver 20b of the bank BK0 via a contact point not shown.

The power supply wiring VDL connected to the sense amplifier/write driver 20b of the bank BK1 will be described.

The power supply wiring VDL0 is connected to the power supply wiring VDL2_0 to VDL2_x via the contacts C2_0 to C2_x, respectively.

The power lines VDL2_0 to VDL2_x are not connected to the bank BK0, but extend in the direction D2 in a manner of being connected to the sense amplifier/write driver 20b of the bank BK1. The power supply wiring VDL2_0~VDL2_x are connected to the power supply wiring VDL6 via the contacts C7_0~C7_x.

The power supply wiring VDL6 extends in the D1 direction. The power supply line VDL6 is connected to the sense amplifier/write driver 20b of the bank BK1 via a contact point not shown.

The power supply wiring VDL2_0~VDL2_x are respectively connected to the power supply wiring VDL4_0~VDL4_x via the contacts C4_0~C4_x.

The power supply wiring lines VDL4_0 to VDL4_x extend in the D1 direction. The power supply wiring VDL4_0~VDL4_x are respectively connected to the power supply wiring VDL5_0~VDL5_x via the contacts C5_0~C5_x.

The power supply wiring lines VDL5_0 to VDL5_x extend in the D2 direction. The power supply wiring VDL5_0~VDL5_x are connected to the power supply wiring VDL6 via the contacts C6_0~C6_x.

<1-1-5-2>A-A section

The A-A cross section of Fig. 6 will be described using Fig. 7. Here, for the sake of simple description, the insulating layer covering each wiring is not shown. In addition, a structure that is not shown in the figure in the A-A section is indicated by a broken line.

First, the memory array 20a of the block BK0 will be described. As described above, the memory array 20a of the block BK0 has a plurality of memory cells. Here, for simple description, only one memory cell of the memory array 20a arranged in the block BK0 is shown.

Specifically, impurity regions 101a and 101b are provided in the front area of the semiconductor substrate 100a. Next, a channel region (not shown) is provided in the front region of the semiconductor substrate 100a and sandwiched between the impurity regions 101a and 101b. Next, an insulating film 102 is disposed above the channel region, and a control gate electrode 103 (word line WL) is disposed on the insulating film 102. In this way, the selection transistor 31 is composed of the impurity regions 101a and 101b, the channel region, the insulating film 102, and the control gate electrode 103.

In addition, the layer provided on the word line WL is described as the first wiring layer (1st ML).

A contact 104 including a conductor is provided on the impurity region 101a, and an MTJ element 30 is provided on the contact 104. A contact 105 containing a conductor is disposed on the MTJ element 30, and a wiring layer 106 (bit line BL) containing a conductor extending in the direction D2 is disposed on the contact 105. In addition, a contact 107 containing a conductor is provided on the impurity region 101b, and a wiring layer (source line SL) containing a conductor extending in the D2 direction is provided on the contact 107. In this way, the memory cell MC is composed of the selection transistor 31, the contact 104, the MTJ element 30, the contact 105, and the contact 107.

In addition, the layer provided with the bit line BL and the source line SL is referred to as a second wiring layer (2nd ML). The second wiring layer is located higher than the first wiring layer in the D3 direction.

A wiring layer 108 (main word line MWL) extending in the D1 direction is provided above the wiring layer 106.

In addition, the layer provided with the main character line MWL is described as the third wiring layer (3rd ML). Match 3 The wire layer is located higher than the second wiring layer in the D3 direction.

Here, for the sake of simple description, one memory cell MC is described. However, the memory array 20a of the block BK0 is provided with a plurality of memory cells MC as described above.

Next, the sense amplifier/write driver 20b of the block BK0 will be described. Here, for the sake of simple description, only one transistor of the sense amplifier/write driver 20b provided in the block BK0 is shown.

Specifically, impurity regions 101c and 101d are provided in the front area of the semiconductor substrate 100a. Next, a channel region (not shown) is provided in the front region of the semiconductor substrate 100a and sandwiched between the impurity regions 101c and 101d. Next, an insulating film 109 is disposed above the channel region, and a control gate electrode 110 is disposed on the insulating film 109. In this way, the transistor is composed of the impurity regions 101c and 101d, the channel region, the insulating film 109, and the control gate electrode 110.

A contact 111 containing a conductor is provided on the impurity region 101c, and a wiring layer 112 containing a conductor is provided on the contact 111. The wiring layer 112 is located in the second wiring layer. A contact 113 containing a conductor is provided on the wiring layer 112, and a wiring layer 114 containing a conductor is provided on the contact 113. The wiring layer 114 is located in the third wiring layer. A contact 115 containing a conductor is provided on the wiring layer 114, and a wiring layer 116 containing a conductor (power supply wiring VDL1) extending in the D2 direction is provided on the contact 115.

In addition, the layer provided with the power supply wiring VDL1 is referred to as the fourth wiring layer (4th ML). The fourth wiring layer is located higher than the third wiring layer in the D3 direction.

The memory array 20a and the sense amplifier/write driver 20b of the block BK0 are described above.

The memory array 20a and the sense amplifier/write driver 20b of the block BK1 also have the same structure.

If the semiconductor substrate 100a in the above description is replaced with the semiconductor substrate 100b, the wiring Layer 116 (power supply wiring VDL1) is replaced with wiring layer 116 (power supply wiring VDL5), which becomes the description of the memory array 20a and sense amplifier/write driver 20b of block BK1.

As shown in FIGS. 6 and 7, although the power supply wiring VDL1 and the power supply wiring VDL5 are electrically connected to the power supply wiring VDL0, they are not directly connected.

<1-1-5-3>B-B section

The B-B section of Fig. 6 will be described using Fig. 8. Here, for the sake of simple description, the insulating layer covering each wiring is not shown. In addition, a broken line in the B-B cross-section indicates a structure that is not originally shown.

The basic description of the block BK0 and the block BK1 is substantially the same as that described in FIG. 7. The difference between FIG. 7 and FIG. 8 is that although the wiring layer 116 (power wiring VDL2) passes above the block BK0, it is not directly connected to the block BK0.

As shown in Figures 6 to 8, the power supply wiring connected to the bank BK0 and the power supply wiring connected to the bank BK1 are connected near the power pad PDV. Therefore, the noise generated by the sense amplifier/write driver 20b of the bank BK0 is absorbed by the power pad PDV, and will not affect the sense amplifier/write driver 20b of the bank BK1. Similarly, the noise generated by the sense amplifier/write driver 20b of the bank BK1 is absorbed by the power pad PDV and will not affect the sense amplifier/write driver 20b of the bank BK0.

In addition, the memory bank BK1 is farther from the power pad PDV than the memory bank BK0. Therefore, in order that the voltage supplied to the bank BK1 will not be lower than the voltage supplied to the bank BK0, the number of power supply wirings connected to the bank BK1 is twice the number of power supply wirings connected to the bank BK0 . In the first embodiment, for the sake of simple description, the number of power supply wirings connected to the bank BK1 is set to twice the number of power supply wirings connected to the bank BK0. However, as long as the number of power supply wires connected to the bank BK1 is more than the number of power supply wires connected to the bank BK0.

<1-2> Action

As described above, the MTJ element of the semiconductor memory device of the first embodiment uses the change in resistance value to store data. When the semiconductor memory device reads the information stored in the MTJ element, the MTJ element flows a read current (also referred to as a cell current). Next, the semiconductor memory device converts the resistance value of the MTJ element into a current value or a voltage value, and compares it with the reference value to determine the resistance state.

However, if the resistance difference of the MTJ element increases, the interval between the resistance value distributions in the "0" state and the "1" state may become narrower. Therefore, in the readout method in which the reference value is set within the range of the resistance value distribution and the state of the MTJ element is determined based on the magnitude relative to the reference value, the readout margin is significantly reduced.

Therefore, in view of this phenomenon, as a reading method, there is a self-reference reading method that overwrites its own data to generate a reference signal, and reads the data based on the generated signal.

In the following embodiments, the read operation of the semiconductor memory device when the self-reference read method is used as the read method will be described.

<1-2-1> Outline of Reading Action

The outline of the read operation of the memory system of the first embodiment will be described using FIG. 9. Furthermore, in this description, refer to FIGS. 4 and 5.

[Step S1001]

The memory controller 2 issues an activation command and a read command to the semiconductor memory device 1.

When the semiconductor memory device 1 receives an activation command and a read command from the memory controller 2, it performs a first read operation (1st READ) on the memory cell to be read. The readout circuit 200 memorizes the resistance state of the read target memory cell as voltage information (signal voltage) V1st through the first readout operation.

[Step S1002]

The semiconductor memory device 1 performs a "0" write operation (WRITE "0") on the memory cell that is the target of the first read operation. Thereby, the memory cell that becomes the target of the first read operation is overwritten with "0" data. In order to generate the following V2nd, this action sets the memory cell to the reference state (here set to "0"). That is, this writing operation may also be described as a standardization operation.

[Step S1003]

The semiconductor memory device 1 performs a second read operation (2nd READ) on the memory cell that is the target of the first read operation. The reading circuit 200 generates voltage information (signal voltage) V2nd by this second reading operation.

[Step S1004]

The readout circuit 200 determines the result of V1st generated in step S1001 based on V2nd generated in step S1003. Specifically, the readout circuit 200 determines the data stored in the memory cell by comparing V1st and V2nd.

Furthermore, the controller 16 writes the data back to the memory cell after determining the data stored in the memory cell. In this way, the data stored in the memory cell at the beginning can be returned to the memory cell.

<1-2-2> Voltage waveform

The waveform of the voltage during the read operation will be described using FIG. 10.

As shown in FIG. 10, when the semiconductor memory device 1 performs the first read operation, the first read result is stored in the first sample and hold circuit 222, and the voltage of V1st rises (time T0 to time T1).

The semiconductor memory device 1 performs a "0" write operation (time T1 to time T2) after the first read operation.

The semiconductor memory device 1 stores the second read result in the second sample-and-hold circuit 224, and the voltage of V2nd rises (time T2 to time T3).

The second sense amplifier 225 performs data determination based on the voltages V1st and V2nd (time T4).

As described above, in the read operation of the memory system of the first embodiment, data is judged by performing the read operation twice.

<1-3> Effect

According to the above embodiment, the power supply wiring connected to the bank BK0 and the power supply wiring connected to the bank BK1 are connected in the vicinity of the power pad PDV. Therefore, the noise generated by the sense amplifier/write driver 20b of the bank BK0 or the bank BK1 is absorbed by the power pad PDV and will not affect the sense amplifier/write driver 20b of the other bank BK.

Here, in order to make the effect of the first embodiment easy to understand, a comparative example will be described.

The power wiring layout of the semiconductor memory device of the comparative example will be described using FIG. 11. Here, for the sake of simple description, the pad for supplying voltage VDD, the wiring for supplying voltage VDD, the memory array and the sense amplifier/write driver 20b are shown.

As shown in FIG. 11, the power supply wiring lines VDL7_0 to VDL7_x extend in the D2 direction. The power supply wiring VDL7_0~VDL7_x are connected to the power supply wiring VDL3 via the contacts C3_0~C3_x. In addition, power supply wiring VDL7_0 to VDL7_x are connected to power supply wiring VDL6 via contacts C6_0 to C6_x.

In this way, in the semiconductor memory device of the comparative example, the power wiring connected to the bank BK0 and the power wiring connected to the bank BK1 are shared.

However, in the semiconductor memory device, different banks BK may operate at the same time.

For example, as shown in FIG. 12, there is a case where the timing of the second read operation for bank BK0 and the first read operation for bank BK1 overlap.

In this case, during the operation of the bank BK0, the bank BK1 may generate noise. Similarly, during the operation of the bank BK1, the bank BK0 may generate noise.

Here, in the read operation, the waveform when the noise from the adjacent memory bank is received will be described.

FIG. 13 shows the waveform when the adjacent bank is activated in the first read operation.

As shown in Figure 13, when the adjacent memory bank is activated in the first read operation, as surrounded by the dotted line in the figure, the voltage value will be stored in the sample and hold when V1st is still low. The situation of circuit 222. In this case, the second sense amplifier 225 may not be able to properly determine the data.

FIG. 14 shows the waveform when the adjacent bank is activated in the second read operation.

As shown in Figure 14, when the adjacent memory bank is activated in the second readout operation, as surrounded by the dotted line in the figure, the voltage value will be stored in the sample and hold when V2nd is still low. The situation of circuit 224. In this case, the second sense amplifier 225 may not be able to properly determine the data.

As described above, in the semiconductor memory device of the comparative example, the data may not be correctly determined due to the influence of adjacent memory banks.

As described above, in the semiconductor memory device, in order to read data from the memory cell, two read operations are performed. Therefore, it is preferable that the first readout operation and the second readout operation operate in the same operating environment.

However, once any one of the first read operation or the second read operation is affected by noise generated by another adjacent memory bank, the data may not be properly read.

Therefore, in the semiconductor memory device of the above embodiment, the power supply wiring connected to the bank BK0 and the power supply wiring connected to the bank BK1 are connected in the vicinity of the power pad PDV. power supply The pad PDV can absorb noise, so the power noise generated by the memory bank BK will not affect another adjacent memory bank BK. Therefore, even if the operation shown in FIG. 12 is performed, the read operation can be performed well.

<1-4> Examples of changes

<1-4-1> Variation example 1

The power supply wiring layout of the semiconductor memory device of Modification 1 of the first embodiment will be described using FIG. 15.

The difference between the power wiring layout of the semiconductor memory device of the first embodiment and the power wiring layout of the semiconductor memory device of the first embodiment is that a power supply circuit 300 is further added.

Specifically, as shown in FIG. 15, a power supply circuit 300a is provided between the power supply wiring VDL0 and the power supply wiring VDL1. In addition, a power supply circuit 300b is provided between the power supply wiring VDL0 and the power supply wiring VDL2.

The power supply circuit 300a may have any configuration as long as it can transmit the power supply voltage from the power supply wiring VDL0 to the power supply wiring VDL1. The same applies to the power supply circuit 300b, as long as the power supply voltage can be transmitted from the power supply wiring VDL0 to the power supply wiring VDL2, any structure may be used.

<1-4-2> Variation 2

The power supply wiring layout of the semiconductor memory device of Modification 2 of the first embodiment will be described using FIG. 16.

It can also be the layout shown in Figure 16. In FIG. 15, one power supply line VDL1 is connected to one power supply circuit 300a. However, as shown in FIG. 16, a plurality of power supply wiring lines VDL1 may be connected to one power supply circuit 300a. Similarly, as shown in Figure 16, a plurality of The source wiring VDL2 is connected to one power supply circuit 300b.

<1-4-3> Variation 3

The power supply wiring layout of the semiconductor memory device of Modification 3 of the first embodiment will be described using FIG. 17.

The difference between the power supply wiring layout of the semiconductor memory device of the first embodiment and the power supply wiring layout of the semiconductor memory device of the first embodiment is that the power supply pad for bank BK0 and the power supply pad for bank BK1 are used. Electric separation.

As shown in FIG. 17, the first power supply pad PDV1 supplies the voltage VDD to the sense amplifier/write driver 20b of the bank BK0 via the power supply wiring VDL.

The first power supply pad PDV1 is connected to the power supply wiring VDL0_0 via the contact C0_0.

The power supply wiring VDL0_0 extends in the D1 direction. The power supply wiring VDL0_0 is connected to the power supply wiring VDL1_0 to VDL1_x via the contacts C10_0 to C10_x, respectively.

Furthermore, as shown in FIG. 17, the second power pad PDV2 supplies the voltage VDD to the sense amplifier/write driver 20b of the bank BK1 via the power supply wiring VDL.

The second power supply pad PDV2 is connected to the power supply wiring VDL0_1 via the contact C0_1.

The power supply wiring VDL0_1 extends in the D1 direction. The power supply wiring VDL0_1 is connected to the power supply wiring VDL2_0 to VDL2_x via the contacts C11_0 to C11_x, respectively.

<1-4-4> Variation 4

The power supply wiring layout of the semiconductor memory device of Modification 4 of the first embodiment will be described using FIG. 18.

The difference between the power supply wiring layout of the semiconductor memory device in the modification 4 of the first embodiment and the power wiring layout of the semiconductor memory device in the modification 3 of the first embodiment is that a power supply circuit 300 is further added.

Specifically, as shown in FIG. 18, a power supply circuit 300a is provided between the power supply wiring VDL0_0 and the power supply wiring VDL1. In addition, a power supply circuit 300b is provided between the power supply wiring VDL0_1 and the power supply wiring VDL2.

The power supply circuit 300a may have any structure as long as it can transmit the power supply voltage from the power supply wiring VDL0_0 to the power supply wiring VDL1. The same applies to the power supply circuit 300b, as long as the power supply voltage can be transmitted from the power supply wiring VDL0_1 to the power supply wiring VDL2, any structure may be adopted.

<1-4-5> Variation example 5

The power supply wiring layout of the semiconductor memory device of Modification 5 of the first embodiment will be described using FIG. 19.

It may also have a layout as shown in Figure 19. In FIG. 18, one power supply line VDL1 is connected to one power supply circuit 300a. However, as shown in FIG. 19, a plurality of power supply lines VDL1 may be connected to one power supply circuit 300a. Similarly, as shown in FIG. 19, a plurality of power supply lines VDL2 may be connected to one power supply circuit 300b.

<2> The second embodiment

The second embodiment will be described. In the second embodiment, another example of the power supply wiring layout of the semiconductor memory device will be described. Furthermore, the basic structure and basic operation of the semiconductor memory device of the second embodiment are the same as those of the semiconductor memory device of the first embodiment described above. Therefore, descriptions about matters already explained in the above-mentioned first embodiment and matters that can be easily analogized based on the above-mentioned first embodiment are omitted.

<2-1>Layout

<2-1-1> Wiring layout

Use FIG. 20 to describe the power wiring layout of the semiconductor memory device of the second embodiment Bright. Here, for the sake of simple description, the pads supplying the voltage VDD, the wiring supplying the voltage VDD, the memory array 20a, and the sense amplifier/write driver 20b are shown.

As shown in FIG. 20, the memory bank BK0 is provided adjacent to the power pad PDV of the supply voltage VDD in the direction D2. The bank BK0 is sandwiched between the power pad PDV and the bank BK1 in the D1 direction. That is, the memory bank BK0 is arranged close to the power pad PDV, and the memory bank BK1 is arranged away from the power pad PDV.

The power pad PDV supplies the voltage VDD to the sense amplifier/write driver 20b via the power supply wiring VDL.

The power supply wiring VDL of the sense amplifier/write driver 20b connected to the bank BK0 will be described.

The power supply pad PDV is connected to the power supply wiring VDL20 via the contact C20.

The power supply wiring VDL20 extends in the D2 direction. The power supply wiring VDL20 is connected to the power supply wiring VDL21_0 to VDL21_y via contacts C21_0 to C21_y (y is an integer), respectively.

The power supply wiring lines VDL21_0 to VDL21_y extend in the D1 direction. The power supply wiring VDL21_0 is connected to the power supply wiring VDL25_0 to VDL25_z via the contacts C23_0-0 to C23_0-z (z is an integer). Similarly, the power supply wiring VDL21_y is connected to the power supply wiring VDL25_0 to VDL25_z via the contacts C23_y-0 to C23_y-z. Furthermore, it is preferable that at least one of the power supply wiring lines VDL21_0 to VDL21_y is provided on the sense amplifier/write driver 20b. In this example, the power supply wiring VDL21_y is provided on the sense amplifier/write driver 20b.

The power supply wiring lines VDL25_0 to VDL25_z extend in the D2 direction. The power supply wiring VDL25_0 to VDL25_z are connected to the power supply wiring VDL26 via the contacts C28_0 to C28_z.

The power supply wiring VDL26 extends in the D1 direction. The power supply wiring VDL26 is connected to the sense amplifier/write driver 20b of the bank BK0 through a contact not shown.

The power supply wiring VDL connected to the sense amplifier/write driver 20b of the bank BK1 will be described.

The power supply wiring VDL20 is connected to the power supply wiring VDL22_0 to VDL22_y via the contact points C22_0 to C22_y, respectively.

The power supply wiring lines VDL22_0 to VDL22_y extend in the direction D1 so as not to be connected to the bank BK0 but to the bank BK1. The power supply wiring VDL22_0 is connected to the power supply wiring VDL27_0 to VDL27_z via the contacts C27_0-0 to C27_0-z. Similarly, the power supply wiring VDL22_y is connected to the power supply wiring VDL27_0 to VDL27_z via the contacts C27_y-0 to C27_y-z. Moreover, it is preferable that at least one of the power supply wiring lines VDL22_0 to VDL22_y is provided on the sense amplifier/write driver 20b. In this example, the power supply wiring VDL22_y is provided on the sense amplifier/write driver 20b.

The power supply wiring lines VDL27_0 to VDL27_z extend in the D2 direction. The power supply wiring VDL27_0 to VDL27_z are connected to the power supply wiring VDL28 via the contacts C29_0 to C29_z.

The power supply wiring VDL28 extends in the D1 direction. The power supply wiring VDL28 is connected to the sense amplifier/write driver 20b of the bank BK1 through a contact point not shown.

In addition, power supply wiring VDL22_0 to VDL22_y are connected to power supply wiring VDL23_0 to VDL23_y via contacts C24_0 to C24_y.

The power supply wiring lines VDL23_0 to VDL23_y extend in the D2 direction. The power supply wiring VDL23_0 is connected to the power supply wiring VDL24_0~VDL24_y via the contacts C25_0~C25_y.

The power supply wiring lines VDL24_0 to VDL24_y extend in the D1 direction. The power supply wiring VDL24_0 is connected to the power supply wiring VDL27_0~VDL27_z via the contacts C26_0-0~C26_0-z. Similarly, the power supply wiring VDL24_y is connected to the power supply wiring VDL27_0 to VDL27_z via the contacts C26_y-0 to C26_y-z. In addition, it is preferable that the power supply wiring VDL24_0~VDL24_y is the most One less one is provided on the sense amplifier/write driver 20b. In this example, the power supply wiring VDL24_y is provided on the sense amplifier/write driver 20b.

<2-1-2>C-C section

The C-C cross section of FIG. 20 will be described using FIG. 21. Here, for the sake of simple description, the insulating layer covering each wiring is not shown. In addition, a structure not shown in the figure in the C-C cross section is indicated by a broken line.

The basic description of the block BK0 is roughly the same as that described in FIG. 6. The difference between FIG. 7 and FIG. 21 is that the power supply wiring and the main character line MWL are alternately provided in the third wiring layer.

<2-1-3> Section D-D

The D-D section of FIG. 20 will be described using FIG. 22. Here, for the sake of simple description, the insulating layer covering each wiring is not shown. In addition, a structure that is not shown in the figure in the D-D cross section is indicated by a broken line.

In FIG. 21, only the power supply wiring VDL21 is connected to the power supply wiring VDL25. However, in FIG. 22, the wiring of the two systems of the power supply wiring VDL22 and VDL24 is connected to the power supply wiring VDL27.

<2-2> Effect

As shown in Figs. 20-22, the power wiring connected to the bank BK0 and the power wiring connected to the bank BK1 are connected near the power pad PDV. In addition, in order to prevent the voltage supplied to the bank BK1 from being lower than the voltage supplied to the bank BK0, the number of power supply wiring lines connected to the bank BK1 is twice the number of power supply wiring lines connected to the bank BK0 . In the first embodiment, for the sake of simple description, the number of power supply wirings connected to the bank BK1 is set to twice the number of power supply wirings connected to the bank BK0. However, the number of power supply wires connected to the bank BK1 may be more than the number of power supply wires connected to the bank BK0.

Therefore, the same effect as the above-mentioned first embodiment can be obtained.

<2-3> Examples of changes

<2-3-1> Variation example 1

The power supply wiring layout of the semiconductor memory device of Modification 1 of the second embodiment will be described using FIG. 23.

The difference between the power supply wiring layout of the semiconductor memory device of Modification 1 of the second embodiment and the power supply wiring layout of the semiconductor memory device of the second embodiment is that a power supply circuit 300 is further added.

Specifically, as shown in FIG. 23, a power supply circuit 300a is provided between the power supply wiring VDL20 and the power supply wiring VDL21. In addition, a power supply circuit 300b is provided between the power supply wiring VDL20 and the power supply wiring VDL22.

The power supply circuit 300a may have any configuration as long as it can transmit the power supply voltage from the power supply wiring VDL20 to the power supply wiring VDL21. The same applies to the power supply circuit 300b, as long as it has a configuration that can transmit the power supply voltage from the power supply wiring VDL20 to the power supply wiring VDL22, it may have any configuration.

<2-3-2> Variation example 2

The power supply wiring layout of the semiconductor memory device of Modification 2 of the second embodiment will be described using FIG. 24.

It may also have a layout as shown in Figure 24. In FIG. 23, one power supply line VDL21 is connected to one power supply circuit 300a. However, as shown in FIG. 24, a plurality of power supply lines VDL21 may be connected to one power supply circuit 300a. Similarly, as shown in FIG. 24, a plurality of power supply lines VDL22 may be connected to one power supply circuit 300b.

<2-3-3> Variation 3

The power supply wiring layout of the semiconductor memory device of Modification 3 of the second embodiment will be described using FIG. 25.

The difference between the power wiring layout of the semiconductor memory device of the second embodiment and the power supply wiring layout of the semiconductor memory device of the second embodiment is that the power pad for bank BK0 and the power pad for bank BK1 are used. Electric separation.

As shown in FIG. 25, the first power pad PDV1 supplies the voltage VDD to the sense amplifier/write driver 20b of the bank BK0 via the power supply wiring VDL.

The first power supply pad PDV1 is connected to the power supply wiring VDL20_0 via the contact C20_0.

The power supply wiring VDL20_0 extends in the D2 direction. Power supply wiring VDL20_0 is connected to power supply wiring VDL21_0 to VDL21_y via contacts C21_0 to C21_y, respectively.

The second power pad PDV2 is connected to the power supply wiring VDL20_1 via the contact C20_1.

The power supply wiring VDL20_1 extends in the D2 direction. The power supply wiring VDL20_1 is connected to the power supply wiring VDL22_0 to VDL22_y through the contacts C22_0 to C22_y, respectively.

<2-3-4> Variation 4

The power supply wiring layout of the semiconductor memory device of Modification 4 of the second embodiment will be described using FIG. 26.

The difference between the power supply wiring layout of the semiconductor memory device of Modification 4 of the second embodiment and the power supply wiring layout of the semiconductor memory device of Modification 3 of the second embodiment is that a power supply circuit 300 is further added.

Specifically, as shown in FIG. 26, a power supply circuit 300a is provided between the power supply wiring VDL20_0 and the power supply wiring VDL21. In addition, a power supply circuit 300b is provided between the power supply wiring VDL20_1 and the power supply wiring VDL22.

As long as the power supply circuit 300a can transmit the power supply voltage from the power supply wiring VDL20_0 to The structure of the power supply wiring VDL21 can be any structure. The same applies to the power supply circuit 300b, as long as the power supply voltage can be transmitted from the power supply wiring VDL20_1 to the power supply wiring VDL22, it may have any structure.

<2-3-5> Variation example 5

The power supply wiring layout of the semiconductor memory device of Modification 5 of the second embodiment will be described using FIG. 27.

It may also have a layout as shown in Figure 27. In FIG. 26, one power supply line VDL21 is connected to one power supply circuit 300a. However, as shown in FIG. 27, a plurality of power supply lines VDL21 may be connected to one power supply circuit 300a. Similarly, as shown in FIG. 27, a plurality of power supply lines VDL22 may be connected to one power supply circuit 300b.

<3> The third embodiment

The third embodiment will be described. In the third embodiment, the controller will be described. Furthermore, the basic structure and basic operation of the semiconductor memory device of the third embodiment are the same as those of the semiconductor memory device of the first embodiment described above. Therefore, descriptions on matters described in the above-mentioned first embodiment and matters that can be easily analogized based on the above-mentioned first embodiment are omitted.

<3-1> Controller

The controller of the semiconductor memory device of the third embodiment will be described using FIG. 28.

Here, when the memory controller stops momentarily, the current path of the internal (semiconductor memory device) and external (memory controller) power supply is cut off, not before the appropriate time point based on the external power supply voltage The controller 16 that performs the action and ends the action appropriately will be described.

A part of the controller 16 is shown in FIG. 28. As shown in FIG. 28, the controller 16 includes a potential drop detector 40, a potential generation circuit 41, a command system circuit 42, and a stabilization capacitor 43.

The potential drop detector 40 determines that "internal voltage VDD* int<external voltage VDD* In the case of "ext", it is determined that the external voltage has not dropped. In contrast, the potential drop detector 40 determines that the external voltage has dropped when it determines that "external voltage VDD*ext<internal voltage VDD*int". The potential drop detector 40 supplies a potential drop detection signal at the "H" level to the potential generating circuit 41 and the command system circuit 42 when judging the external voltage drop. Furthermore, the so-called internal voltage VDD* int refers to the voltage generated by the stabilizing capacitor 43. The so-called external voltage VDD* ext refers to the voltage supplied from the memory controller 2. The external voltage VDD*ext is input to the non-inverting input terminal of the potential drop detector 40 via the resistance element R1 and the node N1. The internal voltage VDD*int is input to the inverting input terminal of the potential drop detector 40 via the resistance element R3 and the node N2.

The potential generating circuit 41 generates various voltages (internal voltage VDD*int) based on the external voltage VDD*ext. The potential generating circuit 41 blocks the current path receiving the external voltage VDD*ext when the potential drop detection signal of the "H" level is received from the potential drop detector 40. Thereby, the potential generating circuit 41 can suppress the internal voltage VDD* int from flowing back to the power supply pad supplying the external voltage VDD* ext.

The stabilizing capacitor 43 is capable of storing charge that can perform, for example, one read operation (first read operation, write operation, second read operation, and judgment operation) even if the external voltage VDD*ext is not supplied. The size of the capacitor.

The command system circuit 42 generates a signal for operating the read circuit 200 or the write driver. When the command system circuit 42 receives the potential drop detection signal at the "H" level from the potential drop detector 40, it causes the semiconductor memory device 1 to operate until it is suitable for turning off. In addition, the command system circuit 42 operates so as not to accept commands after operating the semiconductor memory device 1 to a time suitable for disconnection.

<3-2> Action

<3-2-1> Normal operation

The normal operation of the controller of the semiconductor memory device of the third embodiment will be described using FIG. 29. In FIG. 29, the external voltage VDD* ext, the internal voltage VDD* int, the activation (ACT) command and the writing (Write) command supplied from the memory controller 2, the potential drop detection signal, and the read circuit 200 are shown. The signal SA Act for action and the signal WD Act for the write driver action. Furthermore, the case where the external voltage VDD* ext does not drop will be explained.

When the controller 16 receives the activation command from the memory controller 2, it sets the signal SA Act to the "H" level to activate the read circuit 200 (time T20 to time T21). Although not shown, the controller 16 performs the first read operation by receiving a read command from the memory controller 2.

Next, when the controller 16 receives the activation command from the memory controller 2, it sets the signal SA Act to the "H" level to activate the read circuit 200 (time T22 to time T23). Next, when the controller 16 receives a write command from the memory controller 2, it sets the signal WD Act to the "H" level to activate the write driver (time T23 to T25). Thereby, the controller 16 performs a "0" writing operation.

Although not shown, the controller 16 completes the reading operation by performing the second reading operation afterwards.

<3-2-2> Action when it stops instantly

Next, the operation when the controller of the semiconductor memory device of the third embodiment is instantaneously stopped will be described using FIG. 30.

When the controller 16 receives the activation command from the memory controller 2, it sets the signal SA Act to the "H" level to activate the read circuit 200 (time T30 to time T31). Although not shown, the controller 16 performs the first reading operation by receiving a reading command from the memory controller 2.

Next, the generation momentarily stops at time T31, and the external voltage VDD*ext drops. borrow Therefore, at time T32, the potential drop detector 40 detects a drop in the external voltage VDD*ext, and sets the potential drop detection signal to the "H" level. When the command system circuit 42 receives the potential drop detection signal at the "H" level from the potential drop detector 40, it causes the semiconductor memory device 1 to operate until it is suitable for turning off. The action immediately performed at time T32 is the "0" write action. The so-called "0" writing operation refers to the operation of overwriting the data of the memory cell MC and destroying the data stored in the memory cell. Therefore, if the external voltage VDD* ext is not supplied to the semiconductor memory device 1 and the internal voltage VDD* int is not generated and the "0" write operation is performed, the data stored in the memory cell will be lost concern. Therefore, the command system circuit 42 does not accept commands from the memory controller 2. Thereby, the controller 16 can prevent the data stored in the memory cell from being damaged. Although not shown here, for example, if the external voltage VDD*ext drops after the "0" writing operation, the system circuit 42 is instructed to proceed to the data writing operation. Thereby, the controller 16 can prevent the data stored in the memory cell from being damaged.

<3-3> Effect

According to the above-mentioned embodiment, the controller is configured as follows: it is judged that the memory controller is stopped instantly, the current path between the semiconductor memory device and the memory controller is cut off, and the power supply voltage from the memory controller is not properly terminated action.

Therefore, even in a semiconductor memory device that performs self-referencing read operations, data damage can be suppressed.

<4> Fourth Embodiment

The fourth embodiment will be described. In the fourth embodiment, the write driver will be described. Furthermore, the basic structure and basic operation of the semiconductor memory device of the fourth embodiment are the same as those of the semiconductor memory device of the first to third embodiments described above. Therefore, omit the first to third Explanations about the items explained in the embodiment and the items that can be easily analogized based on the above-mentioned first to third embodiments.

<4-1> Composition

<4-1-1> Sense amplifier/write driver

The sense amplifier/write driver 20b of the semiconductor memory device of the fourth embodiment will be described using FIG. 31.

As shown in FIG. 31, the sense amplifier/write driver 20b includes a sense circuit 200 and a write driver 230 for each group of global bit lines and global source lines. The write driver 230 is connected to the global bit line and the global source line, and supplies the same voltage as the power supply voltage VDD supplied to the preamplifier 210 and the sense amplifier 220.

<4-1-2> Memory array and write drive

The memory array 20a described in the first embodiment will be described in more detail.

As shown in FIG. 32, the memory array 20a includes a plurality of secondary memory areas (not shown). The secondary memory area includes a memory cell array 20d, a first row selection circuit 20e, a second row selection circuit 20f, and a read current sink 20g. Here, for the sake of simplicity, a group of memory cell array 20d, first row selection circuit 20e, second row selection circuit 20f, and read current sink 20g will be described.

The structure of the memory cell array 20d is the same as that of the memory array 20a described using FIG. 2, so the description is omitted.

The first row selection circuit 20e is connected to the memory cell array 20d via a plurality of bit lines BL_0~BL_j-1. In addition, the bit line BL is selected based on the first row selection signal CSL1_0 to CSL1_j-1 received by the self-decoder 12. Furthermore, when the first row selection signals CSL1_0 to CSL1_j-1 are not distinguished, they are simply referred to as the first row selection signal CSL1.

In addition, the first row selection circuit 20e has a transistor whose one end is connected to each bit line BL twenty one. In addition, a global bit line GBL is connected to the other end of the transistor 21, and row selection signals CSL1_0~CSL1_j-1 are respectively connected to the gate electrodes.

The second row selection circuit 20f is connected to the memory cell array 20d via a plurality of source lines SL_0~SL_j-1. In addition, the source line SL is selected based on the second row selection signal CSL2_0 to CSL2_j-1 received by the self-decoder 12. Furthermore, when the second row selection signals CSL2_0 to CSL2_j-1 are not distinguished, they are simply referred to as the second row selection signal CSL2.

In addition, the second row selection circuit 20f includes a transistor 22 whose one end is connected to each source line SL. In addition, the other end of the transistor 22 is connected with a global source line GSL, and the gate electrodes are respectively connected with row selection signals CSL2_0~CSL2_j-1.

The sense current sink 20g is connected to the second row selection circuit 20f via the global source line GSL. In addition, the sense current sink 20g sets the voltage of any source line SL to VSS based on the control signal RDS received from the controller 16 and the row decoder 12.

The write driver 230 is connected to the first row selection circuit 20e via the global bit line GBL. In addition, the write driver 230 is connected to the second row selection circuit 20f via the global source line GSL. In addition, the write driver 230 causes current to flow through the memory cell MC connected to the select word line WL based on the control signal received from the controller 16 and the write data received via the IO circuit 17, thereby writing data.

<4-1-3> Write to drive

The write driver 230 of the semiconductor memory device of the fourth embodiment will be described using FIG. 33.

As shown in FIG. 33, the write driver 230 includes NAND (NOT AND) operation circuits 23a, 23b, 23c, 23f, 23g, and 23h, NOR (NOT OR) operation circuit 23d, inverter 23e, PMOS (P-channel metal oxide semiconductor, P channel Metal oxide semiconductor) transistors 23j, 23k, 23m, and 23n, and NMOS (N-channel metal oxide semiconductor) transistors 23i, 23l, 23o, and 23p.

The NAND operation circuit 23a receives the signal WEN_1 (first write enable signal) at the first input terminal, receives the signal WDATA (write data) at the second input terminal, and outputs the NAND operation results of the signal WEN_1 and the signal WDATA to the node N11. The signal WEN_1 is supplied by the controller 16. The signal WDATA is supplied by the IO circuit 17.

The NAND operation circuit 23b receives the signal WEN_2 (the second write enable signal) at the first input terminal, receives the signal WDATA at the second input terminal, and outputs the NAND operation result of the signal WEN_2 and the signal WDATA to the node N12. The signal WEN_2 is supplied by the controller 16.

The NAND operation circuit 23c receives the output signal of the NAND operation circuit 23a at the first input terminal, receives the output signal of the NAND operation circuit 23b at the second input terminal, and outputs the NAND operation result of the received signal to the node N13.

The NOR operation circuit 23d receives the signal WEN_1 at the first input terminal, receives the signal WEN_2 at the second input terminal, receives the signal PCHGOFF (precharge off signal) at the third input terminal, and combines the signal WEN_1, the signal WEN_2 and the signal PCHGOFF to NOR The calculation result is output to node N16.

The inverter 23e outputs the signal BWDATA after inverting the signal WDATA to the node N17.

The NAND operation circuit 23f receives the signal WEN_1 at the first input terminal, receives the signal BWDATA at the second input terminal, and outputs the NAND operation result of the signal WEN_1 and the signal BWDATA to the node N18.

The NAND arithmetic circuit 23g receives the signal WEN_2 at the first input terminal and connects to the second input terminal The signal BWDATA is received, and the NAND operation result of the signal WEN_2 and the signal BWDATA is output to the node N19.

The NAND operation circuit 23h receives the output signal of the NAND operation circuit 23f at the first input terminal, receives the output signal of the NAND operation circuit 23g at the second input terminal, and outputs the NAND operation result of the received signal to the node N20.

The PMOS transistor 23j supplies the voltage Vwrt1 to the node N21 (global bit line GBL) based on the output signal of the NAND operation circuit 23a. The voltage Vwrt1 refers to the voltage VDD that is also used in the readout circuit 200, and can also be applied to the power supply wiring layout described in the first embodiment or the second embodiment. The PMOS transistor 23j is used as a transistor for charging the global bit line GBL.

The PMOS transistor 23k supplies the voltage Vwrt2 to the node N21 based on the output signal of the NAND operation circuit 23b. The voltage Vwrt2 is, for example, a voltage dedicated to the write driver 230. The voltage Vwrt2 is a voltage from which the impedance of the power pad is higher than the voltage Vwrt1. Furthermore, the voltage values of the voltage Vwrt1 and the voltage Vwrt2 are not defined here. However, regardless of the relationship between the voltage values of the voltage Vwrt1 and the voltage Vwrt2, the following effects can be achieved.

The NMOS transistor 23l discharges the node N21 based on the output signal of the NAND operation circuit 23h.

The NMOS transistor 23o discharges the node N21 based on the output signal of the NOR operation circuit 23d.

The PMOS transistor 23m supplies the voltage Vwrt1 to the node N22 (global source line GSL) based on the output signal of the NAND operation circuit 23f. The PMOS transistor 23m is used as a transistor for charging the global source line GSL.

The PMOS transistor 23n supplies the voltage Vwrt2 to the node N22 based on the output signal of the NAND operation circuit 23g.

The NMOS transistor 23i discharges the node N22 based on the output signal of the NAND operation circuit 23c.

The NMOS transistor 23p discharges the node N22 based on the output signal of the NOR operation circuit 23d.

<4-2> Action

Next, the waveform during the write operation of the semiconductor memory device of the fourth embodiment will be described using FIG. 34. The write operation described here is not the write operation performed during the aforementioned read operation, but a general write operation. Of course, it can also be applied to the write operation performed during the aforementioned read operation. In addition, a case where the voltages of the bit line BL and the source line SL are set to VSS during the period when the write operation and the read operation to the cell are not performed will be described.

[Time T40]~[Time T41]

The column decoder 14 sets the voltage of the word line WL to the "L" level. In addition, the row decoder 13 sets the voltages of the signals CSL1 and CSL2 to the "L" level. In addition, the controller 16 sets the voltages of the signals WEN1 and WEN2 to the "L" level, and sets the signal PCHGOFF (not shown) to the "L" level.

Here, the operation of the write driver 230 will be described using FIG. 33.

The NAND operation circuit 23a supplies a signal of "H" level based on the received signal. Similarly, the NAND arithmetic circuit 23b supplies a signal of "H" level based on the received signal. The NAND operation circuit 23c supplies a signal of "H" level based on the received signal. The NOR operation circuit 23d supplies a signal of "H" level based on the received signal. The NAND operation circuit 23f supplies a signal of "H" level based on the received signal. Similarly, the NAND operation circuit 23g supplies a signal of "H" level based on the received signal. The NAND operation circuit 23h supplies a signal of "L" level based on the received signal.

Thereby, the PMOS transistors 23j, 23k, 23m, and 23n and the NMOS transistors 23i, 23l are turned off, and the NMOS transistors 23o, 23p are turned on. As a result, the global bit line GBL and the global source line GSL are discharged.

[Time T41]~[Time T42]

The column decoder 14 sets the voltage of the selected word line WL to the "H" level according to the column address. In addition, the row decoder 13 sets the voltage of the selection signal CSL1 and the selection signal CSL2 to the "H" level according to the row address.

[Time T42]~[Time T43]

The controller 16 sets the voltage of the signal WEN1 to the "H" level. Moreover, the signal WDATA is also input at this point in time. Furthermore, when writing "1" data to the memory cell MC, the signal WDATA becomes the "H" level. Also, when writing "0" data to the memory cell MC, the signal WDATA becomes the "L" level.

Here, the operation of the write driver 230 when the signal WDATA is at the "H" level (in the case of WDATA=1) will be described.

As shown in FIG. 33, the NAND operation circuit 23a supplies a signal of "L" level based on the received signal. The NAND operation circuit 23b supplies a signal of "H" level based on the received signal. The NAND operation circuit 23c supplies a signal of "H" level based on the received signal. The NOR operation circuit 23d supplies a signal of "L" level based on the received signal. The NAND operation circuit 23f supplies a signal of "H" level based on the received signal. Similarly, the NAND operation circuit 23g supplies a signal of "H" level based on the received signal. The NAND operation circuit 23h supplies a signal of "L" level based on the received signal.

Thereby, the PMOS transistor 23j and the NMOS transistor 23i are turned on. As a result, the voltage Vwrt1 is applied to the global bit line GBL, and the global source line GSL is discharged.

As a result, as shown in FIG. 34, the selected bit line BL is charged to the "H" level, and the source line SL becomes the "L" level.

Furthermore, since the voltage Vwrt1 has a lower impedance from the power pad than the voltage Vwrt2, the bit line BL is selected to be charged at a high speed.

In addition, the operation of the write driver 230 when the signal WDATA is at the "L" level (when WDATA=0) is described.

As shown in FIG. 33, the NAND operation circuit 23a supplies a signal of "H" level based on the received signal. The NAND operation circuit 23b supplies a signal of "H" level based on the received signal. The NAND operation circuit 23c supplies a signal of "L" level based on the received signal. The NOR operation circuit 23d supplies a signal of "L" level based on the received signal. The NAND operation circuit 23f supplies a signal of "L" level based on the received signal. The NAND operation circuit 23g supplies a signal of "H" level based on the received signal. The NAND operation circuit 23h supplies a signal of "H" level based on the received signal.

Thereby, the PMOS transistor 23m and the NMOS transistor 23l are turned on. As a result, the voltage Vwrt1 is applied to the global source line GSL, and the global bit line GBL is discharged.

Thereby, as shown in FIG. 34, the selected source line SL is charged to the "H" level, and the bit line BL becomes the "L" level.

Furthermore, since the voltage Vwrt1 is a voltage with a lower impedance from the power pad than the voltage Vwrt2, the source line SL is selected to be charged at a high speed.

[Time T43]~[Time T44]

The controller 16 sets the voltage of the signal WEN1 to the "L" level, and sets the voltage of the signal WEN2 to the "H" level.

Here, the operation of the write driver 230 when the signal WDATA is at the "H" level (in the case of WDATA=1) will be described.

As shown in FIG. 33, the NAND operation circuit 23a supplies a signal of "H" level based on the received signal. The NAND operation circuit 23b supplies a signal of "L" level based on the received signal. The NAND operation circuit 23c supplies a signal of "H" level based on the received signal. The NOR operation circuit 23d supplies a signal of "L" level based on the received signal. The NAND operation circuit 23f supplies a signal of "H" level based on the received signal. Similarly, the NAND operation circuit 23g supplies a signal of "H" level based on the received signal. The NAND operation circuit 23h supplies a signal of "L" level based on the received signal.

Thereby, the PMOS transistor 23k and the NMOS transistor 23i are turned on. As a result, the global bit line GBL is applied with the voltage Vwrt2, and the global source line GSL is discharged.

Thereby, as shown in FIG. 34, the selected bit line BL maintains the "H" level, and the source line SL becomes the "L" level.

Furthermore, although the voltage Vwrt2 has a higher impedance from the power supply pad than the voltage Vwrt1, the selected bit line BL has been charged at time T42 to time T43. Therefore, even if it is switched to a voltage with high impedance from the power supply pad at time T43 to time T44, the voltage drop accompanying the charging of the global source line GSL and the source line SL will not occur.

In addition, the operation of the write driver 230 when the signal WDATA is at the "L" level (when WDATA=0) is described.

As shown in FIG. 33, the NAND operation circuit 23a supplies a signal of "H" level based on the received signal. The NAND operation circuit 23b supplies a signal of "H" level based on the received signal. The NAND operation circuit 23c supplies a signal of "L" level based on the received signal. The NOR operation circuit 23d supplies a signal of "L" level based on the received signal. The NAND operation circuit 23f supplies a signal of "H" level based on the received signal. The NAND operation circuit 23g supplies a signal of "L" level based on the received signal. The NAND operation circuit 23h supplies a signal of "H" level based on the received signal.

Thereby, the PMOS transistor 23n and the NMOS transistor 23l are turned on. As a result, The voltage Vwrt2 is applied to the global source line GSL, and the global bit line GBL is discharged.

Thereby, as shown in FIG. 34, the source line SL is selected to maintain the "H" level, and the bit line BL becomes the "L" level.

Furthermore, although the voltage Vwrt2 is a voltage with a higher impedance from the power pad than the voltage Vwrt1, at time T42 to time T43, the selected source line SL has been charged. Therefore, even if it is switched to a voltage with high impedance from the power supply pad at time T43 to time T44, the voltage drop accompanying the charging of the global source line GSL and the source line SL will not occur.

[Time T44]~[Time T45]

The controller 16 ends the writing operation by setting the voltage of the signal WEN2 to the "L" level. The NOR operation circuit 23d supplies a signal of "L" level based on the received signal. Thereby, the NMOS transistors 23o and 23p are turned on. As a result, the global bit line GBL and the global source line GSL are discharged.

<4-3> Effect

<4-3-1> Summary

According to the above embodiment, during the first period of charging the global bit line GBL or the global source line GSL, the charging is performed using the first power source with relatively low impedance from the power pad. In addition, after the global bit line GBL or the global source line GSL is charged and during the write operation period, the second power source whose impedance from the power pad is higher than the first power source is used to maintain the global bit line GBL or global source line The potential of GSL. In this way, the write operation can be performed appropriately.

<4-3-2> Comparative example

Here, in order to make the effect of the above-mentioned embodiment easy to understand, a comparative example will be described.

<4-3-2-1> Write to the drive

Write driver of the semiconductor memory device of the comparative example of the fourth embodiment using FIG. 35 230 for description.

As shown in FIG. 35, the write driver 230 includes NAND operation circuits 24a and 24f, NOR operation circuits 24d, inverters 24c, 24e, and 24h, PMOS transistors 24b and 24g, and NMOS transistors 24i, 24j, 24k, and 24l. .

The NAND operation circuit 24a receives the signal WEN (write enable signal) at the first input terminal, receives the signal WDATA at the second input terminal, and outputs the NAND operation result of the signal WEN and the signal WDATA to the node N32.

The inverter 24c outputs a signal obtained by inverting the output signal of the NAND operation circuit 24a.

The NOR operation circuit 24d receives the signal WEN at the first input terminal, receives the signal PCHGOFF at the second input terminal, and outputs the NOR operation result of the signal WEN and the signal PCHGOFF to the node N33.

The inverter 24e outputs the signal BWDATA after inverting the signal WDATA.

The NAND operation circuit 24f receives the signal WEN at the first input terminal, receives the signal BWDATA at the second input terminal, and outputs the NAND operation result of the signal WEN and the signal BWDATA to the node N34.

The inverter 24h outputs a signal obtained by inverting the output signal of the NAND operation circuit 24f.

The PMOS transistor 24b supplies the voltage Vwrt to the node N35 (global bit line GBL) based on the output signal of the NAND operation circuit 24a. The voltage Vwrt corresponds to the voltage Vwrt2 of the above-mentioned embodiment.

The NMOS transistor 24i discharges the node N35 based on the output signal of the inverter 24h.

The NMOS transistor 24k discharges the node N35 based on the output signal of the NOR operation circuit 24d.

The PMOS transistor 24g sends the output signal of the NAND operation circuit 24f to the node N36 (full The local source line GSL) supplies the voltage Vwrt.

The NMOS transistor 24j discharges the node N36 based on the output signal of the inverter 24c.

The NMOS transistor 241 discharges the node N36 based on the output signal of the NOR operation circuit 24d.

<4-3-2-2> Action

Here, the waveform during the write operation of the semiconductor memory device of the comparative example of the fourth embodiment will be described using FIG. 36. A description will be given as a case where the voltages of the bit line BL and the source line SL are set to VSS during the period when the write operation and the read operation to the cell are not performed.

[Time T50]~[Time T51]

The column decoder 14 sets the voltage of the word line WL to the "L" level. In addition, the row decoder 13 sets the voltages of the signals CSL1 and CSL2 to the "L" level. In addition, the controller 16 sets the voltage of the signal WEN to the "L" level, and sets the signal PCHGOFF (not shown) to the "L" level.

Here, the operation of the write driver 230 will be described using FIG. 35.

The NAND operation circuit 24a supplies a signal of "H" level based on the received signal. The NOR operation circuit 24d supplies a signal of "H" level based on the received signal. The NAND operation circuit 24f supplies a signal of "H" level based on the received signal.

Thereby, the NMOS transistors 24i and 24j are turned off, and the NMOS transistors 24k and 24l are turned on.

As a result, the global bit line GBL and the global source line GSL are discharged.

[Time T51]~[Time T52]

The column decoder 14 sets the voltage of the selected word line WL to the "H" level according to the column address. In addition, the row decoder 13 sets the voltage of the selection signal CSL1 and the selection signal CSL2 to the "H" level according to the row address.

[Time T52]~[Time T53]

The controller 16 sets the voltage of the signal WEN to the "H" level. Moreover, the signal WDATA is also input at this point in time.

Here, the operation of the write driver 230 when the signal WDATA is at the "H" level (in the case of WDATA=1) will be described.

As shown in FIG. 35, the NAND operation circuit 24a supplies a signal of "L" level based on the received signal. The NOR operation circuit 24d supplies a signal of "L" level based on the received signal. The NAND operation circuit 24f supplies a signal of "H" level based on the received signal.

Thereby, the PMOS transistor 24b and the NMOS transistor 24j are turned on. As a result, the voltage Vwrt is applied to the global bit line GBL, and the global source line GSL is discharged.

However, the wiring length of the global bit line GBL is longer and the capacitance is larger. Therefore, when the global bit line GBL is charged by the voltage Vwrt whose impedance from the power pad is the same as the voltage Vwrt2, the voltage Vwrt may drop due to the current peak. As a result, as shown in FIG. 36, the charging time of the global bit line GBL may become longer. In this case, the effective writing time to the memory cell MC may be reduced, resulting in poor writing.

In addition, the operation of the write driver 230 when the signal WDATA is at the "L" level (when WDATA=0) is described.

As shown in FIG. 35, the NAND operation circuit 24a supplies a signal of "H" level based on the received signal. The NOR operation circuit 24d supplies a signal of "L" level based on the received signal. The NAND operation circuit 24f supplies a signal of "L" level based on the received signal.

Thereby, the PMOS transistor 24g and the NMOS transistor 24i are turned on. As a result, the voltage Vwrt is applied to the global source line GSL, and the global bit line GBL is discharged.

Even when the signal WDATA is at the "L" level, there may be problems with the above The same question.

<4-3-3> Summary

However, according to the above-mentioned embodiment, during the first period of charging the global bit line GBL or the global source line GSL, charging is performed using a voltage with a low impedance from the power pad. The power source with low impedance from the power pad is not affected by the voltage drop caused by the above-mentioned peak charging current during the first period. Therefore, the global bit line GBL or the global source line GSL can be charged at high speed. As a result, it is possible to suppress the increase in the write failure rate due to the voltage drop. Furthermore, as explained in the first to third embodiments, it is difficult for different memory banks to transmit power noise. Therefore, the operation failure caused by the power noise of other memory banks can be suppressed.

<4-4> Variation example

<4-4-1> Write to drive

The write driver 230 of the semiconductor memory device according to the modification of the fourth embodiment will be described with reference to FIG. 37.

As shown in FIG. 37, the write driver 230 includes NAND operation circuits 25a and 25f, NOR operation circuits 25d, inverters 25c, 25e, and 25h, PMOS transistors 25b, 25g, 25m, and 25n, and NMOS transistors 25i, 25j , 25k and 25l.

The NAND operation circuit 25a receives the signal WEN at the first input terminal, receives the signal WDATA at the second input terminal, and outputs the NAND operation result of the signal WEN and the signal WDATA to the node N42. The signal WEN is supplied by the controller 16.

The inverter 25c outputs a signal obtained by inverting the output signal of the NAND operation circuit 25a.

The NOR operation circuit 25d receives the signal WEN at the first input terminal, receives the signal PCHGOFF at the second input terminal, and outputs the NOR operation result of the signal WEN and the signal PCHGOFF to the node N43.

The inverter 25e outputs the signal BWDATA after inverting the signal WDATA.

The NAND operation circuit 25f receives the signal WEN at the first input terminal, receives the signal BWDATA at the second input terminal, and outputs the NAND operation result of the signal WEN and the signal BWDATA to the node N44.

The inverter 25h outputs a signal obtained by inverting the output signal of the NAND operation circuit 25f.

The PMOS transistor 25m supplies the voltage Vwrt1 to the node N47 based on the signal EN_1.

The PMOS transistor 25n supplies the voltage Vwrt2 to the node N47 based on the signal EN_2.

The PMOS transistor 25b supplies the voltage Vwrt1 or Vwrt2 to the node N45 (global bit line GBL) based on the output signal of the NAND operation circuit 25a.

The NMOS transistor 25i discharges the node N45 based on the output signal of the inverter 25h.

The NMOS transistor 25k discharges the node N45 based on the output signal of the NOR operation circuit 25d.

The PMOS transistor 25g supplies the voltage Vwrt1 or Vwrt2 to the node N46 (global source line GSL) based on the output signal of the NAND operation circuit 25f.

The NMOS transistor 25j discharges the node N46 based on the output signal of the inverter 25c.

The NMOS transistor 25l discharges the node N46 based on the output signal of the NOR operation circuit 25d.

<4-4-2> Action

Here, the waveform during the write operation of the semiconductor memory device of the modification of the fourth embodiment will be described using FIG. 38.

[Time T60]~[Time T61]

The column decoder 14 sets the voltage of the word line WL to the "L" level. In addition, the row decoder 13 sets the voltages of the signals CSL1 and CSL2 to the "L" level. Furthermore, the controller 16 turns the power of the signal WEN Set the pressure and PCHGOFF (not shown) to the "L" level, and set the signals EN_1 and EN_2 to the "H" level.

Here, the operation of the write driver 230 will be described using FIG. 37. A description will be given as a case where the voltages of the bit line BL and the source line SL are set to VSS during the period when the write operation and the read operation to the cell are not performed.

The NAND operation circuit 25a supplies a signal of "H" level based on the received signal. The NOR operation circuit 25d supplies a signal of "H" level based on the received signal. The NAND operation circuit 25f supplies a signal of "H" level based on the received signal.

Thereby, the PMOS transistors 25b, 25g, 25m, and 25n and the NMOS transistors 25i, 25j are turned off, and the NMOS transistors 25k, 25l are turned on. As a result, the global bit line GBL and the global source line GSL are discharged.

[Time T61]~[Time T62]

The column decoder 14 sets the voltage of the selected word line WL to the "H" level according to the column address. In addition, the row decoder 13 sets the voltage of the selection signal CSL1 and the selection signal CSL2 to the "H" level according to the row address.

[Time T62]~[Time T63]

The controller 16 sets the voltage of the signal WEN to the "H" level, and sets the signal EN_1 to the "L" level. Moreover, the signal WDATA is also input at this point in time.

Here, the operation of the write driver 230 when the signal WDATA is at the "H" level (in the case of WDATA=1) will be described.

As shown in FIG. 37, the NAND operation circuit 25a supplies a signal of "L" level based on the received signal. The NOR operation circuit 25d supplies a signal of "L" level based on the received signal. The NAND operation circuit 25f supplies a signal of "H" level based on the received signal.

Thereby, the PMOS transistors 25b and 25m and the NMOS transistor 25j are turned on. As a result, the voltage Vwrt1 is applied to the global bit line GBL, and the global source line GSL is discharged.

Thereby, as in the first embodiment, the global bit line GBL is charged at a high speed.

Furthermore, the operation of the write driver 230 when the signal WDATA is at the "L" level (in the case of WDATA=0) will be described.

As shown in FIG. 37, the NAND operation circuit 25a supplies a signal of "H" level based on the received signal. The NOR operation circuit 25d supplies a signal of "L" level based on the received signal. The NAND operation circuit 25f supplies a signal of "L" level based on the received signal.

Thereby, the PMOS transistors 25g and 25m and the NMOS transistor 25i are turned on. As a result, the voltage Vwrt1 is applied to the global source line GSL, and the global bit line GBL is discharged.

Thereby, as in the first embodiment, the global source line GSL is charged at a high speed.

[Time T62]~[Time T63]

The controller 16 sets the signal EN_1 to the "H" level, and the signal EN_2 to the "L" level.

Here, the operation of the write driver 230 when the signal WDATA is at the "H" level (in the case of WDATA=1) will be described.

As shown in FIG. 37, the NAND operation circuit 25a supplies a signal of "L" level based on the received signal. The NOR operation circuit 25d supplies a signal of "L" level based on the received signal. The NAND operation circuit 25f supplies a signal of "H" level based on the received signal.

Thereby, the PMOS transistors 25b and 25n and the NMOS transistor 25j are turned on. As a result, the global bit line GBL is applied with the voltage Vwrt2, and the global source line GSL is discharged.

Thereby, as in the first embodiment, the potential of the global bit line GBL is maintained.

Furthermore, when the signal WDATA is at the "L" level (when WDATA=0) The operation of the write driver 230 will be described.

As shown in FIG. 37, the NAND operation circuit 25a supplies a signal of "H" level based on the received signal. The NOR operation circuit 25d supplies a signal of "L" level based on the received signal. The NAND operation circuit 25f supplies a signal of "L" level based on the received signal.

Thereby, the PMOS transistors 25g and 25n and the NMOS transistor 25i are turned on. As a result, the voltage Vwrt2 is applied to the global source line GSL, and the global bit line GBL is discharged.

As a result, as in the first embodiment, the potential of the global source line GSL is maintained.

<4-4-3> Effect

As described above, even in the write drive shown in FIG. 37, the same effect as the fourth embodiment can be obtained.

Furthermore, in the above-mentioned embodiment, the case where the voltage of the bit line BL and the source line SL is set to VSS during the period when the write operation and the read operation to the cell are not performed is described. The same effect can be obtained when the voltages of the bit line BL and the source line SL are floating.

When the voltages of the bit line BL and the source line SL are floated, for example, a waveform diagram corresponding to FIG. 34 of the fourth embodiment is shown in FIG. 39.

That is, as shown in FIG. 39, after time T44, the voltages of the bit line BL and the source line SL of WDATA = "1" gradually approach, and maintain the values between the voltage levels between time T43 and time T44 . Furthermore, after the time T44, the voltages of the bit line BL and the source line SL with WDATA="0" gradually approach, and maintain the values between the voltage levels between the time T43 and the time T44.

Similarly, in FIG. 36 of the comparative example of the fourth embodiment, when the voltages of the bit line BL and the source line SL are floated, as shown in FIG. 40, after the time T54, WDATA="1" The voltages of the bit line BL and the source line SL gradually approach and maintain the values between the voltage levels between time T53 and time T54. Also, after time T54, WDATA="0" The voltages of the bit line BL and the source line SL gradually approach and maintain the value between the voltage levels.

Similarly, in FIG. 38 of the comparative example of the fourth embodiment, when the voltages of the bit line BL and the source line SL are floated, as shown in FIG. 41, after the time T64, WDATA="1" The voltages of the bit line BL and the source line SL gradually approach and maintain the values between the voltage levels from time T63 to time T64. Furthermore, after the time T64, the voltages of the bit line BL and the source line SL with WDATA="0" gradually approach and maintain the values between the voltage levels between the time T63 and the time T64.

<5>Other

Furthermore, the term "connection" in each of the above-mentioned embodiments also includes a state in which other objects such as transistors or resistors are interposed and indirectly connected.

Here, the MRAM that uses a magnetoresistance element (Magnetic Tunnel junction (MTJ) element) as a resistance variable element to store data is described as an example, but it is not limited to this.

For example, it can also be applied to the same resistance change memory as MRAM, such as ReRAM (Resistive random-access memory), PCRAM (Phase change Random Access Memory, phase change random access memory) Generally, semiconductor memory devices have components that use resistance changes to store data.

Moreover, whether volatile memory or non-volatile memory, as long as the semiconductor memory device has the ability to memorize data by the resistance change accompanying the application of current or voltage, or by converting the resistance difference accompanying the resistance change into a current difference Or voltage difference can be used to read the memorized data components.

In addition, in each of the above-mentioned embodiments, the bit line pair is referred to as the bit line BL and the source line SL for convenience of description, but it is not limited to this, for example, it may also be referred to as the first bit line and the second bit. Element line Wait.

As mentioned above, the embodiment of the present invention has been described, but the present invention is not limited to the above-mentioned embodiment, and can be implemented with various changes without departing from the gist. Furthermore, the above-mentioned embodiment includes inventions of various stages, and various inventions are proposed by appropriately combining the constituent elements disclosed. For example, even if some constituent elements are deleted from the constituent elements that have been disclosed, they can be proposed as an invention as long as the specified effect can be obtained.

[Related Application Case]

This application enjoys priority based on Japanese Patent Application No. 2017-60041 (application date: March 24, 2017). This application contains all the contents of the basic application by referring to the basic application.

20a‧‧‧Memory array

20b‧‧‧Sense Amplifier/Write Driver

BK0‧‧‧Bank

BK1‧‧‧Bank

C0‧‧‧Contact

C1_0~C1_x‧‧‧Contact

C2_0~C2_x‧‧‧Contact

C3_0~C3_x‧‧‧Contact

C4_0~C4_x‧‧‧Contact

C5_0~C5_x‧‧‧Contact

C6_0~C6_x‧‧‧Contact

C7_0~C7_x‧‧‧Contact

D1‧‧‧direction

D2‧‧‧direction

D3‧‧‧direction

PDV‧‧‧Power Pad

SA‧‧‧Sense amplifier

VDL0‧‧‧Power Wiring

VDL1_0~VDL1_x‧‧‧Power wiring

VDL2_0~VDL2_x‧‧‧Power wiring

VDL3‧‧‧Power Wiring

VDL4_0~VDL4_x‧‧‧Power wiring

VDL5_0~VDL5_x‧‧‧Power wiring

VDL6‧‧‧Power Wiring

WD‧‧‧Write to drive

Claims (17)

A semiconductor memory device including: a power supply pad; a metal layer; a first memory bank including a first memory array and a first peripheral circuit located on the first side of the first memory array; a second memory bank, which Equipped with a second memory array and a second peripheral circuit located on the first side of the second memory array, wherein the first storage system is located between the power pad and the second memory bank in the first direction; plural The first power wirings are in the metal layer and are spaced from each other in a second direction crossing the first direction, and each of the plurality of first power wirings extends in the first direction While crossing the first memory array to reach the first peripheral circuit and connecting the power pad to the first peripheral circuit, the plurality of first power supply wirings do not reach the second peripheral circuit; a plurality of second power supplies Wirings, which are in the metal layer and are separated from each other in the second direction, each of the plurality of second power supply wirings extends in the first direction to cross the first memory array and the first periphery The circuit and the second memory array reach the second peripheral circuit and connect the power supply pad to the second peripheral circuit, and the plurality of second power supply wirings are located in the metal layer from the plurality of first power supply wirings The position is offset in the second direction; and a plurality of third power wirings, which are in the metal layer and are separated from each other in the second direction, and the plurality of third power wirings Each extends in the first direction above and beyond the above The second memory array reaches the second peripheral circuit, the third power wiring of the plurality is electrically connected to the second power wiring of the plurality and the second peripheral circuit, and the position of the third power wiring of the plurality is from The position of the second power wiring is offset in the second direction, and the plurality of third power wirings are aligned with the positions of the first power wiring in the second direction, respectively. The semiconductor memory device of claim 1, wherein the number of the plurality of first power supply wirings in the metal layer is less than the number of the plurality of second power supply wirings in the metal layer and the number of the plurality of first power supply wirings in the metal layer 3 The sum of the number of power wiring. The semiconductor memory device of claim 1, wherein the plurality of first power supply wirings are located above the first memory bank in a third direction orthogonal to the plane of the metal layer; and the plurality of first power wirings 2 Power wiring system: located above the first memory bank and the second memory bank in the third direction; and the plurality of third power wiring systems: located above the second memory bank in the third direction , But not above the first bank. According to any one of claims 1 to 3, the semiconductor memory device further includes: a first power supply circuit located between the power supply pad and the plurality of first power supply wires; and a second power supply circuit located on the power supply Between the pad and the above-mentioned plural second power supply wiring. For example, the semiconductor memory device of any one of claims 1 to 3, further comprising: a plurality of first power supply circuits, each of which is located between the power pad and each of the plurality of first power wirings; and In the second power supply circuit, each of them is located between the power supply pad and each of the plurality of second power supply wirings. A semiconductor memory device comprising: a first power supply pad; a second power supply pad; a metal layer including a plurality of first power supply wirings, a plurality of second power supply wirings, and a plurality of third power supply wirings; a first storage body, which A plurality of memory cells and a first peripheral circuit are provided; and a second memory body, which includes a plurality of memory cells and a second peripheral circuit, wherein the first memory system is located in the first direction parallel to the metal layer. And the second power supply pad and the second memory bank; wherein the metal layer is located above the first and second memory banks in a second direction orthogonal to the plane of the metal layer; the first of the plurality The power supply wiring is connected to the first power supply pad to supply power to the first peripheral circuit, but not to the second peripheral circuit; the plurality of second power supply wirings are connected to the second power supply pad through the first Above the memory bank and the second memory bank, power is supplied to the second peripheral circuit, but power is not supplied to the first peripheral circuit; and the plurality of third power supply wirings are located on the second memory bank but not 1 above It is above the storage body and is electrically connected to the second power supply pad by the plurality of second power supply wirings, and supplies power to the second peripheral circuit, but not to the first peripheral circuit. The semiconductor memory device of claim 6, wherein the number of the plurality of first power supply wirings in the metal layer is less than the number of the plurality of second power supply wirings in the metal layer and the number of the plurality of first power supply wirings in the metal layer 3 The sum of the number of power wiring. The semiconductor memory device of claim 6, wherein the plurality of first power supply wiring lines are located on the first memory bank in the second direction, but not on the second memory bank; and the second plurality of The power supply wiring is located on both the first and second memory banks in the second direction. The semiconductor memory device of claim 6, wherein the first peripheral circuit is located between the first power pad and the second memory bank along the first direction; and the first, second, and third power supply wirings extend In the first direction above. According to any one of claims 6 to 9, the semiconductor memory device further includes: a first power supply circuit located between the first power supply pad and the plurality of first power supply wires; and a second power supply circuit located Between the second power supply pad and the plurality of second power supply wires. For example, any semiconductor memory device of claim 6 to 9, which further has: A plurality of first power supply circuits, each of which is located between the first power pad and each of the plurality of first power wirings; and a plurality of second power supply circuits, each of which is located on the first 2 Between the power pad and each of the above-mentioned plural second power wirings. A semiconductor memory device including: a power supply pad; a first memory bank including: a first memory array and a first peripheral circuit adjacent to each other in a first direction; and a second memory bank including: The second memory array and the second peripheral circuit adjacent to each other in the 1 direction; the first metal layer, which is located on the first and second memory banks; the first power wiring, which is in the first metal layer And is located on the first storage body, and electrically connects the power supply pad and the first peripheral circuit; the second power supply wiring, which is in the first metal layer and is located on the first and second storage bodies , The first portion of the second power supply wiring located above the first storage body is parallel to the first power supply wiring, and the second power supply wiring is electrically connected to the power supply pad and the second peripheral circuit; and a third power supply Wiring, which is in the first metal layer and located on the second memory bank, the second part of the second power supply wiring located on the second memory bank is parallel to the third power supply wiring, the third The power supply wiring electrically connects the power supply pad and the second peripheral circuit via the second power supply wiring. The semiconductor memory device of claim 12, wherein the number of the first power supply wiring in the first metal layer is less than the number of the second power supply wiring in the first metal layer and the number of the first power wiring in the first metal layer 3 The sum of the number of power wiring. The semiconductor memory device of claim 12, wherein the first memory system is located between the power pad and the second memory bank in the first direction. According to any one of claims 12 to 14, the semiconductor memory device further includes: a first power supply circuit located between the power supply pad and the first power supply wiring; and a second power supply circuit located between the power supply pad and the Between the above-mentioned second power supply wiring. The semiconductor memory device of claim 12, wherein the first power supply wiring extends in a second direction perpendicular to the first direction and is connected to the first peripheral circuit via a plurality of fourth power supply wirings, and the plurality of fourth power supplies The wiring is in the second metal layer and extends in the first direction; the second power wiring extends in the second direction, and is connected to the second peripheral circuit by a plurality of fifth power wirings, and the fifth The power supply wiring extends in the first direction in the second metal layer; and the third power supply wiring is connected to the second peripheral circuit via the plurality of fifth power supply wirings. The semiconductor memory device of claim 16, wherein the second metal layer is located on the first metal layer.

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