TWI697121B - Tri-gate field effect transistor - Google Patents

Abstract

A tri-gate field effect transistor includes a substrate, a shallow trench isolation structure, at least one fin structure, a gate feature, a source region, a drain region, and a first fin isolation air gap. The shallow trench isolation structure is formed on the substrate and defines an active area. The fin structure is placed on the substrate, and located in the active area. The gate feature spans the fin structure. The source region and the drain region are located in the active area and positioned at opposite sides of the gate feature. The first fin isolation air gap is located between the fin structure and the shallow trench isolation structure. When the tri-gate field effect transistor includes more than two fin structures, the tri-gate field effect transistor further includes an air gap between two adjacent fin structures.

Description

Three-gate field effect transistor

This disclosure relates to a three-gate field effect transistor.

There are two improvements in semiconductor structure and manufacturing process that can effectively reduce the size of the integrated circuit and increase the efficiency of the integrated circuit. One development in semiconductor structure is the introduction of a transistor structure called "Fin-field-effect transistor" (FinFET). FinFET has advantages over other types of transistors (eg, planar field effect transistors), such as better channel control, suppression of short channel effects, higher device density, and lower sub-threshold leakage current.

The FinFET includes a gate feature (which spans the protruding fin) and a pair of source/drain features (which are arranged laterally on both sides of the gate feature along the fin direction). Although FinFET has the above-mentioned advantages, it usually has a high parasitic capacitance between the gate feature and the source feature of FinFET, or between the gate feature and the drain feature. Higher parasitic capacitance will reduce various performance of FinFET (such as cutoff frequency, signal delay, etc.), which may limit the application of FinFET.

In addition, in order to further reduce the size of FinFET, FinFET structures have higher and higher fin heights, and the distance between fins (hereinafter referred to as fin pitch) is getting narrower. Please refer to Figures 1A, 1B, and 1C. In the 22-nanometer process technology (as shown in Figure 1A), the fin pitch is approximately 60 nanometers, and in the 14-nanometer process technology (as shown in Figure 1A) 1B), the fin pitch is about 42 nm, and in the 10 nm process technology (as shown in FIG. 1C), the fin pitch is about 34 nm.

As the fin pitch decreases, the width of the shallow trench isolation (STI) structure 300 filled between the two fins increases as a percentage of the fin pitch from about 58% (22 nm process technology) Up to about 64% (10nm process technology). It can be seen that the STI structure 300 filled between the two fins will affect the size and density of the entire FinFET.

An aspect of the present disclosure provides a three-gate field effect transistor including a substrate, an insulating isolation of a shallow trench structure, at least one fin structure, a gate feature, a source semiconductor feature, a drain semiconductor feature, and The first fin isolates the air gap. The insulating isolation of the shallow trench structure is located on the substrate and defines the active area. The fin structure is disposed on the substrate and located in the active area, wherein the fin structure extends along the first direction. The gate feature spans the fin structure and extends along a second direction, where the second direction is perpendicular to the first direction. The source semiconductor feature and the drain semiconductor feature are located in the active area and are disposed on opposite sides of the gate feature in the first direction. The first fin isolation air gap extends along the first direction and is located between the insulation isolation of the fin structure and the shallow trench structure.

In an embodiment of the present disclosure, the three-gate field effect transistor includes at least two fin structures, and the three-gate field effect transistor further includes at least one second fin isolation air gap. The second fin isolation air gap extends along the first direction and is located between two adjacent fin structures and between the source semiconductor feature and the drain semiconductor feature.

In an embodiment of the present disclosure, the upper part of the fin structure is not doped with impurity ions or impurity ions below the first concentration, and the lower part of the fin structure is doped with higher than the first Concentration of impurity ions at a second concentration.

In one embodiment of the present disclosure, the doping ions include P ⁺ , As ⁺ , B ₂ F ⁺ , BF ²⁺ or B ⁺ .

In one embodiment of the present disclosure, the gate features include a gate dielectric layer and a gate metal underlayer, a work function metal layer, and a gate metal layer disposed above the gate dielectric layer.

In an embodiment of the present disclosure, the gate dielectric layer includes a high-k dielectric layer, and the gate metal layer includes at least one metal layer.

In an embodiment of the present disclosure, the second fin isolation air gap is located between the gate dielectric layer and the gate metal bottom layer.

In an embodiment of the present disclosure, the gate features include spacers disposed between the gate metal underlayer and the source semiconductor features, and between the gate metal underlayer and the drain semiconductor features.

In one embodiment of the present disclosure, the gate feature includes a spaced air gap between the gate metal underlayer and the source semiconductor feature, and between the gate metal underlayer and the drain semiconductor feature.

In an embodiment of the present disclosure, the three-gate field effect transistor further includes a source contact plug and a drain contact plug, which are disposed on opposite sides of the gate feature. The bottom of the source contact plug contacts the source semiconductor feature, and the bottom of the drain contact plug contacts the drain semiconductor feature.

The above description will be described in detail in the following embodiments, and the technical solutions of the present disclosure will be further explained.

10: Three-gate field effect transistor

110: substrate

121: The first fin structure

121a: upper part

121b: Lower

122: Second fin structure

122a: upper

122b: Lower

131: The second fin isolates the air gap

132: The first fin isolates the air gap

141: Source semiconductor features

142: Drain semiconductor features

200: Gate characteristics

210: Gate metal layer

220: Gate dielectric layer

230: spacer

240: interval air gap

250: work function metal layer

260: Gate metal bottom

270: protective layer

300: Insulation isolation of shallow trench structure

300a: groove

501: Source contact plug

502: Drain contact plug

503: Gate contact plug

610: Dielectric layer

R1: punch-through barrier

D1, D2: direction

When reading in conjunction with the accompanying drawings, various aspects of the present disclosure can be better understood from the following detailed description. It should be noted that according to standard practices in the industry, many features are not drawn to scale. In fact, the size of multiple features can be arbitrarily increased or decreased in order to clarify the discussion.

FIGS. 1A to 1C are schematic cross-sectional views of three-gate field effect transistors manufactured using conventional manufacturing techniques.

FIG. 2A is a schematic perspective view of a three-gate field effect transistor according to some embodiments of the present disclosure.

FIG. 2B is a schematic cross-sectional view of a three-gate field effect transistor according to some embodiments of the present disclosure.

FIG. 2C is a schematic cross-sectional view of a three-gate field effect transistor according to some embodiments of the present disclosure.

FIG. 2D is a schematic top view of a three-gate field effect transistor according to some embodiments of the present disclosure.

FIG. 3 is a schematic cross-sectional view of a three-gate field effect transistor according to some embodiments of the present disclosure.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to limit this disclosure. For example, forming the first feature on or on the second feature in the subsequent description may include forming an embodiment of the first feature and the second feature in direct contact, and may also be included in the first feature and An embodiment in which additional features are formed between the second features so that the first feature and the second feature do not directly contact. In addition, the present disclosure may repeat element symbols and/or letters in various examples. This repetition is for simplicity and clarity, and does not itself indicate the relationship between the various embodiments and/or configurations discussed.

In addition, spatial relative terms such as "below", "below", "lower", "above", "upper" and the like are used here to simplify the description of one element or feature and another element shown in the drawings ( Or multiple elements) or features (or multiple features). In addition to the directions depicted in the drawings, spatial relative terms are intended to encompass different directions of the device in use or operation. The device can be in different directions (rotated 90 degrees or in other directions), and the spatially related descriptors used here can also be interpreted accordingly.

Please refer to Figures 2A, 2B, 2C, and 2D. FIG. 2A illustrates a three-dimensional schematic diagram of a three-gate field effect transistor 10 according to some embodiments of the present disclosure. FIGS. 2B and 2C illustrate lines XX′ and Y along line 2A, respectively. -Y' cross-sectional schematic view of the three-gate field effect transistor 10, and FIG. 2D shows a top view of the three-gate field effect transistor 10 Schematic. It should be noted that in FIG. 2A, the source contact plug 501, the drain contact plug 502, the gate contact plug 503, and the dielectric layer 610 are omitted (as shown in FIGS. 2C and 2D) In order to understand the relationship between the elements more clearly. The three-gate field effect transistor 10 includes a substrate 110, a first fin structure 121 and a second fin structure 122, a gate feature 200, a source semiconductor feature 141 and a drain semiconductor feature 142, and a shallow trench structure insulation Isolate 300.

The insulating isolation 300 of the shallow trench structure is located on the substrate 110, and the first fin structure 121, the second fin structure 122, the source semiconductor feature 141, and the drain semiconductor feature 142 are located on the insulating isolation 300 of the shallow trench structure external. Specifically, the insulating isolation 300 of the shallow trench structure has a trench 300a (as shown in FIG. 2B). The trench 300a defines an active area, and the first fin structure 121, the second fin structure 122, the source semiconductor feature 141, and the drain semiconductor feature 142 are located in this active area. In some embodiments, the insulating material of the shallow trench isolation 300 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or silicon oxynitride (SiOCN).

In some embodiments, the substrate 110 may be a silicon substrate. In some other embodiments, the substrate 110 may be made of some other suitable element semiconductors, such as germanium; or made of some suitable compound semiconductors, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide ; Or made of some or suitable alloy semiconductors, such as silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, the substrate 110 may be a silicon-on insulator (SOI) substrate. In addition, the substrate 110 may contain doped impurities (e.g. Such as P-type or N-type) various areas.

As shown in FIGS. 2A and 2B, the first fin structure 121 and the second fin structure 122 are disposed on the substrate 110 and located in the trench 300a. The first fin structure 121 and the second fin structure 122 may be made of the same material as the substrate 110. In some embodiments, the first fin structure 121 and the second fin structure 122 are made of silicon. In some embodiments, the first fin structure 121 and the second fin structure 122 may be appropriately doped with P-type or N-type impurities.

It should be understood that although two fin structures (ie, the first fin structure 121 and the second fin structure 122) are shown in FIGS. 2A and 2B, the number of fin structures is not limited to two Pcs. The number can be one, three, four or more.

In some embodiments, the first fin structure 121 and the second fin structure 122 may be formed by the following processes. After forming the insulating isolation 300 of the shallow trench structure, an etching mask is formed on a part of the active region of the bulk substrate. The etching mask is used to etch (for example, using a dry etching process) the bulk substrate. Accordingly, since a part of the bulk substrate is covered by the etching mask, it is retained after the etching process, thereby forming the first fin structure 121 and the second fin structure 122.

As shown in FIGS. 2A and 2B, the first fin structure 121 and the second fin structure 122 extend along the first direction D1. Specifically, the first fin structure 121 and the second fin structure 122 extend from a sidewall of the source semiconductor feature 141 to a sidewall of the drain semiconductor feature 142.

The gate feature 200 extends along the second direction D2 and spans the first fin structure 121 and the second fin structure 122. In some embodiments, the first The second direction D2 is substantially perpendicular to the first direction D1. The gate feature 200 can be any suitable known gate structure. For example, the gate feature 200 can include a gate dielectric layer 220 and a gate metal underlayer 260 disposed above the gate dielectric layer 220, and a work function. The metal layer 250, the protective layer 270, and the gate metal layer 210, but the invention is not limited thereto. In some embodiments, the gate dielectric layer 220, the gate metal bottom layer 260, the work function metal layer 250, the protective layer 270, and the gate metal layer 210 may include a single layer or a multilayer structure.

As shown in FIG. 2B, a part of the gate dielectric layer 220 and a part of the gate metal underlayer 260 are filled in the trench 300a. In detail, the gate dielectric layer 220 is conformally formed on the upper surface and sidewalls of the first and second fin structures 121 and 122, the upper surface of the substrate 110, and the insulation isolation of the shallow trench structure 300 on the upper surface and side walls. The gate metal bottom layer 260 covers the upper surface of the insulating isolation 300 of the shallow trench structure and covers the upper portions 121a and 122a of the first fin structure 121 and the second fin structure 122. It should be noted that the gate metal bottom layer 260 does not completely cover the sidewalls of the isolation trench 300 of the shallow trench structure, and also does not fill the lower portion 121b of the first fin structure 121 and the lower portion 122b of the second fin structure 122 Thus, a first fin isolation air gap 132 and a second fin isolation air gap 131 are generated.

In the conventional FinFET structure, the fins are filled with insulating materials (such as the STI structure 300 in FIGS. 1A, 1B, and 1C). As mentioned above, the STI structure 300 filled between the two fins will affect the size of the FinFET. However, the first fin structure 121 and the second fin structure 122 of the tri-gate field effect transistor 10 of the present invention do not need to be filled with an insulating material (as shown in FIG. 2B), so the fins can be effectively reduced spacing. specific In other words, according to various embodiments of the present invention, by adjusting the etching process and the fin spacing, the gate dielectric layer 220 can be conformally formed on the two fins, and the gate metal bottom layer 260 can only cover the two fins The upper part of the fin can not fill the gap between the two fins. Accordingly, the first fin isolation air gap 132 and the second fin isolation air gap 131 are formed.

In some embodiments, the gate dielectric layer 220 includes a single layer or multiple layers of high-k (dielectric constant) dielectric layers. Each high-k dielectric layer includes a material having a "k" value greater than about 4.0. In some embodiments, each high-k dielectric layer may be formed of at least one material selected from Al ₂ O ₃ , HfAlO, HfAlON, AlZrO, HfO ₂ , HfSiO _x , HfAlO _x , HfZrSiO _x , HfSiON, LaAlO ₃ , ZrO ₂ or a combination thereof. The high-k dielectric may be formed using a suitable process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination thereof. Electrical layer.

In some embodiments, the gate metal underlayer 260 includes metal nitrides, such as TiN, TaN, TiAlN, TaAlN, etc., but not limited thereto. The gate metal underlayer 260 may be formed using a suitable process such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, or a combination thereof.

In some embodiments, aluminum (Al) may be used as the material of the work function metal layer 250, and the aluminum (Al) concentration at the bottom of the work function metal layer 250 is higher, while the aluminum (Al) concentration at the top of the work function metal layer 250 The aluminum (Al) concentration is lower than the bottom of the work function metal layer 250. An embodiment of an Al-base work function metal layer has the general formula MAlX, where M may be hafnium (Hf), titanium (Ti), tantalum (Ta), zirconium (Zr), niobium (Nb), etc., X It can be carbon (C), nitrogen (N), silicon (Si), etc. In some embodiments, silicon (Si) may be used as the material of the work function metal layer 250, and the silicon (Si) concentration at the bottom of the work function metal layer 250 is higher, while the silicon (Si) concentration at the top of the work function metal layer 250 The silicon (Si) concentration at the bottom of the work function metal layer 250 is lower. An embodiment of the metal silicide work function metal layer has the general formula MSi _y , where M can be hafnium (Hf), titanium (Ti), tantalum (Ta), zirconium (Zr), tungsten (W), lanthanum (La) or Similar to other materials, y represents any number of silicon in the composition that is greater than zero. Other materials having a vacuum work function value of less than about 4.4 eV may also be used for the material of the work function metal layer 250. Examples of suitable materials for the work function metal layer include, but are not limited to, titanium (Ti), tantalum (Ta), hafnium (Hf), zirconium (Zr), and combinations thereof.

In some embodiments, the protective layer 270 includes metal nitrides, such as TiN, TaN, TiAlN, TaAlN, etc., but not limited thereto. The protective layer 270 may be formed using a suitable process such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, or a combination thereof.

In some embodiments, the gate metal layer 210 may include at least one metal layer or polysilicon layer. For example, the gate metal layer 210 may include polysilicon, Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi, or a combination thereof. Similarly, a suitable process such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or a combination thereof may be used to form the gate metal layer 210.

As mentioned above, the number of fin structures is not limited to two, but may be one, three, four or more. Therefore, when the number of fin structures When there are two or more, the three-gate field effect transistor 10 may include at least one second fin isolation air gap 131 between two adjacent fin structures, and between the source semiconductor feature 141 and the drain Between semiconductor features 142. In addition, when the three-gate field effect transistor 10 includes a plurality of second fin isolation air gaps 131, the second fin isolation air gaps 131 are arranged along the second direction D2.

Taking the embodiment of FIG. 2B as an example, the three-gate field effect transistor 10 includes a second fin isolation air gap 131, and the second fin isolation air gap 131 is located between the first fin structure 121 and the second fin The structure 122 is located between the source semiconductor feature 141 and the drain semiconductor feature 142. Specifically, the second fin isolation air gap 131 is located between the lower portion 121b of the first fin structure 121 and the lower portion 122b of the second fin structure 122, and extends from a sidewall of the source semiconductor feature 141 to the drain semiconductor feature One side wall of 142. More specifically, the second fin isolation air gap 131 is located between the gate dielectric layer 220 and the gate metal bottom layer 260.

In addition, as shown in FIG. 2B, the first fin isolation air gap 132 is located between the first fin structure 121 and the insulating isolation 300 of the shallow trench structure, and between the second fin structure 122 and the shallow trench structure. Between 300 insulation. Specifically, the first fin isolation air gap 132 is located between the lower portion 121b of the first fin structure 121 and the insulating isolation 300 of the shallow trench structure, and the lower portion 122b of the second fin structure 122 and the shallow trench structure Between the insulating isolations 300, and extending from a sidewall of the source semiconductor feature 141 to a sidewall of the drain semiconductor feature 142. More specifically, the first fin isolation air gap 132 is located between the gate dielectric layer 220 and the gate metal bottom layer 260.

As mentioned earlier, compared to flat field effect transistors, FinFET Has a high parasitic capacitance. Specifically, as shown in FIG. 2C, since the source semiconductor feature 141 and the drain semiconductor feature 142, the source contact plug 501 and the drain contact plug 502 are closely adjacent to the gate feature 200, and the first fin The plate structure 121 is closely adjacent to the second fin structure 122 (as shown in FIG. 2B ), so a higher parasitic capacitance may be generated. In the conventional FinFET structure, a low dielectric constant material is used to form an insulating layer between the source/drain feature and the gate feature, and between adjacent fins to improve device performance and reduce parasitic capacitance ( (STI structure 300 in FIGS. 1A, 1B, and 1C). For example, the low dielectric constant material is silicon dioxide (its dielectric constant is about 3.9). According to various embodiments of the present invention, the air-filled second fin isolation air gap 131 is formed between the first fin structure 121 and the second fin structure 122, and the air-filled first fin isolation air gap 132 is formed between the first fin structure 121 and the insulating isolation 300 of the shallow trench structure, and the second fin structure 122 and the insulating isolation 300 of the shallow trench structure (as shown in FIG. 2B ). Therefore, compared with the conventional FinFET structure, air with a lower dielectric constant (with a dielectric constant of about 1) can more effectively reduce the parasitic capacitance between the fins.

In some embodiments, doping can be performed through an implantation process to implant appropriate impurity ions to form a punch-through stopper R1. The through barrier layer R1 can increase the resistivity, thereby reducing current leakage. Specifically, through the implantation process, the lower portion 121b of the first fin structure 121, the lower portion 122b of the second fin structure 122, and the portion of the substrate 110 exposed by the trench 300a may be doped with impurity ions. First, the upper portion 121a of the first fin structure 121 and the upper portion 122a of the second fin structure 122 are not doped with impurity ions or doped with impurity ions with a concentration of 10 ¹⁸ /cm ³ or less as channel regions. In some embodiments, the impurity ions are, for example, P ⁺ , As ⁺ , B ₂ F ⁺ , BF ²⁺ or B ⁺ . Secondly, the lower portion 121b of the first fin structure 121 and the lower portion 122b of the second fin structure 122 are doped with a higher concentration of impurity ions than the upper portion 121a and the upper portion 122a, and the concentration thereof is about 10 ¹⁷ /cm ³ to 10 ²⁰ / between cm ³ .

As shown in FIGS. 2A and 2C, the source semiconductor feature 141 and the drain semiconductor feature 142 are located on opposite sides of the gate feature 200 in the first direction D1. In some embodiments, the source semiconductor feature 141 and the drain semiconductor feature 142 may be formed by the following process. After forming the gate feature 200, etching is performed to create a cavity at the position where the source semiconductor feature 141 and the drain semiconductor feature 142 are to be formed. After the cavity is formed, an epitaxial growth process is applied to epitaxially grow the source semiconductor feature 141 and the drain semiconductor feature 142 in the cavity.

The source semiconductor feature 141 and the drain semiconductor feature 142 may include any acceptable materials, such as materials suitable for N-type FinFET and/or P-type FinFET. For example, in N-type FinFET, source semiconductor feature 141 and drain semiconductor feature 142 may include SiC, SiCP, SiP, etc., while in P-type FinFET, source semiconductor feature 141 and drain semiconductor feature 142 may Including SiGe, SiGeB, Ge, GeSn and so on.

As shown in FIGS. 2C and 2D, the dielectric layer 610 is formed on the source semiconductor feature 141 and the drain semiconductor feature 142. In some embodiments, the dielectric layer 610 includes fluorinated silica glass (FSG), phosphorosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon doped Silicon oxide (SiO _x C _y ), polyimide, etc., but not limited to this. The dielectric layer 610 may be formed using a suitable process such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, or a combination thereof.

In some embodiments, the three-gate field effect transistor 10 may include other dielectric layers (not shown) formed on the dielectric layer 610 and covering the gate features 200. The source contact plug 501, the drain contact plug 502, and the gate contact plug 503 pass through the dielectric layer 610 and the other dielectric layers (not shown) to contact the source semiconductor feature 141 and the drain, respectively Semiconductor feature 142, and gate feature 200. In some embodiments, the source contact plug 501, the drain contact plug 502, and the gate contact plug 503 may each include a metal material, for example, Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN , TaN, NiSi, CoSi or a combination thereof.

In some embodiments, the source contact plug 501, the drain contact plug 502, and the gate contact plug 503 can be formed by the following process. A patterned mask layer is formed on the dielectric layer 610 and the other dielectric layers, wherein the patterned mask layer has openings aligned with each area where the contact plug is to be formed. Using the patterned mask layer as an etching mask, an etching process is performed to etch the dielectric layer 610 and the other dielectric layers, thereby exposing the source semiconductor feature 141, the drain semiconductor feature 142, and the gate feature 200. Next, using an appropriate process such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or a combination thereof, the dielectric layer 610 and the etched portions of the other dielectric layers are refilled with the metal materials described above.

In some embodiments, the gate feature 200 includes a spacer 230, disposed between the gate metal underlayer 260 and the source semiconductor feature 141, and between the gate metal underlayer 260 and the drain semiconductor feature 142 (as shown in FIG. 2C). In some embodiments, the spacer 230 includes silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxynitride (SiOCN), or other suitable materials. In some embodiments, the spacer 230 may be formed on the sidewalls of the gate metal underlayer 260, and the gate metal underlayer 260, work function by using techniques such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, or other suitable techniques. At least one of the above materials is deposited on the metal layer 250, the protective layer 270, and the gate metal layer 210. Next, an etching process is performed on the deposited material, and a spacer 230 is formed on the sidewall of the gate metal bottom layer 260.

Please refer to Figure 3. FIG. 3 is a schematic cross-sectional view of the three-gate field effect transistor 10a taken along the line XX′ of FIG. 2A according to other embodiments of the present disclosure. It should be noted that in FIG. 3, elements that are the same as or similar to those in FIG. 2C are given the same symbols, and related descriptions are omitted. The three-gate field effect transistor 10a in FIG. 3 is similar to the three-gate field effect transistor 10 in FIG. 2C, the difference is that the space gap 240 of the three-gate field effect transistor 10a replaces the three-gate field effect The spacer 230 of the transistor 10.

As described above, since the source semiconductor feature 141, the drain semiconductor feature 142, the source contact plug 501, and the drain contact plug 502 are closely adjacent to the gate feature 200, the source semiconductor feature 141 (or A higher parasitic capacitance may be generated between the drain semiconductor feature 142) and the gate metal layer 210, and between the source contact plug 501 (or the drain contact plug 502) and the gate metal layer 210. In the three-gate field effect transistor 10a, The spacer air gap 240 replaces the spacer 230 of the three-gate field effect transistor 10. Specifically, a spaced air gap 240 filled with air (which has a lower dielectric constant) separates the source semiconductor feature 141 and the source contact plug 501 from the gate metal layer 210, and the drain semiconductor feature 142 and The drain contact plug 502 is separated from the gate metal layer 210. Therefore, the parasitic capacitance between the source semiconductor feature 141 (or the drain semiconductor feature 142) and the gate metal layer 210, and the source contact plug 501 (or the drain contact plug 502) and the gate can be more effectively reduced The parasitic capacitance between the polar metal layer 210.

In some embodiments, the spacer air gap 240 may be formed by the following process. A chemical mechanical polishing process is performed to remove the upper portion of the dielectric layer 610 to expose the spacer 230 (as shown in FIG. 2C). Next, an etching process is performed to remove the spacer 230, thereby forming a spacer air gap 240 (as shown in FIG. 3). For example, when the spacer 230 (shown in FIG. 2C) includes a nitride such as silicon nitride (SiN), phosphoric acid may be used to perform an etching process to remove the spacer 230.

It can be known from the above embodiments of the invention that the three-gate field effect transistor disclosed herein includes a fin isolation air gap disposed between the two fins, so that the parasitic capacitance between the fins can be effectively reduced. The three-gate field effect transistor disclosed here also includes the source/drain semiconductor features and the spaced air gap between the source/drain contact plug and the gate metal layer, so the source/ The parasitic capacitance between the drain semiconductor feature and the gate metal layer, and the parasitic capacitance between the source/drain contact plug and the gate metal layer.

Compared with the conventional FinFET structure, when manufacturing the three-gate field effect transistor of the present invention, it is not necessary to fill a low dielectric constant material between the two fins Therefore, the size of the three-gate field effect transistor can be greatly reduced, and the manufacturing process can be simplified. In addition, the three-gate field effect transistor disclosed herein also includes a punch-through barrier layer, so current leakage current can be reduced.

The above outlines the features of several embodiments, so that those skilled in the art can better understand the present disclosure. Those skilled in the art should understand that this disclosure can easily be used as a basis for designing or modifying other processes and structures in order to implement the same purposes and/or achieve the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent structures do not deviate from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations in this document can be made without departing from the spirit and scope of this disclosure.

10: Three-gate field effect transistor

110: substrate

121: The first fin structure

122: Second fin structure

141: Source semiconductor features

142: Drain semiconductor features

200: Gate characteristics

210: Gate metal layer

220: Gate dielectric layer

230: spacer

250: work function metal layer

260: Gate metal bottom

270: protective layer

300: Insulation isolation of shallow trench structure

R1: punch-through barrier

D1, D2: direction

Claims (9)

A three-gate field effect transistor includes: a substrate; an insulating isolation of a shallow trench structure located on the substrate and defining an active area; at least one fin structure disposed on the substrate and located on the In the active area, the at least one fin structure extends along a first direction; a gate feature spans the at least one fin structure and extends along a second direction, the second direction and the first direction Vertical; a source semiconductor feature and a drain semiconductor feature, located in the active area, and located on opposite sides of the gate feature in the first direction; and a first fin isolation air gap, along Extending in the first direction and located between the insulating isolation of the at least one fin structure and the shallow trench structure, wherein the gate feature includes a gate dielectric layer and a gate dielectric layer disposed above the gate dielectric layer A gate metal bottom layer, wherein the first fin isolation air gap is located between the gate dielectric layer and the gate metal bottom layer. The three-gate field effect transistor as described in item 1 of the patent application scope, wherein the three-gate field effect transistor includes at least two fin structures, and further includes: at least one second fin isolation air gap, along It extends in the first direction and is located between two adjacent fin structures and between the source semiconductor feature and the drain semiconductor feature. The three-gate field effect transistor as described in item 1 of the patent application scope, wherein an upper portion of the at least one fin structure is not doped with impurity ions or doped with impurity ions below a first concentration, and the at least one The lower part of the fin structure is doped with impurity ions at a second concentration higher than the first concentration. The three-gate field effect transistor as described in item 3 of the patent application scope, wherein the impurity ion is P ⁺ , As ⁺ , B ₂ F ⁺ , BF ²⁺ or B ⁺ . The three-gate field effect transistor as described in item 1 of the patent application scope, wherein the gate feature further includes a work function metal layer and a gate metal layer disposed above the gate metal bottom layer. The three-gate field effect transistor as described in item 5 of the patent application range, wherein the gate dielectric layer includes a high-k dielectric layer, and the gate metal layer includes at least one metal layer. The three-gate field effect transistor as described in item 5 of the patent application range, wherein the gate feature includes a spacer disposed between the gate metal underlayer and the source semiconductor feature, and the gate metal underlayer And the drain semiconductor feature. The three-gate field effect transistor as described in item 5 of the patent application scope, wherein the gate characteristic includes a spaced air gap, which is disposed on the gate Between the bottom metal layer and the source semiconductor feature, and between the gate metal bottom layer and the drain semiconductor feature. The three-gate field effect transistor as described in item 1 of the patent application scope further includes: a source contact plug and a drain contact plug, which are disposed on opposite sides of the gate feature, wherein the source electrode The bottom of the contact plug contacts the source semiconductor feature, and the bottom of the drain contact plug contacts the drain semiconductor feature.

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