TWI692116B - Light-emitting element - Google Patents

Abstract

A light-emitting device, includes: a first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; an active layer formed between the second and the third semiconductor layers; an exposed region, passing through the third semiconductor layer and the active layer to expose a first surface of the first semiconductor layer and a second surface of the second semiconductor layer; and a first electrode, formed in the exposed region and contacting the first surface and the second surface; wherein the first semiconductor layer and the second semiconductor layer have different resistances.

Description

Light emitting element

The present invention relates to a light-emitting device, and more specifically, to a light-emitting element with high brightness.

Light-emitting diode (LED) is a photoelectric element composed of P-type semiconductor and N-type semiconductor. It emits light through the combination of carriers on the PN junction, plus it has small size, low power consumption and long life. , Fast response and other advantages, widely used in optical display devices, traffic signs, data storage devices, communication devices, lighting devices and medical equipment.

A light emitting device includes: a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; an active layer on the second semiconductor layer and the first Between three semiconductor layers; an exposed area, passing through the third semiconductor layer and the active layer, exposing a first surface of the first semiconductor layer and a second surface of the second semiconductor layer; and a first electrode, located in the exposed area , And contact the first surface and the second surface; wherein, the first semiconductor layer and the second semiconductor layer have different resistance values.

The embodiments of the application will be described in detail and drawn in the drawings, and the same or similar parts will appear in the drawings and descriptions with the same numbers.

FIG. 1A is a variation A of a top view of a light-emitting element 1 disclosed in the first embodiment of the present application. Fig. 1B is a side view along the B-B' cross-section of Modification A in Fig. 1A, and Fig. 1C is a partial enlarged view of the region R in Fig. 1B.

Referring to FIGS. 1A to 1C, the light-emitting element 1 of Variation A in the first embodiment includes a substrate 10, and a semiconductor structure 20 is located on the upper surface 10a of the substrate 10. The semiconductor structure 20 includes a first semiconductor layer 201, a second semiconductor layer 202, an active layer 204, and a third semiconductor layer 203 in sequence from the upper surface 10a of the substrate 10. The semiconductor structure 20 includes an exposed region 28 extending downward from the upper surface 203a of the third semiconductor layer 203, passing through the third semiconductor layer 203 and the active layer 204, exposing the upper surface TS1 of the first semiconductor layer 201 and The side surface LS1, and the upper surface TS2, upper side surface LS2, and lower side surface LS2' of the second semiconductor layer 202, wherein the top surface TS1 of the first semiconductor layer 201 has a width W1 as viewed from the side of the cross section; The side surface LS1 of the first semiconductor layer 201 and the lower side surface LS2' of the second semiconductor layer 202 are connected, and the upper surface TS1 of the first semiconductor layer 201 and the upper surface TS2 of the second semiconductor layer 202 are substantially parallel.

In an embodiment of the present application, the exposed region 28 may be formed by multiple etching processes. For example, in the first etching process, a part of the area is selected from the upper surface 203a of the third semiconductor layer 203, toward The third semiconductor layer 203, the active layer 204, and the second semiconductor layer 202 underneath are removed to a depth of the second semiconductor layer 202, exposing the upper surface TS2 and the upper side surface LS2 of the second semiconductor layer 202. In one embodiment, the etching depth is from 0.8 to 1.5 μm from the upper surface 203a. Next, in the second etching process, a part of the area is selected from the upper surface TS2 of the second semiconductor layer 202, and the second semiconductor layer 202 and the first semiconductor layer 201 below it are removed downwards until the first semiconductor One depth of the layer 201 exposes the upper surface TS1 and the side surface LS1 of the first semiconductor layer 201 and the lower side surface LS2' of the second semiconductor layer 202. In one embodiment, the etching depth is between 0.2-1 μm from the top surface TS2 of the second semiconductor layer 202. In this embodiment, the upper surface TS1 of the first semiconductor layer 201 is closer to the substrate 10 than the interface between the first semiconductor layer 201 and the second semiconductor layer 202.

In an embodiment of the present application, the substrate 10 includes an insulating substrate or a conductive substrate. When the substrate 10 is a conductive substrate, there will be an insulating region between the substrate 10 and the semiconductor structure 20 thereon to avoid the gap between the two Leakage current is generated. The insulating substrate includes a sapphire (Al ₂ O ₃ ) wafer for growing indium gallium nitride (InGaN); the conductive substrate includes a gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), or To grow InGaN gallium nitride (GaN) wafers, silicon (Si) wafers or silicon carbide (SiC) wafers. The upper surface 10a of the semiconductor structure 20 to be formed on the substrate 10 may include a patterned structure 101, thereby improving the epitaxial quality of the semiconductor structure 20 or improving the light extraction efficiency of the light emitting element 1.

In one embodiment of the present application, another semiconductor layer may be included between the substrate 10 and the first semiconductor layer 201, for example, including a buffer structure (not shown). The buffer structure can alleviate the mismatch in lattice constant between the substrate 10 and the semiconductor structure 20, or help stress relief to improve epitaxial quality.

The method of forming the semiconductor structure 20 including the buffer structure on the substrate 10 includes a deposition method. The deposition includes epitaxy and physical vapor deposition (PVD). Epitaxy includes molecular beam epitaxy (MBE), organometallic vapor phase epitaxy (MOVPE), vapor phase epitaxy (VPE) or liquid phase epitaxy (LPE); physical vapor deposition includes vapor deposition (evaporator) or sputtering.

In the present application, the first semiconductor layer 201, the second semiconductor layer 202, the active layer 204, or the third semiconductor layer 203 in the semiconductor structure 20 may be a single layer or include a plurality of sub-layers. The materials of the semiconductor structure 20 include group III-Ⅴ semiconductor materials, such as Al _x In _y Ga _(1-xy) N or Al _x In _y Ga _(1-xy) P, where 0≦x, y≦1; (x+ y)≦1. According to the material of the active layer 204, when the semiconductor structure 20 material is AlInGaP series material, it can emit red light with a wavelength between 610 nm and 650 nm, and green light with a wavelength between 530 nm and 570 nm. When the structure 10 material is InGaN series material, it can emit blue light with a wavelength between 450 nm and 490 nm, or when the semiconductor structure 20 material is AlN, AlGaN, AlGaInN series material, it can emit a wavelength between 400 nm and 250 Blue-violet light or invisible ultraviolet light between nm. The choice of III-Ⅴ semiconductor materials is not limited to this. Materials other than the above can also be selected to generate invisible light in other wavelength bands, such as infrared light or far infrared light. The active layer 204 may be a single heterostructure (single heterostructure, SH), a double heterostructure (DH), a double-side double heterostructure (DDH), a multi-quantum well structure (multi-quantum well, MQW). The active layer material may be a semiconductor undoped with dopants, doped with p-type dopants, or doped with n-type dopants.

The first and second semiconductor layers 201 and 202 have the same conductivity, electrical property, polarity or dopant, and the third semiconductor layer 203 and the first and second semiconductor layers 201 and 202 have different conductivity and electrical properties , Polarity or dopant. Taking this embodiment as an example, the third semiconductor layer 203 is p-type to provide holes, and the first and second semiconductor layers 201 and 202 are n-type to provide electrons, so that electrons and holes can recombine in the active layer 204 to Generate light. In one embodiment, the thickness of the second semiconductor layer 202 is less than the thickness of the first semiconductor layer 201, for example, the thickness of the second semiconductor layer 202 is less than 1 μm. Among them, the first and second semiconductor layers 201 and 202 have different resistance values, and their materials and implementations will be described in detail later.

The resistance of the first semiconductor layer 201 can be higher or lower than that of the second semiconductor layer 202. In an embodiment, the first and second semiconductor layers 201 and 202 include the same material and the same conductive dopant at different doping concentrations; here, the same material refers to the same composition of materials other than the dopant in the semiconductor . For example, the first semiconductor layer 201 and the second semiconductor layer 202 are respectively n-type GaN with different silicon doping concentrations. In one embodiment, the resistance of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202, the first semiconductor layer 201 is n-type GaN with a silicon doping concentration of 2×10 ¹⁹ cm ^-3 , and the second semiconductor layer 202 is silicon N-type GaN with a doping concentration of 1.3×10 ¹⁹ cm ^-3 ; in another embodiment, the resistance of the first semiconductor layer 201 is greater than that of the second semiconductor layer 202, and the first semiconductor layer 201 is a silicon doping concentration of 8×10 ¹⁸ cm ^-3 n-type GaN, the second semiconductor layer 202 is n-type GaN with a silicon doping concentration of 1.3×10 ¹⁹ cm ^-3 .

In another embodiment, the first and second semiconductor layers 201 and 202 include different materials, for example, the first semiconductor layer 201 is n-type AlGaN, and the second semiconductor layer 202 is n-type GaN; or the first and second The semiconductor layers 201 and 202 are respectively n-type AlGaN with different aluminum contents, wherein the aluminum content of the first semiconductor layer 201 is higher than that of the second semiconductor layer 201. In one embodiment, the resistance of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202. For example, the first semiconductor layer 201 is an n-type Al _x Ga _1-x N with a silicon doping concentration of a×10 ¹⁹ cm ^-3 The second semiconductor layer 202 is an n-type Al _y Ga _1-y N with a silicon doping concentration of b×10 ¹⁹ cm ⁻³ , where a>b, 10>a>0.5, and x>y. In addition, the first and second semiconductor layers 201 and 202 may further have the same conductive dopant with different or the same doping concentration. In an embodiment, the resistance value of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202. For example, the first semiconductor layer 201 is n-type AlGaN with a silicon doping concentration of 2×10 ¹⁹ cm ^-3 , and the second semiconductor layer 202 It is n-type GaN with a silicon doping concentration ranging from 5×10 ¹⁸ cm ^-3 to 7×10 ¹⁸ cm ^-3 .

In another embodiment, the first semiconductor layer 201 may include a superlattice structure, for example, a superlattice structure of two sublayers of AlGaN/GaN, or a semiconductor formed by modulation doping in a single semiconductor material Floor.

A first electrode 30 is located in the exposed region 28 and simultaneously contacts the first semiconductor layer 201 and the second semiconductor layer 202 with different resistances. As shown in FIGS. 1B and 1C, the first electrode 30 contacts the upper surface TS1 and the side surface LS1 of the first semiconductor layer 201, and the upper surface TS2 and the lower side surface LS2' of the second semiconductor layer 202, and the first electrode 30 There is a gap with the upper side surface LS2. In this embodiment, the first electrode 30 is a first wire bonding pad with a width W _N in the top view, and the top surface TS1 and the first electrode 30 have a similar pattern shape. The upper surface TS1 includes a first contact region C ₁ that contacts the first electrode 30, and the upper surface TS2 includes a second contact region C _{2 that} contacts the first electrode 30. The area of the first contact area C ₁ is not equal to the area of the second contact area C ₂ . In Variation A of the first embodiment, the width W _{N of the} first electrode 30 is greater than the width W ₁ of the upper surface TS1, the area of the first contact region C ₁ is equal to the area of the upper surface TS1, and the area of the first contact region C ₁ is greater than The area of the second contact area C ₂ . In an embodiment, the resistance of the first semiconductor layer 201 is greater than that of the second semiconductor layer 202, and the area of the first contact region C ₁ is greater than or equal to the area of the second contact region C ₂ . In one embodiment, the resistance of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202, and the area of the first contact region C ₁ is larger than the area of the second contact region C ₂ .

In another embodiment of the present application, the area of the first contact area C ₁ is smaller than the area of the second contact area C ₂ . In one embodiment, the resistance of the first semiconductor layer 201 is greater than that of the second semiconductor layer 202, and the area of the first contact region C ₁ is smaller than the area of the second contact region C ₂ . In one embodiment, the resistance of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202, and the area of the first contact region C ₁ is less than or equal to the area of the second contact region C ₂ .

The upper surface 203a of the third semiconductor layer 203 has a current blocking layer 60. In one embodiment, the current blocking layer 60 includes an opening 60a exposing a portion of the upper surface 203a. The current blocking layer 60 may comprise a single layer of dielectric material or a stack of dielectric materials composed of alternating stacks of multiple dielectric materials with different refractive indices. The materials may include but are not limited to silicon oxide (SiO _X ) and silicon nitride (Si ₃ N ₄ ), aluminum oxide (Al ₂ O ₃ ), titanium oxide (Ti _X O _Y ), tantalum pentoxide (Ta ₂ O ₅ ), niobium oxide (Nb ₂ O ₅ ), zirconium oxide (ZrO ₂ ) Or a combination of the aforementioned materials. The current blocking layer 60 is transparent to the light emitted by the active layer 204.

A transparent conductive layer 18 covers the upper surface 203a of the third semiconductor layer 203, is in electrical contact with the third semiconductor layer 203, and simultaneously covers the current blocking layer 60. The transparent conductive layer 18 may be a metal or a transparent conductive material, wherein the metal may be selected from a thin metal layer with light transmission, the transparent conductive material is transparent to the light emitted by the active layer 204, including indium tin oxide (ITO), Alumina zinc (AZO), gallium zinc oxide (GZO), or indium zinc oxide (IZO) and other materials. The transparent conductive layer 18 has an opening 18a corresponding to the opening 60a of the current blocking layer 60. In one embodiment, the transparent conductive layer 18 only covers the upper surface 203a of the third semiconductor layer 203 and is in electrical contact with the third semiconductor layer 203, but does not cover the current blocking layer 60, the transparent conductive layer 18 and the current blocking layer There is a gap between 60.

A second electrode 40 is located on the current blocking portion 60, the transparent conductive layer 18 and the third semiconductor layer 203, and is electrically connected to the transparent conductive layer 18 and the third semiconductor layer 203. The second electrode 40 includes a second wire bonding pad 401 and a second extension electrode 402 extending from the second wire bonding pad 401. Compared to the second extension electrode 402, the first bonding pad of the first electrode 30 and the second bonding pad 401 of the second electrode 40 have a wider width, and can be used for bonding and external power supply or external electronics in the subsequent process The components are electrically connected. The second electrode 40 is located at a corresponding position of the current blocking portion 60. The outer contour of the second electrode 40 may be equal to or slightly smaller than the outer contour of the current blocking portion 60. In this embodiment, the position of the second bonding pad 401 corresponds to the opening 60a of the current blocking layer 60 and the opening 18a of the transparent conductive layer 18, and passes through these openings to contact the third semiconductor layer 203. The materials of the first electrode 30 and the second electrode 40 include metals such as chromium (Cr), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), Metals such as rhodium (Rh) or platinum (Pt) or alloys or laminates of the above materials. On the surface of the first electrode 30 and the second electrode 40 close to the semiconductor structure 20, a metal material with higher reflectivity can be selected to form a mirror to enhance light extraction. Here, the higher reflectivity refers to the active layer The wavelength of the light emitted by 204 has a reflectivity of more than 80%. Metal materials with higher reflectivity include, for example, aluminum (Al) or silver (Ag).

In another embodiment of the present application, the light-emitting element 1 does not have the current blocking layer 60, and the second bonding pad 401 contacts the third semiconductor layer 203 through the opening 18a of the transparent conductive layer 18.

In another embodiment of the present application, the current blocking layer 60 does not have an opening 60a, the transparent conductive layer 18 covers part of the upper surface and the side walls of the current blocking layer 18, and the opening 18a of the transparent conductive layer 18 exposes the second bonding pad 401 The upper surface of the current blocking layer 60 directly below makes the second bonding pad 401 contact the current blocking layer 60 via the opening 18a. The second bonding pad 401 may contact the transparent conductive layer 18 on the sidewall of the opening 18a, or the second bonding pad 401 may not contact the transparent conductive layer 18 on the sidewall of the opening 18a.

In another embodiment of the present application, the current blocking layer 60 does not have an opening 60a, the transparent conductive layer 18 covers part of the upper surface and the side wall of the current blocking layer 18, and the opening 18a of the transparent conductive layer 18 is exposed on the second bonding pad The upper surface and the side wall of the current blocking layer 60 directly below 401 make the second bonding pad 401 contact the current blocking layer 60 but not the transparent conductive layer 18.

In another embodiment of the present application, the current blocking layer 60 is only disposed under the second bonding pad 401, and the current blocking portion 60 is not provided under the second extension electrode 402.

In another embodiment of the present application, the opening 18a of the transparent conductive layer 18 may be greater than, less than, or equal to the width of the second bonding pad 401. When the opening 18 a of the transparent conductive layer 18 is larger than the width of the second bonding pad 401, the second bonding pad 401 does not contact the transparent conductive layer 18.

In another embodiment of the present application, the opening 60a of the current blocking layer 60 may be greater than, less than, or equal to the opening 18a of the transparent conductive layer 18.

A reflective structure (not shown) can be selectively disposed on the lower surface 10b of the substrate 10 to reflect the light from the semiconductor structure 20 and improve the light emitting efficiency of the light emitting element 1. The material of the reflective structure may be a metallic material, including but not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel ( Ni), platinum (Pt), tungsten (W), rhodium (Rh) or alloys of the above materials. The reflective structure may also be a distributed Bragg reflector (DBR), which is formed by stacking at least two layers of light-transmissive materials with different refractive indexes. The Bragg reflective structure may be an insulating material or a conductive material, and the insulating material includes but is not limited to polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), magnesium oxide (MgO), Su8 , Epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC ), polyetherimide (Polyetherimide), fluorocarbon polymer (Fluorocarbon Polymer), glass (Glass), aluminum oxide (Al ₂ O ₃ ), magnesium oxide (MgO), silicon oxide (SiO _x ), titanium oxide ( TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), silicon nitride (SiN _x ), spin-on-glass (SOG) or tetraethoxysilane (TEOS). Conductive materials include but are not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide ( ZTO), Gallium Zinc Oxide (GZO), Zinc Oxide (ZnO), Magnesium Oxide (MgO), Aluminum Gallium Arsenide (AlGaAs), Gallium Nitride (GaN), Gallium Phosphide (GaP) or Indium Zinc Oxide (IZO) . The reflective structure may also be an omnidirectional reflector (ODR) formed by the light-transmitting material layer and the metal layer.

FIG. 1D illustrates the light-emitting element 1 of Variation B in the first embodiment. The light-emitting element 1 of Variation B in the first embodiment is similar to Variation A, except that the upper surface TS1 and the first electrode 30 have the same width and pattern shape from the top view, and the area of the upper surface TS1 is the same as that of the first The bottom area of one electrode 30 is the same. The contact surface between the first electrode 30 and the semiconductor structure 20 includes the upper surface TS1 and the side surface LS1 of the first semiconductor layer 201, and the lower side surface LS2' of the second semiconductor layer 202 without contacting the second semiconductor layer 202 Surface TS2.

FIG. 2A is a variation C and D of a top view of a light-emitting element 2 disclosed in the second embodiment of the present application. FIG. 2B is a side view along the BB′ cross-section of Variation C in FIG. 2A. The light-emitting element 2 in the second embodiment is similar to the light-emitting element 1 except that the upper surface TS1 of the first semiconductor layer 201 in the modification C is a ring-shaped pattern when viewed from above. Increase compared to the light emitting element 1, the light emitting element 2 a first electrode 30 and the second semiconductor layer 202 in contact with the second contact region C ₂ area 201 and the first semiconductor layer in contact with the first contact area of regions C _{1 and} cut back.

Variation D is similar to Variation C, except that the upper surface TS1 of the first semiconductor layer 201 includes a plurality of regions from the top view; that is, the upper surface TS1 includes a ring-shaped pattern region TS1a and a ring-shaped region The middle area TS1b in the pattern area TS1a.

FIG. 3A is a variation E and F of a top view of a light-emitting element 3 disclosed in the third embodiment of the present application. Fig. 3B is a side view along the B-B' cross section of Modification E or Modification F. The light-emitting element 3 in the third embodiment is similar to the light-emitting element 1. The difference is that, from a top view, the upper surface TS1 of the first semiconductor layer 201 in Variations E and F includes two regions TS1' separated from each other, and this The two regions TS1' are separated by a portion of the first semiconductor layer 201 and the second semiconductor layer 202. Therefore, in the top view of this embodiment, the upper surface TS2 of the second semiconductor layer 202 in the shape of a strip is between the two regions TS1'. The upper surface TS2 of the strip-shaped second semiconductor layer 202 may be parallel to any edge 11 of the light emitting element 3 as shown in Modification E, or may be inclined to any edge 11 of the light emitting element 3 as shown in Modification F .

FIG. 4A is a variation G to K of a top view of a light-emitting element 4 disclosed in the fourth embodiment of the present application. The difference between the light-emitting elements 4 of the modified examples G to K is the exposed area 28, the contact surface below the first electrode 30; the structure of each layer except the exposed area 28 is the same. Fig. 4B is a side view along the B-B' cross section of the modification G in Fig. 4A, and Fig. 4C is a side view along the B-B' cross section of the modification J. The light-emitting element 3 in the third embodiment is similar to the light-emitting element 1. The difference is that, from a top view, the upper surface TS1 of the first semiconductor layer 201 in the modified examples G to K includes plural regions TS1' separated from each other, and this The plurality of regions TS1' are separated by the upper surface TS2 of the plurality of strip-shaped second semiconductor layers 202. The top surface TS2 of the strip-shaped second semiconductor layer 202 is viewed from above, as shown in the modification G, parallel or perpendicular to the side 11 of the light emitting element 4 and in a cross shape.

In Variation H of the present embodiment, the upper surface TS2 of the plurality of strip-shaped second semiconductor layers 202 is viewed from above and crosses and inclines to the side 11 of the light emitting element 3.

In Variation I of this embodiment, the number of complex regions TS1' is greater than Variation H. The upper surface TS2 of the plurality of strip-shaped second semiconductor layers 202 is viewed from above, in the shape of a "meter", The plural areas TS1' of the surface TS1 are arranged radially.

In Variation J of this embodiment, the upper surface TS2 of the plurality of strip-shaped second semiconductor layers 202 is arranged in a horizontal stripe as viewed from above, and the plurality of regions TS1' of the upper surface TS1 are also arranged in a horizontal stripe with each other . In another variation, the plurality of regions TS1' may also be arranged in stripes perpendicular to each other, or in stripes arranged parallel to each other and inclined to the side 11.

In Variation K of this embodiment, the upper surface TS2 of the plurality of strip-shaped second semiconductor layers 202 is arranged in a grid from a top view, so that the plurality of regions TS1 on the upper surface TS1 of each first semiconductor layer 201 'Arranged in an array.

Experiments were conducted with different first semiconductor layer 201 and second semiconductor layer 202 in combination with the light-emitting elements of the above-mentioned variations AK, and were compared with a control light-emitting element (not shown), in which the first electrode of the control light-emitting element Only a single n-type semiconductor layer was contacted. The best results of each set of experiments are listed in Table 1. In the experimental group No. 1, the first semiconductor layer 201 is n-type GaN with a silicon doping concentration of 2×10 ¹⁹ cm ^-3 , and the second semiconductor layer 202 is an n-type silicon with a doping concentration of 1.3×10 ¹⁹ cm ^-3 For GaN, the resistance of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202. Compared with the performance of the comparative light-emitting element, the light-emitting elements of the AK and the control light-emitting element with the variation of AK under the current density of 0.5-1.5 A/mm ² have higher photoelectric conversion efficiency (Wall Plug Efficiency, WPE), WPE increased by 1.47%-1.69% compared to the control light-emitting element. In the experiment group No. 2, the first semiconductor layer 201 is n-type GaN with a silicon doping concentration of 8×10 ¹⁸ cm ^-3 , and the second semiconductor layer 202 is an n-type with a silicon doping concentration of 1.3×10 ¹⁹ cm ^-3 For GaN, the resistance of the first semiconductor layer 201 is greater than that of the second semiconductor layer 202. The light-emitting element and the control light-emitting element of each modification under the operation of the current density of 0.5-1.5 A/mm ² , compared with the performance of the control light-emitting element, the light-emitting element with the modification A has a higher WPE, WPE than the control light-emitting element Increased by 1.2%; and the light-emitting device with variation K has a lower forward voltage (Vf), and Vf is reduced by 0.021-0.037V compared to the control light-emitting device. In the experiment group No. 3, when the first semiconductor layer 201 is n-type AlGaN with a silicon doping concentration of 2×10 ¹⁹ cm ^-3 , the second semiconductor layer 202 is an n-type silicon doping concentration of 7×10 ¹⁸ cm ^-3 Type GaN, the resistance of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202 at this time. The light-emitting element and the control light-emitting element of each modification under the operation of the current density of 0.5-1.5 A/mm ² , compared with the performance of the control light-emitting element, the light-emitting element with modification B has a higher WPE, WPE than the control light-emitting element Increased by 0.26%-0.41%; and the light-emitting device with Variation F has a lower Vf, which is 0.002-0.031V lower than the control light-emitting device. 【Table I】

FIG. 5A is a top view of a light-emitting element 5 disclosed in the fifth embodiment of the present application. Fig. 5B is a side view taken along the B-B' section in Fig. 5A. The structure of the light-emitting element 5 and the light-emitting element 1 outside the exposed area 28 is similar, and thus will not be described again. The difference is that the exposed area 28 of the light emitting element 5 is disposed on a short side 12 of the light emitting element 5 and extends along a long side 13; and the exposed area 28 is provided with a first electrode 30 including a first wire bonding pad 301 and a A first extended electrode 302 extended from a dozen wire pads 301. As in the previous embodiment, in addition to forming the upper surface TS1 of the first semiconductor layer 201 in the exposed area 28 of the corresponding position of the first bonding pad 301 by the etching method, the exposed area 28 of the corresponding position of the first extended electrode 302 can also be simultaneously The upper surface TS1 is also formed inside. As shown in FIGS. 5A and 5B, in the exposed region 28 in the long side 13 direction, the upper surface TS1 of the first semiconductor layer 201 includes a plurality of divided regions TS1′, and the plurality of regions TS1′ are arranged along the first extension electrode 302 . The contact area between the first extension electrode 301 and the semiconductor structure 20 includes a plurality of regions TS1' of the upper surface TS1 of the first semiconductor layer 201, the side surface LS1 of the first semiconductor layer 201, the upper surface TS2 of the second semiconductor layer, and the lower side surface LS2 '.

This embodiment is not limited to this. The exposed region 28 may be provided in any area within the semiconductor structure 20, the first electrode 30 may include one or more first extension electrodes 301, and the upper surface TS1 of the first semiconductor layer 201 may be provided in the first Below a dozen wire pads 301 and/or below the first extension electrode 301.

As in the light-emitting devices in the foregoing embodiments, the first semiconductor layer 201 and the second semiconductor layer 202 with different resistance values are used in combination with the upper surfaces TS1 and TS2 with different pattern shapes, so that the first electrode 30 and the first The first semiconductor layer 201 and the second semiconductor layer 202 have different contact areas and contact shapes, and at the same time, the first electrode 30 and the first semiconductor layer 201 and the second semiconductor layer 202 have different contact resistances. By adjusting the contact mode between the first electrode 30 and the first semiconductor layer 201 and the second semiconductor layer 202, the light emitting device has a lower forward voltage (forward voltage, Vf). For example, when the first electrode 30 has a larger contact area between the first semiconductor layer 201 and the second semiconductor layer 202 having a lower resistance value, the first electrode 30 and the overall semiconductor structure 20 have a lower contact resistance value .

FIG. 6 is a schematic diagram of a light-emitting device 6 disclosed in an embodiment of the application. Any one of the light emitting elements 1-5 in the foregoing embodiment is mounted on the first pad 511 and the second pad 512 of the package substrate 51. The first gasket 511 and the second gasket 512 are electrically insulated by an insulating portion 53 including an insulating material. In flip chip mounting, the side of the growth substrate opposite to the pad forming surface is set as the main light extraction surface. In order to increase the light extraction efficiency of the light emitting device, a reflective structure 54 may be provided around the light emitting element 1.

FIG. 7 is a schematic diagram of a light-emitting device 7 according to an embodiment of the invention. The light-emitting device 7 is a bulb lamp including a lamp cover 602, a reflector 604, a light-emitting module 610, a lamp holder 612, a heat sink 614, a connecting portion 616, and an electrical connection element 618. The light emitting module 610 includes a carrying portion 606, and a plurality of light emitting units 608 are located on the carrying portion 606, wherein the plurality of light emitting units 608 may be any of the light emitting elements 1-5 or the light emitting device 6 in the foregoing embodiment.

However, the above-mentioned embodiments are only illustrative for explaining the principle and effect of the present application, not for limiting the present application. Anyone with general knowledge in the technical field to which this application belongs can modify and change the above embodiments without violating the technical principles and spirit of this application. Therefore, the scope of protection of the rights in this application is listed in the scope of patent applications mentioned later.

1, 2, 3, 4, 5‧‧‧‧Lighting element 6, 7‧‧‧Lighting device 10‧‧‧Substrate 10a‧‧‧Upper surface 10b‧‧‧Lower surface 101‧‧‧Patterned structure 11‧‧‧ Side 12‧‧‧Short side 13‧‧‧Long side 18‧‧‧Transparent conductive layer 18a‧‧‧Opening of transparent conductive layer 20‧‧‧Semiconductor structure 201‧‧‧First semiconductor layer 202‧‧‧Second Semiconductor layer 203‧‧‧third semiconductor layer 204‧‧‧active layer 30‧‧‧first electrode 301‧‧‧first wire bonding pad 302‧‧‧first extension electrode 40‧‧‧second electrode 401‧‧‧ Second wire bonding pad 402‧‧‧Second extension electrode 51‧‧‧Package substrate 511‧‧‧First pad 512‧‧‧Second pad 53‧‧‧Insulation part 54‧‧‧Reflective structure 60‧‧‧ Current blocking layer 60a ‧‧‧ opening of current blocking layer 602 ‧ ‧ ‧ lamp cover 604 ‧ ‧ ‧ reflector 606 ‧ ‧ ‧ bearing part 608 ‧ ‧ ‧ light unit 610 ‧ ‧ ‧ light module 612 ‧ ‧ ‧ lamp holder 614 ‧ ‧‧ Heat sink 616‧‧‧Connecting part 618‧‧‧Electrical connection element C ₁ ‧‧‧ First contact area C ₂ ‧‧‧ Second contact area TS1‧‧‧Top surface of the first semiconductor layer TS1′‧‧ ‧ Complex area TS2‧‧‧ Upper surface LS1 of the second semiconductor layer ‧‧‧ Side surface LS2‧‧‧Upper side surface LS2′‧‧‧Lower side surface W ₁ ‧‧‧Width of upper surface TS1 W _N ‧‧‧ The width of the first electrode

﹝ FIGS. 1A to 1D ﹞ is a light-emitting element 1 according to an embodiment of the present application. ﹝ 2A to 2B ﹞ is a light-emitting element 2 of another embodiment of the present application. ﹝ FIGS. 3A to 3B ﹞ is a light-emitting element 3 according to another embodiment of the present application. ﹝ FIGS. 4A to 4C ﹞ are light-emitting elements 4 according to another embodiment of the present application. ﹝ 5A to 5B ﹞ is a light-emitting element 5 of another embodiment of the present application. ﹝Figure 6﹞ is a light-emitting device 6 according to an embodiment of the application. ﹝Figure 7﹞ is a light-emitting device 7 according to another embodiment of the application.

1‧‧‧Lighting element

10‧‧‧ substrate

10a‧‧‧upper surface

10b‧‧‧Lower surface

101‧‧‧patterned structure

18‧‧‧Transparent conductive layer

18a‧‧‧Opening of transparent conductive layer

20‧‧‧Semiconductor structure

201‧‧‧First semiconductor layer

202‧‧‧Second semiconductor layer

203‧‧‧third semiconductor layer

204‧‧‧active layer

30‧‧‧First electrode

40‧‧‧Second electrode

401‧‧‧ Second playing pad

402‧‧‧Second extension electrode

60‧‧‧Current blocking layer

60a‧‧‧Opening of current blocking layer

W ₁ ‧‧‧ Upper surface TS1 width

W _N ‧‧‧ The width of the first electrode

Claims (10)

A light-emitting device includes: a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; an active layer on the second semiconductor layer And the third semiconductor layer; an exposed region, through the third semiconductor layer and the active layer, exposing a first surface of the first semiconductor layer and a second surface of the second semiconductor layer, wherein The first surface includes a first side surface and a first upper surface; and a first electrode is located in the exposed area and contacts the first side surface, the first upper surface, and the second surface; wherein, The first semiconductor layer and the second semiconductor layer have different resistances. The light-emitting element according to item 1 of the patent application range, wherein the first semiconductor layer and the second semiconductor layer have the same conductive dopant with different doping concentrations. The light-emitting element as described in item 2 of the patent application range, wherein the first semiconductor layer and the second semiconductor layer contain the same material. The light-emitting element as described in item 1 of the patent application range, wherein the first semiconductor layer and the second semiconductor layer include different materials. The light-emitting element as described in item 1 of the patent application range, wherein the thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer. The light-emitting element according to item 1 of the patent application scope, wherein: the first upper surface includes a first contact area, which is in contact with the first electrode; and The second surface includes a second side surface and a second upper surface, wherein the second upper surface includes a second contact area, which is in contact with the first electrode. The light-emitting element according to item 6 of the patent application scope, wherein the first contact area and/or the second contact area include a pattern from above, and/or the area of the first contact area and the second The area of the contact area is different. The light-emitting element as described in item 7 of the patent application range, wherein the pattern includes a strip, a ring, or a geometric shape. The light-emitting element as described in item 6 of the patent application range, wherein the first contact area includes a plurality of first patterns as viewed from above, and the plurality of first patterns are separated by the second contact area. The light-emitting element according to item 1 of the patent application scope, wherein the first electrode has a larger contact area between the first semiconductor layer and the second semiconductor layer having a lower resistance value.

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