TWI691755B - Array substrate, display panel and display device - Google Patents

Abstract

Provided are an array substrate, a display panel, and a display device. The array substrate includes a base substrate and a picture element unit provided on the base substrate. The picture element unit includes a light-emitting layer and at least one first transistor disposed between the light-emitting layer and the base substrate, the first transistor including an active layer. The picture element unit further includes a light-shielding layer disposed between the light-emitting layer and the first transistor, and an orthographic projection of the light-shielding layer on the base substrate at least partially covers the first transistor An orthographic projection of the source layer on the base substrate.

Description

Array substrate, display panel and display device

The embodiments of the present disclosure relate to an array substrate, a display panel, and a display device.

Organic Light Emitting Diode (Organic Light Emitting Diode, referred to as OLED), especially Active-matrix Organic Light Emitting Diode (AMOLED), because of its high brightness, full viewing angle, response speed The advantages of fast and flexible display have been widely used in the field of display.

At present, in a display panel using AMOLED, the display area of the array substrate is usually provided with a plurality of picture element units in an array, each picture element unit includes an OLED and a picture element driving circuit connected to the OLED; each picture element driving circuit The first transistor in is used to provide a driving signal to the corresponding OLED to make the OLED emit light. However, the active layer of the first transistor is easily affected by the ambient light or the light emitted by the OLED, which deteriorates the conductive properties of the first transistor, such as the occurrence of poor conduction phenomena such as threshold voltage drift or increased leakage current Therefore, the array substrate where the first transistor is located is difficult to use reliably.

According to an embodiment of the present disclosure, an array substrate is provided. The array substrate includes a base substrate and a picture element unit provided on the base substrate. The picture element unit includes a light emitting layer and at least one first transistor disposed between the light emitting layer and the base substrate, the first transistor includes an active layer; the picture element unit further includes a A light-shielding layer between the light-emitting layer and the first transistor, an orthographic projection of the light-shielding layer on the base substrate at least partially covers an active layer of the first transistor on the base substrate Orthographic projection.

For example, the side of the light-emitting layer facing the first transistor is provided with an anode; the light-shielding layer includes a light-shielding electrode layer provided in the same layer as the anode.

For example, the light-shielding electrode layer is connected to the anode.

For example, the side of the light-emitting layer facing the first transistor is provided with an anode; the light-shielding layer includes a light-shielding metal layer disposed between the anode and the first transistor.

For example, the light shielding layer further includes a light shielding electrode layer provided in the same layer as the anode; an orthographic projection of the light shielding metal layer on the base substrate and an orthographic projection of the light shielding electrode layer on the base substrate Connected or partially overlapped.

For example, the array substrate further includes a signal line; the light-shielding metal layer is provided in the same layer as the signal line and connected to the signal line.

For example, the picture element unit further includes: at least one second transistor electrically connected to the first transistor, and a passivation layer covering the first transistor and the second transistor; the signal line The source electrode of the second transistor is connected through the via hole provided in the passivation layer.

For example, the picture element unit further includes a storage capacitor including a first electrode plate and a second electrode plate sequentially arranged on the base substrate; the orthographic projection of the light-shielding metal layer on the base substrate At least partially overlaps with the orthographic projection of the second polar plate on the base substrate.

For example, the array substrate includes a plurality of picture element units arranged on the base substrate in an array. In each of the picture element units, the side of the light-emitting layer facing the first transistor is provided with an anode; the plurality of picture element units includes at least two picture element units to display at least two different colors; In the picture element unit displaying one color, the light-shielding layer includes a light-shielding electrode layer provided in the same layer as the anode; in the picture element unit displaying another color, the light-shielding layer includes the anode and all The light-shielding metal layer between the first transistors.

For example, the array substrate includes a plurality of picture element units arranged on the base substrate in an array manner, wherein the minimum spacing between the light shielding layers in each two adjacent picture element units is 2μm~10μm.

For example, the first transistor is a driving transistor directly connected to the anode.

According to an embodiment of the present disclosure, there is provided a display panel including the array substrate as described above.

According to an embodiment of the present disclosure, there is provided a display device including the display panel as described above.

To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described clearly and completely in conjunction with the drawings. Obviously, the described embodiments are a part of the embodiments of the present disclosure, but not all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.

Unless otherwise defined, the technical or scientific terms used herein shall have the usual meanings understood by those of ordinary skill in the field to which this disclosure belongs. The terms "first", "second" and similar words used in this disclosure and the scope of patent application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similar words such as "include" or "include" mean that the elements or objects before "include" or "include" cover the elements or objects listed after "include" or "include" and their equivalents, and do not exclude other Components or objects. "Up", "down", "left", "right", etc. are only used to indicate the relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

Please refer to FIGS. 1 to 9, an embodiment of the present disclosure provides an array substrate including a base substrate 1 and a picture element unit provided on the base substrate 1; the picture element unit includes a light emitting layer 22 and At least one first transistor 3 disposed between the light-emitting layer 22 and the base substrate 1, the first transistor 3 includes an active layer 31; the picture element unit further includes one disposed between the light-emitting layer 22 and the first transistor 3 The orthographic projection of the light shielding layer on the base substrate 1 at least partially covers the orthographic projection of the active layer 31 of the first transistor 3 on the base substrate 1.

For example, the array substrate provided by the embodiment of the present disclosure includes a plurality of the picture element units arranged on the base substrate 1 in an array manner; each picture element unit includes a light emitting layer 22, at least one first transistor 3, and a light shielding layer; In the same picture element unit, the orthographic projection of the light shielding layer on the base substrate 1 at least partially covers the orthographic projection of the active layer 31 of the first transistor 3 on the base substrate 1.

For example, the array substrate provided by the embodiment of the present disclosure is an OLED array substrate, and the substrate substrate 1 of the OLED array substrate may be a glass substrate or a flexible substrate; each picture element unit of the OLED array substrate is provided with an OLED 2. The OLED 2 includes, for example, an anode 21 and a cathode 23 arranged oppositely, and a light-emitting layer 22 formed between the anode 21 and the cathode 23. The light-emitting layer 22 may have a single-layer structure, for example, the light-emitting layer 22 only includes an organic light-emitting layer disposed between the anode 21 and the cathode 23; the light-emitting layer 22 may also have a multilayer structure, for example, the light-emitting layer 22 includes the anode 21 and the cathode 23 Between the hole transport layer, the organic light-emitting layer and the electron transport layer.

The orthographic projection of the light shielding layer on the base substrate 1 at least partially covers the orthographic projection of the active layer 31 of the first transistor 3 on the base substrate 1, for example, includes one of the following situations: the orthographic projection of the light shielding layer on the base substrate 1 The projection completely overlaps or substantially overlaps the orthographic projection of the active layer 31 of the first transistor 3 on the base substrate 1 in the same picture element unit; the orthographic projection of the shading layer on the substrate substrate 1 is the same as the first projection in the same picture element unit The active layer 31 of a transistor 3 partially overlaps in the orthographic projection of the base substrate 1; the orthographic projection of the active layer 31 of the first transistor 3 on the base substrate 1 in the same picture element unit is located in the shading layer on the base substrate Within 1 of the orthographic projection.

For example, the OLED 2 in each picture element unit drives and emits light through the picture element drive circuit. The pixel driving circuit includes at least one switching transistor, at least one driving transistor, and at least one storage capacitor. For example, the above-described first transistor 3 provided between the light-emitting layer 22 and the base substrate 1 of the embodiment of the present disclosure functions as a driving transistor. Further, for example, the above-mentioned first transistor 3 provided between the light-emitting layer 22 and the base substrate 1 in the embodiment of the present disclosure refers to the driving transistor directly connected to the anode 21 in the picture element driving circuit corresponding to the OLED 2 The number of the first transistor 3 may be one or more. Of course, in some embodiments, the orthographic projection of the light-shielding layer on the base substrate 1 may further at least partially cover the orthographic projection of the active layer of the second transistor in the same picture element unit on the substrate substrate 1, in order to ensure the corresponding Conductivity of two transistors. For example, the second transistor is used as a switching transistor.

In the array substrate provided by the embodiment of the present disclosure, a light-shielding layer is provided between the light-emitting layer 22 and the corresponding first transistor 3, and the orthographic projection of the light-shielding layer on the base substrate 1 at least partially covers the first element in the same picture element unit The orthographic projection of the active layer 31 of the transistor 3 on the base substrate 1, the light shielding layer can be used to shield the active layer 31 of the first transistor 3 in the same picture element unit to avoid ambient light or the light-emitting layer 22 The outgoing light of is irradiated to the active layer 31 of the first transistor 3 to ensure that the active layer 31 of the first transistor 3 will not affect its conductive performance due to light, that is, no leakage current will be generated due to light, resulting in the first Poor conduction phenomena such as a threshold voltage shift of the transistor 3 are beneficial to improve the conduction stability of the first transistor 3 and further improve the reliability of use of the array substrate.

The arrangement of the above-mentioned light-shielding layer in the array substrate may have various implementation forms, which will be described in detail below with reference to the drawings.

It should be noted that the following embodiments are only exemplary embodiments of the present disclosure and should not be construed as limiting the scope of the present disclosure.

It should be noted that, in the following description, the same or similar parts between the various embodiments may refer to each other.

Please refer to FIGS. 1-3. In the array substrate provided by the embodiment of the present disclosure, the light-emitting layer 22 is provided with an anode 21 on the side facing the first transistor 3; the light-shielding layer includes a light-shielding electrode layer provided on the same layer as the anode 21 41. The light-shielding electrode layer 41 and the anode 21 are provided in the same layer. When the anode 21 is made of a light-shielding material such as a metal material, the light-shielding electrode layer 41 and the anode 21 can be formed by using the same material in one patterning process, simplifying the manufacturing process.

Further, for example, the light-shielding electrode layer 41 is connected to the anode 21. In this case, the light-shielding electrode layer 41 may be provided integrally with the anode 21, that is, the light-shielding electrode layer 41 may be regarded as an extension of the anode 21. The embodiment of the present disclosure uses the extension of the anode 21 as the light-shielding electrode layer 41, which is not only convenient for manufacturing and easy to improve production efficiency, but also can effectively improve the space utilization rate of the picture element unit where the OLED is located, so as to achieve high-resolution display of the array substrate. Furthermore, the display effect of the array substrate is improved.

In addition, in the array substrate provided by the embodiment of the present disclosure, the pixel driving circuit corresponding to the anode 21 includes, for example, at least one switching transistor T1, at least one driving transistor T2, and at least one storage capacitor. For example, the above-mentioned first transistor 3 is used as the driving transistor T2, and the above-mentioned second transistor is used as the switching transistor T1. For example, the switching transistor T1 and the driving transistor T2 use the same top gate structure, and each includes: an active layer 31, a first gate insulating layer 35, a gate electrode 34, and a second gate which are sequentially stacked on the base substrate 1 The insulating layer 36 and the interlayer insulating layer 37 are provided with a source electrode 32 and a drain electrode 33 on the surface facing away from the base substrate 1, and the source electrode 32 and the drain electrode 33 are respectively connected to the active layer 31 through corresponding via holes . The first plate C1 of the storage capacitor and the gate electrode 34 are arranged in the same layer, and the second plate C2 of the storage capacitor is disposed between the second gate insulating layer 36 and the interlayer insulating layer 37 and is opposite to the first plate C1. It can be understood that, before forming the active layer 31 of the switching transistor T1 and the driving transistor T2, the above-mentioned array substrate usually also has a buffer layer 5 formed thereon.

For example, when the array substrate shown in FIGS. 1 and 2 is manufactured, the manufacturing method is shown in FIG. 3:

In step S1, a base substrate 1 is provided, and a buffer layer 5 and an active layer 31 are sequentially stacked on the base substrate 1.

For example, the above base substrate 1 may be a flexible substrate, which is formed by laminating a first polyimide film (PI layer), a first barrier layer, a second PI layer, and a second barrier layer.

For example, the above-mentioned buffer layer 5 is formed by stacking silicon nitride (SiNX) and silicon dioxide (SiO2), for example, it may be formed by plasma enhanced chemical vapor deposition (PECVD process).

For example, the above-mentioned active layer 31 is formed through a patterned polysilicon (p-Si) thin film. For example, the formation process of the active layer 31 is: forming an amorphous silicon (a-Si) thin film on the surface of the buffer layer 5 facing away from the base substrate 1; performing laser annealing on the amorphous silicon (a-Si) thin film (for example, Excimer laser annealing, Excimer Laser Annealing (ELA) or Solid Phase Crystallization (SPC) treatment to obtain polycrystalline silicon (p-Si) film; patterning polycrystalline silicon (p-Si) film to obtain active Layer 31, and ion doping the active layer 31 using an ion implantation process.

Step S2, forming a first gate insulating layer 35 on the surface of the buffer layer 5 not covered by the active layer 31 and the surface of the active layer 31 facing away from the buffer layer 5; forming the first gate insulating layer 35 on the surface of the first gate insulating layer 35 facing away from the buffer layer 5 A layer of metal film, patterning the first layer of metal film using a photolithography process to form the gate electrode 34 of the switching transistor T1 and the driving transistor T2 and the first electrode of the storage capacitor on the first gate insulating layer 35 Board C1.

Step S3, forming a second gate insulating layer 36 on the first gate insulating layer 35, the gate electrode 34 and the first plate C1 of the storage capacitor; forming a second gate insulating layer 36 on the surface of the second gate insulating layer 36 facing away from the first gate insulating layer 35 A two-layer metal film, using a photolithography process to pattern the second metal film to form a second plate C2 of a storage capacitor on the surface of the second gate insulating layer 36, the second plate C2 and the previously formed first plate One plate C1 is opposite.

For example, the first gate insulating layer 35 and the second gate insulating layer 36 are formed of a silicon dioxide (SiO2) film layer, or a stack of silicon nitride (SiNX) and silicon dioxide (SiO2), for example, a PECVD process may be used Production formation.

For example, the first metal thin film and the second metal thin film can be made of metal materials with low resistance such as aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), or aluminum neodymium alloy (AlNd) It is preferable to use molybdenum (Mo) metal material for production and formation, and it can be produced by, for example, a magnetron sputtering process or an evaporation process.

Step S4, an interlayer insulating layer 37 is formed on the surface of the second gate insulating layer 36 that is not covered by the second electrode plate C2, and the surface of the second electrode plate C2 facing away from the second gate insulating layer 36; Via holes are formed in the gate insulating layer 36 and the first gate insulating layer 35, and the via holes expose a part of the active layer 31.

For example, the above-mentioned interlayer insulating layer 37 is formed by a stack of silicon dioxide (SiO 2) and silicon nitride (SiNX), for example, it can be formed by a PECVD process.

Step S5, for example, using a magnetron sputtering process to form a third metal film on the surface of the interlayer insulating layer 37 facing away from the second gate insulating layer 36; using a photolithography process to pattern the third metal film to form an interlayer insulating layer The source 32 and the drain 33 of the switching transistor T1 and the driving transistor T2 are formed on the 37; the source 32 and the drain 33 of the switching transistor T1 and the driving transistor T2 are respectively connected to the corresponding active layer 31 through the via And the drain of the switching transistor T1 is also connected to the source of the driving transistor T2.

For example, the third-layer metal thin film may be a single-layer metal thin film formed of aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), or aluminum neodymium alloy (AlNd), or alternatively, aluminum (Al ), copper (Cu), molybdenum (Mo), titanium (Ti) or aluminum neodymium alloy (AlNd) multilayer metal film, such as: molybdenum/aluminum/molybdenum (Mo/Al/Mo) film, titanium/aluminum/titanium (Ti/Al/Ti) film etc.

Step S6, a passivation layer 6 and a planarization layer 7 are sequentially stacked on the interlayer insulating layer 37 and the source 32 and the drain 33 of the switching transistor T1 and the driving transistor T2; using a photolithography process, the passivation layer 6 and the planarization layer 7 are formed. A via hole is formed in the metallization layer 7, and the via hole exposes the drain of the driving transistor T2.

For example, the above-mentioned passivation layer 6 is formed of a silicon nitride (SiNX) film layer, which can be formed by PECVD, for example. For example, the planarization layer 7 is formed of a polyimide film (Polyimide Film, PI film for short).

For example, after the passivation layer 6 and the planarization layer 7 are completed, the array substrate may be subjected to rapid thermal annealing or heat treatment furnace annealing to activate the doped ions of the active layer 31 in the array substrate and to the active layer 31 is hydrogenated to repair the lattice defects of the active layer 31.

Step S7, forming a light-shielding conductive film on the surface of the planarization layer 7 facing away from the passivation layer 6; patterning the light-shielding conductive film using a photolithography process to form an anode 21 and a light-shielding electrode connected to the anode 21 on the planarization layer 7 Layer 41. The anode 21 is connected to the drain of the driving transistor T2 through the via. For example, the orthographic projection of the light-shielding electrode layer 41 on the base substrate 1 completely covers the orthographic projection of the active layer 31 of the driving transistor T2 on the base substrate 1.

In step S8, on the planarization layer 7, the anode 21 and the light-shielding electrode layer 41, a picture element defining layer 8, a light emitting layer 22, and a cathode 23 are formed in this order.

For example, the above picture element defining layer 8 is formed of a polyimide film (Polyimide Film, PI film for short).

It can be understood that the manufacturing materials of each functional film layer and the thickness of its formation in the embodiments of the present disclosure can be set according to actual needs; the embodiments of the present disclosure provide an example exemplarily, see Table 1 for details.

Table I

For example, referring to FIGS. 4-6, in the array substrate provided by the embodiment of the present disclosure, the first transistor 3 includes an active layer 31, a first gate insulating layer 35, and a gate stacked on the base substrate 1 in this order. The electrode 34, the second gate insulating layer 36, and the interlayer insulating layer 37. The surface of the interlayer insulating layer 37 facing away from the base substrate 1 is provided with a source electrode 32 and a drain electrode 33. The source electrode 32 and the drain electrode 33 respectively pass through corresponding via holes It is connected to the active layer 31. For example, the light shielding layer includes a light shielding metal layer 42 disposed between the anode 21 and the first transistor 3. For example, the surfaces of the source electrode 32 and the drain electrode 33 of the first transistor 3 are stacked in this order to form the passivation layer 6 and the planarization layer 7, and the light-shielding metal layer 42 is formed between the passivation layer 6 and the planarization layer 7.

In the array substrate provided by the embodiment of the present disclosure, a light-shielding metal layer 42 is provided between the first transistor 3 and the light-emitting layer 22 as a light-shielding layer. The light-shielding metal layer 42 can shield the first transistor 3 while shielding the metal The orthographic projection of the layer 42 on the base substrate 1 and the orthographic projection of the second plate C2 on the base substrate 1 at least partially overlap to form an auxiliary storage capacitor from the light-shielding metal layer 42 and the second plate C2, thereby increasing storage in the array substrate The total capacitance value of the capacitor ensures that the driving voltage of the first transistor 3 is stable, which further improves the use reliability of the array substrate.

In addition, in the array substrate provided in this embodiment, by providing a light-shielding metal layer 42 between the anode 21 and the first transistor 3, it is also possible to avoid the use of the anode 21 to form a light-shielding layer to ensure that each picture element unit There is a large gap between the anodes 21; when the above-mentioned light-shielding metal layer 42 is formed as a light-shielding layer in an array substrate with high display resolution, the risk of short-circuiting between the anodes 21 in different picture element units can be reduced, which is beneficial to increase Production yield of array substrates.

For example, please continue to refer to FIG. 4, the array substrate provided by the embodiment of the present disclosure further includes a signal line (for example, a power signal line VDD), the signal line is connected to the source electrode 32 of the switching transistor T1; the light-shielding metal layer 42 may be connected to the signal line Set on the same level. In the embodiments of the present disclosure, the signal lines and the light-shielding metal layer 42 are arranged in the same layer, which is convenient for forming the signal line and the light-shielding metal layer 42 in one photolithography process, which is beneficial to simplify the manufacturing process of the array substrate and improve the production efficiency. For example, referring back to FIG. 4, the light-shielding metal layer 42 can be connected to the signal line to further simplify the manufacturing process, and realize the light-shielding metal layer 42 in parallel with the source of the switching transistor T1 to ensure the light-shielding metal layer 42 and the second plate C2 An auxiliary storage capacitor is formed to further improve the reliability of the array substrate.

For example, please continue to refer to FIG. 4, in the array substrate provided by the embodiment of the present disclosure, each picture element unit further includes at least one switching transistor T1 electrically connected to the driving transistor T2; the switching transistor T1 and the driving transistor T2 For example, thin-film transistors with the same structure have the same manufacturing process.

For example, when the array substrate shown in FIGS. 4 and 5 is manufactured, the manufacturing method may be as shown in FIG. 6:

In step S1', a switching transistor T1 and a driving transistor T2 are formed on the base substrate 1.

Step S2', a passivation layer 6 is formed on the source 32 and the drain 33 of the switching transistor T1 and the driving transistor T2; a via is formed in the passivation layer 6 through a photolithography process, the via exposes the switching transistor T1 Source electrode 32.

For example, the above-mentioned passivation layer is formed of a silicon nitride (SiNX) film layer, which can be formed by a PECVD process, for example. After the passivation layer 6 is completed, the array substrate may be subjected to rapid thermal annealing or heat treatment furnace annealing to activate the doped ions of the active layer 31 in the array substrate and hydrogenate the active layer 31 to repair The lattice defect of the active layer 31.

Step S3', for example, using a magnetron sputtering process to form a metal thin film on the surface of the passivation layer 6 facing away from the base substrate 1; using a photolithography process to pattern the metal thin film to form signal lines on the passivation layer 6 and The light-shielding metal layer 42 to which the signal line is connected; the signal line is connected to the source electrode 32 of the switching transistor T1 through the via hole provided in the passivation layer 6.

For example, the light-shielding metal layer 42 is formed of a laminated metal thin film of titanium/aluminum/titanium (Ti/Al/Ti); the orthographic projection of the light-shielding metal layer 42 on the base substrate 1 at least partially covers the driving transistor T2 The orthographic projection of the source layer 31 on the base substrate 1.

Step S4', a planarization layer 7 is formed on the passivation layer 6 and the signal line and the light-shielding metal layer 42; a photolithography process is used to form a via hole in the passivation layer 6 and the planarization layer 7, the via hole exposing the first transistor T2's drain 33.

For example, the planarization layer 7 is formed of a polyimide film (Polyimide Film, PI film for short).

Step S5', a conductive film is formed on the surface of the planarization layer 7 facing away from the passivation layer 6; the conductive film is patterned using a photolithography process to form an anode 21 on the planarization layer 7. On the planarization layer 7 and the anode 21, a picture element defining layer 8, a light emitting layer 22, and a cathode 23 are formed in this order.

For example, the conductive film may be a single-layer conductive film formed of oxides such as indium tin oxide (ITO) or indium zinc oxide (IZO), or indium tin oxide/silver/indium tin oxide (ITO/Ag/ITO) Or indium zinc oxide/silver (IZO/Ag) and other composite films. For example, the embodiments of the present disclosure use an indium tin oxide/silver/indium tin oxide (ITO/Ag/ITO) composite film to form the anode 21 to ensure that the anode 21 has relatively good conductive properties. For example, the above picture element defining layer 8 may be formed of a polyimide film (Polyimide Film, PI film for short).

It can be understood that the manufacturing materials and the forming thickness of each functional film layer in the embodiments of the present disclosure can be set according to actual needs; the embodiments of the present disclosure exemplarily provide a specific example, see Table 2 for details.

Table II

For example, referring to FIGS. 7 and 8, in the array substrate provided by the embodiment of the present disclosure, the light-shielding layer may include both the light-shielding metal layer 42 and the light-shielding electrode layer 41, that is, the light-shielding layer in the at least one picture element unit, namely It includes a light-shielding metal layer 42 disposed between the anode 21 and the first transistor 3, and further includes a light-shielding electrode layer 41 disposed in the same layer as the anode 21. For example, as shown in FIG. 7, the orthographic projection of the light-shielding metal layer 42 on the base substrate 1 may be in contact with the orthographic projection of the light-shielding electrode layer 41 on the base substrate 1. For example, as shown in FIG. 8, the orthographic projection of the light-shielding metal layer 42 on the base substrate 1 may overlap with the orthographic projection of the light-shielding electrode layer 41 on the base substrate 1.

For example, the orthographic projection of the light-shielding metal layer 42 on the base substrate 1 and the orthographic projection of the light-shielding electrode layer 41 on the base substrate 1 are expressed as follows: the light-shielding metal layer 42 is on the side of the orthographic projection of the base substrate 1 The edges of the orthographic projection of the light-shielding electrode layer 41 on the base substrate 1 are in contact with each other, and there is no overlap between the orthographic projections of the light-shielding metal layer 42 and the light-shielding electrode layer 41 on the base substrate 1, such as As shown in Figure 7. For example, the orthographic projection of the light-shielding metal layer 42 on the base substrate 1 overlaps with the orthographic projection of the light-shielding electrode layer 41 on the base substrate 1 as follows: both the light-shielding metal layer 42 and the light-shielding electrode layer 41 are on the base substrate 1 The orthographic projection of has overlapping parts, as shown in Figure 8.

In order to ensure that the shading layer can have a better shading effect, the specific setting of the shading layer can be reasonably set according to actual needs. The embodiment of the present disclosure uses both the light-shielding electrode layer 41 and the light-shielding metal layer 42 to form a light-shielding layer, which can take into account the advantages of the light-shielding electrode layer 41 and the light-shielding metal layer 42.

When the array substrate provided by the embodiment of the present disclosure adopts the structure shown in FIG. 8, the manufacturing method thereof is shown in FIG. 9. For the manufacturing steps of the manufacturing method, refer to FIGS. 3 and 6, and details are not described herein.

For example, in the array substrate provided by the embodiment of the present disclosure, the plurality of picture element units may be divided into at least two picture element units according to different display colors to display at least two different colors. For example, in the embodiments of the present disclosure, according to different picture element units, a light-shielding layer may be reasonably arranged in each picture element unit, for example, in a picture element unit displaying a color, a light-shielding layer provided on the same layer as the anode and connected to the anode The electrode layer serves as a light-shielding layer; in the picture element unit displaying another color, the light-shielding metal layer provided between the anode and the first thin film transistor is used as the light-shielding layer.

Exemplarily, please refer to FIG. 10, an array substrate provided by an embodiment of the present disclosure uses RGB color mode for display. The plurality of picture element units of the array substrate includes a plurality of R picture element units, a plurality of G picture element units, and a plurality of B primitive unit. In order to effectively improve the display resolution of the array substrate, the plurality of R picture element units, the plurality of G picture element units, and the plurality of B picture element units are generally distributed using the “product” shape structure shown in FIG. 10; For example, according to the location of each picture element unit, a light-shielding electrode layer with the same layer as the anode can be provided as a light-shielding layer in each G picture element unit, and the anode can be provided in the R picture element unit and/or B picture element unit The light shielding metal layer between the first thin film transistor and the light shielding metal layer serves as a light shielding layer. For example, the word "product" as described above can be expressed as: in the direction in which the repeating units composed of the R unit, the G unit, and the B unit are periodically arranged (for example, the horizontal direction in FIG. 10), The R primitive unit and the B primitive unit are aligned, while the G primitive unit is not aligned with the R primitive unit and the B primitive unit.

The array substrate provided by the embodiments of the present disclosure can selectively use the light-shielding electrode layer as a light-shielding layer or the light-shielding metal layer as a light-shielding layer according to different distributions of picture element units of different colors, so as to reasonably set light-shielding in each picture element unit In order to efficiently use the pixel space of the array substrate, and to achieve high-resolution display of the array substrate, to ensure that the array substrate has a high reliability of use.

In order to ensure that the light-shielding layers in each picture element unit are independent of each other, for example, in the embodiment of the present disclosure, the minimum spacing between the light-shielding layers in each adjacent two picture element units is 2 μm to 10 μm, preferably 4 μm. The array substrate provided by the embodiment of the present disclosure can not only ensure that the shading layers in each picture element unit are independent of each other by defining the minimum spacing between the shading layers in each adjacent two picture element units, but also facilitate the fabrication; The short circuit and other defects due to the too small distance between them are beneficial to improve the reliability of the array substrate.

An embodiment of the present disclosure also provides a display panel including the array substrate according to the embodiment of the present disclosure as described above. The array substrate in the display panel has the same advantages as the array substrate according to the embodiments of the present disclosure as described above, and will not be repeated here.

An embodiment of the present disclosure also provides a display device including the display panel provided by the embodiment of the present disclosure. The display panel in the display device has the same advantages as the display panel in the embodiments of the present disclosure, which will not be repeated here.

The above is only an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure, which is determined by the appended claims.

1: substrate substrate, 2: OLED, 21: anode, 22: light-emitting layer, 23: cathode, 3: first transistor, 31: active layer, 32: source, 33: drain, 34: gate , 35: first gate insulating layer, 36: second gate insulating layer, 37: interlayer insulating layer, 41: light-shielding electrode layer, 42: light-shielding metal layer, 5: buffer layer, 6: passivation layer, 7: planarization layer , 8: primitive definition layer, S1~S8, S1'~S5': steps.

In order to more clearly explain the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings of the embodiments of the present disclosure. Obviously, the drawings described below only relate to some embodiments of the present disclosure, rather than limiting the present disclosure . 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure; FIG. 2 is a partial cross-sectional view of the array substrate shown in FIG. 1; FIG. 3 is a schematic flowchart of a manufacturing method of the array substrate shown in FIG. 1; FIG. 4 is an implementation of the present disclosure 5 is a partial cross-sectional view of the array substrate shown in FIG. 4; FIG. 6 is a schematic flow chart of the manufacturing method of the array substrate shown in FIG. 4; FIG. 7 is an array provided by an embodiment of the present disclosure Another structural schematic diagram of the substrate; FIG. 8 is another schematic structural diagram of the array substrate provided by the embodiment of the present disclosure; FIG. 9 is a schematic flowchart of the manufacturing method of the array substrate shown in FIG. 8; FIG. 10 is an array provided by the embodiment of the present disclosure Schematic diagram of another structure of the substrate.

1: substrate substrate, 2: OLED, 21: anode, 22: light-emitting layer, 23: cathode, 3: first transistor, 31: active layer, 32: source, 33: drain, 34: gate , 35: first gate insulating layer, 36: second gate insulating layer, 37: interlayer insulating layer, 41: light-shielding electrode layer, 5: buffer layer, 6: passivation layer, 7: planarization layer, 8: picture element definition Layer, T1, T2: transistors, C1, C2: plates.

Claims (12)

An array substrate includes a base substrate and a picture element unit provided on the base substrate, wherein the picture element unit includes a light emitting layer; at least one provided between the light emitting layer and the base substrate A first transistor including an active layer; and a light-shielding layer disposed between the light-emitting layer and the first transistor, the light-shielding layer being at least partially orthographically projected on the base substrate The active layer covering the first transistor is orthographically projected on the base substrate; the light-emitting layer is provided with an anode on the side facing the first transistor; the light-shielding layer includes the same layer as the anode The shading electrode layer is provided. The array substrate according to item 1 of the patent application scope, wherein the light-shielding electrode layer is connected to the anode. The array substrate according to item 1 of the patent application range, wherein the light-shielding layer further includes a light-shielding metal layer disposed between the anode and the first transistor. The array substrate of claim 3, wherein the orthographic projection of the light-shielding metal layer on the base substrate is in contact with or partially overlaps with the orthographic projection of the light-shielding electrode layer on the base substrate. The array substrate according to item 3 of the patent application scope further includes a signal line, wherein the light-shielding metal layer is provided in the same layer as the signal line and connected to the signal line. The array substrate according to item 5 of the patent application scope, wherein the picture element unit further includes: at least one second transistor electrically connected to the first transistor, and covering the first transistor and all A passivation layer of the second transistor; the signal line passes through the via hole provided in the passivation layer and the source phase of the second transistor even. The array substrate according to item 5 of the patent application scope, wherein the picture element unit further includes a storage capacitor including a first electrode plate and a second electrode plate sequentially arranged on the base substrate; The orthographic projection of the light-shielding metal layer on the base substrate and the orthographic projection of the second polar plate on the base substrate at least partially overlap. The array substrate as described in item 1 of the patent application scope includes a plurality of picture element units arranged on the base substrate in an array manner, wherein in each picture element unit, the anode is provided at The light-emitting layer faces a side of the first transistor; the plurality of picture element units includes at least two picture element units to display at least two different colors; in picture element units displaying one color, the The light-shielding layer includes the light-shielding electrode layer provided in the same layer as the anode; in a picture element unit displaying another color, the light-shielding layer includes a light-shielding metal disposed between the anode and the first transistor Floor. The array substrate according to any one of items 1 to 8 of the patent application range, including a plurality of the picture element units arranged on the base substrate in an array manner, wherein each adjacent two The minimum distance between the light-shielding layers in the picture element unit is 2 μm to 10 μm. The array substrate according to any one of items 1 to 8 of the patent application range, wherein the first transistor is a driving transistor directly connected to the anode. A display panel includes the array substrate according to any one of items 1-10 of the patent application range. A display device includes a display panel as described in item 11 of the patent application scope.

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